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Gowin HyperRAM Memory Interface
Introduction
Gowin HyperRAM Memory Interface IP is a common used HyperRAM interface IP, in compliance with HyperRAM standard protocol. The IP includes the HyperRAM MCL (Memory Controller Logic) and the
corresponding PHY (Physical Interface) design. Gowin HyperRAM Memory Interface IP provides you a common command interface to connect with the HyperRAM chip for data access and storage.
Features
- Compatible with interfaces of standard HyperRAM devices
- Supports memory data path width of 8 bits, 16 bits, 24 bits, 32 bits
- Supports x8 data width memory chip
- Programs 16, 32, 64 or 128 burst lengths
- The clock rate is 1:2
- Supports the initial latency of 3, 4, 5, 6, 7, 8
- Supports the fixed latency mode
- Supports the power off option
- Configurable drive strength
- Configurable self-refresh area
- Configurable refresh rate
- The clock interface can be configured as single-ended or differential