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GOWIN AHB BUS ARBITER

Gowin AHB Bus Arbiter includes 16 Master device interfaces and one Slave device interface. Master device can be the MCU (Such as
Gowin_EMPU_M1) or the FPGA logic modules with AHB bus protocol interfaces. Slave device can be the FPGA logic modules in accordance with the AHB bus protocol. The base address is 0x80000000.
Gowin AHB Bus Arbiter supports 32-bit standard AHB bus bit width and enhanced 64-bit AHB bus bit width, offering high speed and high bandwidth data communication.
The 16 Master device interfaces of Gowin AHB Bus Arbiter offer fixed priority arbitration. The priority is from high to low in turn from the first Master device interface to the 16th Master device interface.

 

Features

Gowin AHB Bus Arbiter features are as follows:

  • Offers 16 Master device interfaces and one Slave device interface;
  • Master device can be the MCU or the FPGA logic modules with AHB bus protocol interfaces;
  • Supports 32-bit standard AHB bus bit width and enhanced 64-bit AHB bus bit width;
  • Supports priority arbitration of the 16 Master device interfaces; the priority is from high to low in turn.
Documents Download
User Guide Gowin AHB Bus Arbiter IP User Guide Download
Release Note Gowin AHB Bus Arbiter IP Release Note Download