GOWIN now offers an Image Signal Processor (ISP) pipeline and AE/AWB coprocessor which accepts a raw Bayer input stream generated by image sensor and outputs RGB stream with improved image quality for display or recognition purposes. The ISP takes the pixel data in Bayer format and adjusts it through CFA, CCM, and Gamma correction modules, and AEAWB module based on accumulated data in the statistics and histogram engines to provide a clear image which is balanced in color and brightness.

GOWIN now offers multiple USB interface solutions including a USB v2.0 soft PHY and USB v2.0 Device Controller (SIE).  The USB 2.0 interface solution is supported on all GOWIN FPGAs (with exception to the 1NZ) providing a line rate of 480Mbps in USB High Speed mode.  The USB PHY and Device Controller allows GOWIN FPGA designers to easily integrate USB connectivity to their end products without the need for additional silicon ICs or devices.  GOWIN’s USB solution is useful for virtually every market segment including consumer, automotive, industrial and communications.

GOWIN provides USB solutions for v1.1 'Full Speed' and 'High Speed' v2.0 modes.  USB v1.1 operates with a line rate of 12Mbps, which is suitable for control and configuration type applications.  USB v2.0 operates with a line rate of 480Mbps, which is used for data streaming applications.

GOWIN's USB IP's are available in the latest version of GOWIN EDA's IP core generator, which provides a configuration GUI for the PHY as well as the device controller.  Once the IP is generated with the desired configuration the PHY and device controller can be instantiated in a design to provide one or more USB interfaces.  Please note, external PCB requirements are needed for this IP to work properly.

To evaluate the USB v2.0 Soft PHY and Device Controller IPs, GOWIN provides a USB v2.0 reference design targeting the DK-Start USB 2.0 GW2AR18 development board.  The board provides a USB connector along with appropriate trace matching and circuitry to communicate data over USB at High Speed data rates.  The reference design configures the device controller as a VCP (Virtual COM Port) and initializes with native USB serial device drivers on Microsoft Windows and Linux.  The reference design provides an example of a USB to UART bridge with a loop back on the UART data.  Data is transmitted from a computer’s USB port to UART TX and then looped back from UART RX to USB to return the same data back to the computer.  Using a serial port terminal program, developers can type characters on their computer and have it returned to them in the console window.

GOWIN uSoC FPGA with embedded Hardcore ARM CortexM3
Promoting Edge AI, Security & High Performance Display Applications

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GoAI 2.0 is a machine learning development platform to deploy CNNs (Convolutional Neural Networks) on GOWIN FPGAs. It includes software scripts needed to convert TensorFlow files and accelerator FPGA IP to run trained machine learning models as well as tutorials and examples.

HDMI receiver and transmitter interfaces are now available and included in GOWIN EDA targeting both Littlebee and Arora FPGA product families.  Reference designs such as HDMI to LVDS are also available for resolutions up to 1080p providing significant BOM cost reductions to alternative ASIC interfacing solutions.  Human machine interfaces, video recorders interactive kiosks and automotive display consoles all benefit by using this very low cost and very scalable HDMI solution.

The GW1NZ-ZV offers an ultra-low power ash based FPGA in the GOWIN LittleBee product family.  At <28μW the GW1NZ-ZV consumes the lowest static power consumption of any ash based FPGA to date making it great for always-on and always-monitoring applications.  As part of the LittleBee family, the GW1NZ-ZV offers instant-on, embedded non-volatile ash, security and exible package options.  The device is widely used in edge and IoT applications for communication, industry control, consumer, and video products.  GOWIN supports the GW1NZ series of FPGA products through a full FPGA software development suite including synthesis, place and route, as well as bitstream generation and device programming.

The GW1NRF Bluetooth FPGA is the first uSoC FPGA to offer a built in Bluetooth transceiver to wirelessly communicate data.  The device offers a full Bluetooth 5.0 Low Energy stack, a low power 32-bit ARC processor, power management with a 5mA power disable mode, step up/down DCDC regulator for powering the device directly with a battery in addition to the standard FPGA features expected from the GOWIN Littlebee family.

SecureFPGA products provide a hardware Root of Trust based on PUF (Physical Unclonable Function) technology.  PUFs use the behavior of SRAM to differentiate chips from each other. They are virtually impossible to duplicate, clone or predict. This makes them very suitable for applications such as secure key generation and storage, device authentication, flexible key provisioning and chip asset management.  Each device is factory provisioned with a unique key pair that is never exposed outside of the device.

HyperBus is a high-performance memory interface which offers:

• Low signal count (Address, Command, and Data using only eight DQ pins)

• High Bandwidth performance

• Low Power consumption

• User-friendly protocol

HyperBus currently interfaces to the HyperRAM TM and HyperFlash TM memories with maximum performance (up to 333 MBytes/s). Designed for reliable while being compactness, these memories are great for mobile and automotive applications.

Features:

• Low FPGA Fabric resource utilization

• Supports Burst Mode for Read/Write transfers

• Operating Frequency up to 166 MHz (max 333 MBytes/s) with only 12 x IO pins (CS, Clk/Clk_n, DQS, DQ[7:0])

• 16 bit Slave Data Interface with Burst (and wrap) support

• 16 bit Slave Register Interface to access HyperRAM memory registers

• Burst Wrap mode support

• Configurable IP options

• SCF Timing Constraints.

• Dual-die memories supported

Memories Supported:

Winbond PSRAM

ISSI IS66/67WVH8M8ALL/BLL - 64Mb

Cypress S27KL/S0641 - 64Mb

Cypress S70KL/S1281 - 128Mb

The GOWIN Development Platform combines the RISC-V Microprocessor SW design flow and FPGA HW Design flow as a fully integrated single toolchain consisting of all GOWIN device model libraries and software driver libraries needed to program the GW2A-18/55 FPGA hosting with the configurable RISC-V & System Peripheral. The platform supports Application software compiling, linking, in-circuit-emulation/debugging on behalf of the embedded RISC-V microprocessor as well as synthesis and place & route of the FPGA design embedded with the RISC-V & System Soft IP.

I3C is a new generation two-wire serial bus interface developed by MIPI Alliance Sensor Working Group and collaborated by industry-wide sensor chip makers, IP companies and Top-Tier ODMs in mobile and embedded markets. I3C is targeted to be a fundamental interface for mobile, embedded system and IoT applications

More IO in a Smaller Package!

Smart speaker with mircrophone array is now the portal of Smart Home. GOWIN LittleBee^TM non-volatile FPGA provides you more IO to connected to the microphone array in a tiny package.  The integrated high performance, configurable DSP accelerates signal decoding while the abundant logic insides perform trans-coding from PCM to I2S. And all these are done in a tiny low power LittleBeeÔnon-volatile FPGA.

Highest Integrated of the industry – HMI on one chip!

GOWIN LittleBee^TM Family GW1NR FPGA provides the highest integration for HMI and industrial display applications, realizes perfect solution of HMI on single chip in the programmable logic industry.