In order to optimize your browsing experience we uses cookies. You agree to the usage of cookies when you browsing this site.
For more information regarding cookies and the processing of your personal data please read our Privacy Policy.
SUPPORT
Listen to Your Voices and Let Us Know Your Needs
Back
GOWIN RAM BASED SHIFT REGISTER
GOWIN RAM Based Shift Register IP provides an efficient multi-bit width shift
register that can be used as a FIFO-like data buffer or delay line
function to create fixed-length and variable-length shift registers, as shown
in Table 2-1.
Features
- Support GW1N, GW1NR, GW2A, GW2AR series chips.
- Can create fixed-length, lossy variable or lossless variable shift
registers. - The speed of the variable length shift register can be optimized or the
resource can be optimal. - Design support is based on LUT implementation, BSRAM implementation and SSRAM implementation.