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Gowin DDR PHY Interface
Introduction
Gowin DDR Memory Interface IP is a commonly used DDR interface IP, in compliance with JESD79-F. The IP includes the DDR Memory Controller (MC) and the corresponding Physical Interface (PHY) design. Gowin DDR Memory Interface IP provides the user a generic command interface to connect with the memory chip to access and store.
Features
- Supports FPGA devices of GW2A-18,GW2AR-18, GW2A-55, GW1N(S)(R)
- Support connecting to the industrial standard DDR SDRAM devices
and modules compatible with the JESD79-2F specification - Support selecting the clock ratio of DDR MC to PHY 1:1/1:2
- Support memory data path width of 8 bits, 16 bits, 24 bits, 32 bits, 40
bits, 48 bits, 56 bits, 64 bits, and 72 bits. - Support x4, x8, and x16 data widths memory chips
- 1:1 programmable burst length 2/4/8, 1:2 programmable burst length
4/8. - Support ECC
- Configurable CL
- Configurable AL
- Configurable tFAW
- Configurable tRAS
- Configurable tRCD
- Configurable tRFC
- Configurable tRRD
- Configurable tRTP
- Configurable tWTR
- Support automatically refreshing and user startup refreshing, the interval of automatically refreshing configurable.