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Gowin SEU Handler
Introduction
Gowin Arora V FPGA devices adopt an SEU Handler module so as to protect the configuration memory from soft errors. The module is implemented by reading the configuration memory frame by frame in background of user design and performing ECC decoding and CRC checksum comparison. It would correct limited number of error bits by programming corrected frame data back to configuration SRAM.
Features
- ECC and CRC algorithm-based detection and correction
- Report any number of bit error within the configuration SRAM
- Correct a single bit of error within a 64-bit configuration SRAM data block
- The feature could be enabled either by user logic or automatically after wake-up
- 1-bit error injection for functional verification and evaluation
- Higher frequency of operation clock is supported[1].
[1] Please contact the local support for more information.