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Documentation Database

Previous Name: DK-VIDEO-GW2A18-PG484 V1.2


DK_VIDEO_GW2A-LV18PG484C8I7_V1.2 applies to high-speed data storage based on DDR3, high-speed communication test based on LVDS and HDMI RX/TX, 18k series of FPGA evaluation, the hardware verification and software learning and debugging, etc.

The development board uses the GW2A- LV18PG484 FPGA device, which is the first generation of Gowin Arora family. The GW2A series of FPGA products offer a range of features and rich resources like high-performance DSP, high-speed LVDS interface and BSRAM. These embedded resources combine a streamlined FPGA architecture with a 55nm process to make the GW2A series of FPGA products ideal for high-speed and low-cost applications.

The development board includes a DDR3 chip with 2Gbit storage space and 16 bits data bus width. It integrates four HDMI interfaces, two of which are used to receive signals (One receives signals via decoding chip, and the other receives signals via FPGA IP), and the other two are used to transmit signals (One transmits signals via decoding chip, and the other transmits signals via FPGA IP). Besides that, this board also includes abundant external interfaces, including LVDS TX, LVDS RX, MIPI CSI, MIPI DSI, and GPIO. The external Flash is used to store FPGA configuration programs. Slide switches, keys, and LED facilitate users debugging.

Documents Download
User Guide DK_VIDEO_GW2A-LV18PG484C8I7_V1.2 Development Board User Guide Download
- Minimum FPGA System SCH Download
- Gowin FPGA SCH Symbol Download
- BSDL Download
Schematic DK_VIDEO_GW2A-LV18PG484C8I7_V1.2 SCH Download
User Guide DK-VIDEO-GW2A18-PG484_V1.1 Development Board User Guide Download
User Guide DK-VIDEO-GW2A18-PG484 V1.2 Development Board User Guide Download
Schematic DK-VIDEO-GW2A18-PG484 SCH_V1.2 Download
Schematic DK-VIDEO-GW2A18-PG484 SCH_V1.1 Download