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GOWIN FIFO HS
IP Introduction
Gowin FIFO IP contains synchronous FIFO (FIFO SC HS) IP and
asynchronous FIFO (FIFO HS) IP.
- The read ports signals and write ports signals of the synchronous FIFO are all controlled by one clock domain;
- The read ports signals and write ports signals of the asynchronous FIFO are controlled by two independent clock domains.
The Gowin IP Core Generator can be used to generate a FIFO IP with single-cycle read/write and configurable ports. The configuration port is such that you can generate
FIFO HS IP Function and Feature
- The implementation type of the internal storage structure of FIFO HS IP is configurable, including block SRAM, Shadow SRAM and LUT;
- Write data depth is configurable. The depth is 2n, and the maximum value is 65536;
- Write data bit width is configurable. The size is 1-256 bit;
- Read data depth is configurable. The depth is 2n, and the maximum value is 65536;
- Read data bit-width=Write data depth x Write bit-width / Read data depth, not configurable.
Note!
The figures applied to the formula described above must be divisible, which limits the maximum read data depth. - The output of the read/write data number is configurable. You can choose whether to output the read/write number data or not;
- The reset function is configurable. You can choose not to use reset (reset by GSR), to use one reset, or to reset read and write respectively;
- The flag signal output is optional. You can choose to output a almost-empty flag, an almost-full flag or no flag; The output almost-empty signal and almost-full signal are one cycle later compared to those of the original FIFO IP;
- If you choose to output an almost-empty or almost-full flag, the threshold of almost-empty, almost-full is configurable. They can be setas: Static single constant threshold, Static double constant threshold, Dynamic single input threshold, Dynamic double input threshold;
- The ECC check function is optional. The ECC check function can be selected when the asynchronous FIFO HS IP storage structure is achieved by block SRAM and the read/write bit-width are equal and are all below than 64bit;
- The output register function is configurable. If you choose the output register function, the read-enable (RdEn) control is optional. If you choose enable-control, the output register is controlled by RdEn, and the last data cannot be output. If you choose the output register function instead of read-enable control, the read data output will be a cycle later, and the last data will be output.
- First-Word Fall-Through function is supported, but some conditions of this timing are not easily met and the design runs at a slower clock frequency.
Documents Download
| User Guide | Gowin FIFO HS User Guide | Download |