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Documentation Database

GOWIN DIVIDER IP is available for all GOWIN FPGA chips and is designed to perform division operations.




  • can achieve division of signed decimals;
  • configurable data bit width;
  • configurable decimal place precision;
  • The output latency is related to the configuration of the parameters (data bit width N and decimal bit precision Q).


Documents Download
Reference Design Gowin DIVIDER RefDesign Download
Release Note Gowin DIVIDER Release Note Download
User Guide Gowin DIVIDER User Guide Download