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PRODUCTS
Low Power, High Performance, High Reliability
ARORA®

 

 

 


 Arora® Family is designed to offer the best-in-class performance cost ratio FPGA. With abundant logic, high-performance DSP resources and high speed I/O, the family is optimized for co-processing to offload the application processor on intensive computation tasks. The Arora® family is also the first FPGA with embedded pSRAM in the industry, which gives customers more usable device I/O.

 

  • Lower Power Consumption
    - 55nm SRAM technology
    - Core voltage: 1.0V
    - Clock dynamically turning on/ turning off

 

  • Multiple I/O Standards
    - LVCMOS33/25/18/15/12;LVTTL33,SSTL33/25/18 I, II, SSTL15; HSTL18 I, II, HSTL15 I;PCI, LVDS25, RSDS, LVDS25E, BLVDSE, MLVDSE, LVPECLE, RSDSE
    - Input hysteresis option
    - Supports 4mA, 8mA, 16mA, 24mA,etc. drive options
    - Slew Rate option
    - Output drive strength option
    - Individual Bus Keeper, Weak Pull-up, Weak Pull-down, and Open Drain option
    - Hot Socket

 

  • High Performance DSP
    - High performance digital signal processing ability
    - Supports 9 x 9,18 x 18,36 x 36bit multiplier and 54bit accumulator;
    - Multiplier cascading
    - Registers pipeline and bypass
    - Adaptive filtering through signal feedback
    - Supports barrel shifter

 

  • Abundant Slices
    - 4 input LUT (LUT4)
    - Double-edge flip-flops
    - Supports shift register and distributed register Block SRAM with Multiple Modes
    - Supports Dual Port, Single Port, and Semi Dual Port
    - Supports bytes write enable Flexible PLLs
    - Frequency adjustment (multiply and division) and phase adjustment
    - Supports global clock Configuration
    - JTAG configuration
    - 6 GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, DUAL BOOT
    - Data stream file encryption and security bit settings

Coming Soon.

GOWIN Semiconductor has been manufacturing automotive grade FPGA since early 2018. Providing fully certified AEC-Q100 Level-2 non-volatile Flash-based and SRAM FPGA devices that support a wide range of interface standards including MIPI-DPHY and LVDS.

 

Devices
GOWIN AEC-Q100 automotive qualified devices are ideally suited for interfacing and bridging camera sensors and displays for ADAS, 360o surround view, infotainment systems and LCD dashboard applications as well as system control, monitoring and management applications.

 

IP

GOWIN provides a wide range of freely-licenced reference designs and IP cores that are readily accessible using the IP Core Generator provided in our free FPGA EDA Design Software.

 

Solutions

Over 10 complete solutions have been developed, many of which have passed vehicle   installation tests in a number of leading top automotive companies.

GW2A Family Table

 

Device GW2A-18 GW2A-55
LUT4 20,736 54,720
Flip-Flop (FF) 15,552 41,040
Shadow SRAM S-SRAM(bits) 41,472 109,440
Block SRAM B-SRAM(bits) 828K 2,520K
Number of B-SRAM 46 140
18 x 18 Multiplier 48 40
PLLs 4 6
I/O Bank Number 8 8
Max. User I/O on die 384 608
Core voltage 1.0V 1.0V

 


 

Package Options and Max I/O (* Refer to the latest datasheet for details)

 

Package Pitch (mm)

Size(mm)

E-pad size (mm) GW2A-18 GW2A-55
QN88 0.4 10 x 10 6.74 x 6.74 66(22) -
LQ144 0.5 20 x 20 119(34) -
EQ144  0.5 20 x 20 9.74 x 9.74  119(34) -
MG196 0.5 8 x 8 114(39)
PG256 1.0 17 x 17 207(73) -
PG256S 1.0 17 x 17 192(72)
PG256C 1.0 17 x 17 190(64)
PG256E 1.0 17 x 17 - 162(29) -
PG484 1.0 23 x 23 319(78) 319(76)
PG1156 1.0 35 x 35 - 607(97)
UG324 0.8 15 x 15 239(90) 240(86)
UG324D 0.8 15 x 15 - - 240(71)
UG676 0.8 21 x 21 - - 525(97)

 

GW2AN Family
The GW2AN series of FPGA products are the first generation non-volatile FPGA products of the Arora family. They offer a range of comprehensive features and rich internal resources, a high-speed LVDS interface, abundant BSRAM memory resources, and NOR Flash resources.

These embedded resources combine a streamlined FPGA architecture with a 55nm process to make the GW2AN series of FPGA products suitable for high-speed, low-cost applications. GOWIN continually invests the development of next-generation FPGA hardware environment through the market-oriented independent research and developments that supports the GW2AN series of FPGA products, which can be used for FPGA synthesizing, layout, place and routing, data bitstream generation and download, etc.

 

2.1    Features

  • Lower power consumption
    • 55nm technology
    • EV version: Supports 1.0V core voltage;
    • LV version: Supports 1.2 V core voltage;
    • UV version: Supports5V and 3.3 V core voltage;
    • Clock dynamically turns on and off
  • Multiple I/O standards
    • LVCMOS33/25/18/15/12;LVTTL33,SSTL33/25/18 I, II, SSTL15; HSTL18 I, II, HSTL15 I; PCI, LVDS25, RSDS, LVDS25E, BLVDSE MLVDSE, LVPECLE, RSDSE
    • Input hysteresis option
    • Supports 4mA,8mA,16mA,24mA,etc. drive options
    • Slew rate option
    • Output drive strength option
    • Individual bus keeper, weak pull-up, weak pull-down, and open drain option
    • Hot socket
  • Abundant slices
    • Four input LUT (LUT4)
    • Double-edge flip-flops
    • Supports shift register and distributed register
  • Integrate NOR Flash
  • Block SRAM with multiple modes
    • Supports dual port, single port, and semi-dual port
    • Supports byte write enable
  • Flexible PLLs
    • Frequency adjustment (multiply and division) and phase adjustment
    • Supports global clock
  • Configuration
    • Supoprts JTAG configuration
    • Five GowinCONFIG configuration modes: SSPI, Autoboot, CPU, I2C, SERIAL
    • Supoprts I2C and SSPI background programing
    • Supports JTAG and SSPI programming SPI Flash directly and other modes programming SPI Flash via IP
    • Data stream file encryption and security bit settings


GW2AN Family Table

Device GW2AN-4X GW2AN-9X GW2AN-18X

LUT4

4608

10368

20,736

Flip-Flop (FF)

4608

10368

15,552

SSRAM(bits)

36864

41472

41,472

BSRAM(bits)

108K

450K

540K

BSRAM quantity

6

25

30

NOR Flash

16M bit

16M bit

16M bit

PLLs

2

2

2

Global Clock

8

8

8

High Speed Clock

8

8

8

LVDS (Mb/s)

1250

1250

1250

MIPI (Mb/s)

1200

1200

1200

Total number of I/O

banks

9

9

9

Max. I/O

TBD

TBD

384

Core voltage (EV)

1.0V

1.0V

1.0V

Core voltage (LV)

1.2V

1.2V

1.2V

Core voltage (UV)

2.5V/3.3V

2.5V/3.3V

2.5V/3.3V

 

 

Package Options and Max I/O (* Refer to the latest datasheet for details)

Package Pitch (mm)

Size(mm)

E-pad size (mm) GW2AN-4X GW2AN-9X GW2AN-18X

PG256

1.0

17 x 17

TBD

TBD

207(86)

UG256

0.8

14 x 14

TBD

TBD

207(86)

UG324

0.8

15 x 15

TBD

TBD

279(74)

UG332

0.8

17 x 17

TBD

TBD

279(82)

UG400

0.8

17 x 17

TBD

TBD

335(95)

UG484

0.8

19 x 19

TBD

TBD

393(96)

Note!

  • The package types in this data sheet are written with abbreviations. See 1Part Name for further information.
  • JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The Max. I/O noted in this table is referred to when the four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O. For further detailed information, pelase refer toUG973, GW2AN series of FPGA Products Package and Pinout .

GW2AN-55 is the first generation products of the Arora family. They offer a range of comprehensive features and rich internal resources like high-performance DSP resources, a high-speed LVDS interface, and abundant BSRAM memory resources. These embedded resources combine a streamlined FPGA architecture with a 55nm process to make GW2AN-55 suitable for high-speed, low-cost applications.

GOWINSEMI continually invests the development of next-generation FPGA hardware environment through the market-oriented independent research and developments that supports GW2AN-55, which can be used for FPGA synthesizing, layout, place and routing, data bitstream generation and download, etc.

 

Features

  • Lower power consumption
    • 55nm SRAM technology
    • Core voltage: 0V
    • Clock dynamically turns on and off
  • Multiple I/O standards
    • LVCMOS33/25/18/15/12;LVTTL33,SSTL33/25/18 I, II, SSTL15;
    • HSTL18 I, II, HSTL15 I; PCI, LVDS25, RSDS, LVDS25E, BLVDSE
    • MLVDSE, LVPECLE, RSDSE
    • Input hysteresis option
    • Supports 4mA,8mA,16mA,24mA,etc. drive options
    • Slew rate option
    • Output drive strength option
    • Individual bus keeper, weak pull-up, weak pull-down, and open drain option
    • Hot socket
  • Integrates NOR FLASH
  • High performance DSP
    • High performance digital signal processing ability
    • Supports 9 x 9,18 x 18,36 x 36 bits multiplier and 54 bits accumulator;
    • Multipliers cascading
    • Registers pipeline and bypass
    • Adaptive filtering through signal feedback
    • Supports barrel shifter
  • Abundant slices
    • Four input LUT (LUT4)
    • Double-edge flip-flops
    • Supports shift register and distributed register
  • Block SRAM with multiple modes
    • Supports dual port, single port, and semi-dual port
    • Supports bytes write enable
  • Flexible PLLs
    • Frequency adjustment (multiply and division) and phase adjustment
    • Supports global clock
  • Configuration
    • JTAG configuration
    • Four GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, DUAL BOOT
    • Supports JTAG and SSPI programming SPI Flash directly and other modes programming SPI Flash via IP
    • Data stream file encryption and security bit settings

 

Product Resources

Device GW2AN-55

LUT4

54,720

Flip-Flop (FF)

41,040

Shadow SRAM

SSRAM (bits)

109,440

Block SRAM BSRAM (bits)

2,520K

BSRAM quantity BSRAM

140

NOR Flash (bits)

32M

18 x 18 Multiplier

40

Maximum PLLs

6

Total number of I/O banks

8

Max. I/O

608

Core voltage

1.0V

 

Package Options and Max I/O (* Refer to the latest datasheet for details)

Package Pitch (mm)

Size(mm)

E-pad size (mm) GW2AN-55

UG676

0.8

21 x 21

525(97)

 

Note!

  • The package types in this data sheet are written with abbreviations. See 1Part Name for further information.
  • JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The Max. I/O noted in this table is referred to when the four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O. When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO, and TMS) can be used as GPIO simultaneously, and the Max. user I/O is increased by For further detailed information, please refer to UG975, GW2AN-55 Package and Pinout Guide.

GW2ANR Family Table

 

Device GW2ANR-18
LUT4 20,736
Flip-Flop (FF) 15,552
Shadow SRAM S-SRAM(bits) 41,472
Block SRAM B-SRAM(bits) 828K
Number of B-SRAM 46
NOR FLASH (bits) 32M
SDR SDRAM (bits) 64M
18 x 18 Multiplier 48
PLLs 4
I/O Bank Number 8
Max. User I/O on die 384
Core voltage 1.0V

 

Package Device Memory Bit Width Capacity
PLL
QN88 GW2ANR-18 SDR SDRAM 32 bits 64M bits PLLL1/PLLR1
NOR FLASH 1 bit 32M bits

 

Package Options and Max I/O (* Refer to the latest datasheet for details)

 

 GW2ANR-18

Package Pitch (mm) Size(mm) E-PAD Size (mm) GW2AR-18
QN88 0.4 10 x 10 6.74 x 6.74 66(22)

GW2AR Family Table

 

Device GW2AR-18
LUT4 20,736
Flip-Flop (FF) 15,552
Shadow SRAM S-SRAM(bits) 41,472
Block SRAM B-SRAM(bits) 828K
Number of B-SRAM  46
PSRAM (bits) 64M
SDR/DDR SDRAM (bits) 64M / 128M
18 x 18 Multiplier 48
PLLs 4
I/O Bank Number 8
Max. User I/O 384
Core voltage 1.0V

 

Package Device Memory PLL
LQ144 GW2AR-18 SDR SDRAM PLLL0/PLLL1/PLLR0/PLLR1
EQ144 GW2AR-18

SDR SDRAM

PLLL0/PLLL1/PLLR0/PLLR1

EQ144P(1) GW2AR-18

PSRAM

PLLL0/PLLL1/PLLR0/PLLR1

EQ144PF(1) GW2AR-18

PSRAM

PLLL0/PLLL1/PLLR0/PLLR1

QN88 GW2AR-18

SDR SDRAM

PLLL1/PLLR1

QN88P(1) GW2AR-18

PSRAM

PLLL1/PLLR1

QN88PF(1) GW2AR-18

PSRAM

PLLL1/PLLR1

LQ176 GW2AR-18 DDR SDRAM PLLL1/PLLR0/PLLR1
EQ176 GW2AR-18 DDR SDRAM PLLL1/PLLR0/PLLR1

 

Note (1) "P" indicates PSRAM; "F" indicates secondary pinout.

 

Package Options and Max I/O (* Refer to the latest datasheet for details)

 

 GW2AR-18

Package Pitch (mm) Size(mm) E-PAD Size (mm) GW2AR-18
LQ144 0.5 20 x 20 - 120(35)
EQ144 0.5 20 x 20 9.74 x 9.74 120(35)
EQ144P 0.5 20 x 20 9.74 x 9.74 120(35)
EQ144PF 0.5 20 x 20 9.74 x 9.74 120(35)
QN88 0.4 10 x 10 6.74 x 6.74 66(22)
QN88P 0.4 10 x 10 6.74 x 6.74 66(22)
QN88PF 0.4 10 x 10 6.74 x 6.74 66(22)
LQ176 0.4 20 x 20 -  140(45)
EQ176 0.4 20 x 20 6 x 6 140(45)