Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\HYPERRAM\data\HPRAM_TOP.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\HYPERRAM\data\hpram_code_1N2A.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.03 (64-bit)
Part Number GW1NSR-LV4CQN48PC7/I6
Device GW1NSR-4C
Created Time Fri Aug 1 14:15:43 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module HyperRAM_Memory_Interface_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.387s, Peak memory usage = 64.211MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 64.211MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.056s, Peak memory usage = 64.211MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 64.211MB
    Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.062s, Peak memory usage = 64.211MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 64.211MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 64.211MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 64.211MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 64.211MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 64.211MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 64.211MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 64.211MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 94.121MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.377s, Peak memory usage = 94.121MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.061s, Peak memory usage = 94.121MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 94.121MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 99
Embedded Port 13
I/O Buf 112
    IBUF 64
    OBUF 39
    IOBUF 9
Register 391
    DFF 1
    DFFP 4
    DFFPE 3
    DFFC 212
    DFFCE 171
LUT 630
    LUT2 189
    LUT3 188
    LUT4 253
ALU 30
    ALU 30
INV 8
    INV 8
IOLOGIC 30
    IDES4 8
    OSER4 12
    IODELAY 10
BSRAM 2
    SDPB 1
    SDPX9B 1
CLOCK 2
    CLKDIV 1
    DHCEN 1

Resource Utilization Summary

Resource Usage Utilization
Logic 668(638 LUT, 30 ALU) / 4608 15%
Register 391 / 3612 11%
  --Register as Latch 0 / 3612 0%
  --Register as FF 391 / 3612 11%
BSRAM 2 / 10 20%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 memory_clk Base 20.000 50.000 0.000 10.000 memory_clk_ibuf/I
2 clk Base 20.000 50.000 0.000 10.000 clk_ibuf/I
3 u_hpram_top/clkdiv/CLKOUT.default_gen_clk Generated 40.000 25.000 0.000 20.000 memory_clk_ibuf/I memory_clk u_hpram_top/clkdiv/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 122.469(MHz) 6 TOP
2 u_hpram_top/clkdiv/CLKOUT.default_gen_clk 25.000(MHz) 134.223(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 8.904
Data Arrival Time 1.589
Data Required Time 10.493
From u_hpram_top/u_hpram_sync/cs_memsync_4_s0
To u_hpram_top/u_dqce_clk_x2p
Launch Clk clk[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 31 clk_ibuf/O
0.538 0.538 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_4_s0/CLK
0.878 0.340 tC2Q RF 8 u_hpram_top/u_hpram_sync/cs_memsync_4_s0/Q
1.589 0.711 tNET FF 1 u_hpram_top/u_dqce_clk_x2p/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 memory_clk
10.000 0.000 tCL FF 1 memory_clk_ibuf/I
10.000 0.000 tINS FF 1 memory_clk_ibuf/O
10.711 0.711 tNET FF 3 u_hpram_top/u_dqce_clk_x2p/CLKIN
10.681 -0.030 tUnc u_hpram_top/u_dqce_clk_x2p
10.493 -0.188 tSu 1 u_hpram_top/u_dqce_clk_x2p
Path Statistics:
Clock Skew: 0.173
Setup Relationship: 10.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.711, 67.685%; tC2Q: 0.340, 32.315%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 2

Path Summary:
Slack 11.835
Data Arrival Time 8.407
Data Required Time 20.242
From u_hpram_top/u_hpram_sync/lock_cnt_1_s3
To u_hpram_top/u_hpram_sync/lock_cnt_10_s3
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 31 clk_ibuf/O
0.538 0.538 tNET RR 1 u_hpram_top/u_hpram_sync/lock_cnt_1_s3/CLK
0.878 0.340 tC2Q RF 6 u_hpram_top/u_hpram_sync/lock_cnt_1_s3/Q
1.589 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n47_s2/I1
2.403 0.814 tINS FF 5 u_hpram_top/u_hpram_sync/n47_s2/F
3.115 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n43_s2/I2
3.724 0.609 tINS FF 4 u_hpram_top/u_hpram_sync/n43_s2/F
4.435 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n41_s4/I0
5.200 0.765 tINS FF 2 u_hpram_top/u_hpram_sync/n41_s4/F
5.911 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n41_s8/I2
6.520 0.609 tINS FF 1 u_hpram_top/u_hpram_sync/n41_s8/F
7.232 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n41_s9/I3
7.696 0.464 tINS FF 1 u_hpram_top/u_hpram_sync/n41_s9/F
8.407 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/lock_cnt_10_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 31 clk_ibuf/O
20.538 0.538 tNET RR 1 u_hpram_top/u_hpram_sync/lock_cnt_10_s3/CLK
20.242 -0.296 tSu 1 u_hpram_top/u_hpram_sync/lock_cnt_10_s3
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.261, 41.443%; route: 4.268, 54.241%; tC2Q: 0.340, 4.316%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 3

Path Summary:
Slack 11.990
Data Arrival Time 8.251
Data Required Time 20.242
From u_hpram_top/u_hpram_sync/lock_cnt_1_s3
To u_hpram_top/u_hpram_sync/lock_cnt_12_s3
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 31 clk_ibuf/O
0.538 0.538 tNET RR 1 u_hpram_top/u_hpram_sync/lock_cnt_1_s3/CLK
0.878 0.340 tC2Q RF 6 u_hpram_top/u_hpram_sync/lock_cnt_1_s3/Q
1.589 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n47_s2/I1
2.403 0.814 tINS FF 5 u_hpram_top/u_hpram_sync/n47_s2/F
3.115 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n43_s2/I2
3.724 0.609 tINS FF 4 u_hpram_top/u_hpram_sync/n43_s2/F
4.435 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n39_s2/I2
5.044 0.609 tINS FF 4 u_hpram_top/u_hpram_sync/n39_s2/F
5.756 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n39_s6/I2
6.365 0.609 tINS FF 1 u_hpram_top/u_hpram_sync/n39_s6/F
7.076 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n39_s7/I3
7.540 0.464 tINS FF 1 u_hpram_top/u_hpram_sync/n39_s7/F
8.251 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/lock_cnt_12_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 31 clk_ibuf/O
20.538 0.538 tNET RR 1 u_hpram_top/u_hpram_sync/lock_cnt_12_s3/CLK
20.242 -0.296 tSu 1 u_hpram_top/u_hpram_sync/lock_cnt_12_s3
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.106, 40.262%; route: 4.268, 55.335%; tC2Q: 0.340, 4.403%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 4

Path Summary:
Slack 12.805
Data Arrival Time 7.437
Data Required Time 20.242
From u_hpram_top/u_hpram_sync/lock_cnt_1_s3
To u_hpram_top/u_hpram_sync/lock_cnt_11_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 31 clk_ibuf/O
0.538 0.538 tNET RR 1 u_hpram_top/u_hpram_sync/lock_cnt_1_s3/CLK
0.878 0.340 tC2Q RF 6 u_hpram_top/u_hpram_sync/lock_cnt_1_s3/Q
1.589 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n47_s2/I1
2.403 0.814 tINS FF 5 u_hpram_top/u_hpram_sync/n47_s2/F
3.115 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n43_s2/I2
3.724 0.609 tINS FF 4 u_hpram_top/u_hpram_sync/n43_s2/F
4.435 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n41_s4/I0
5.200 0.765 tINS FF 2 u_hpram_top/u_hpram_sync/n41_s4/F
5.911 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n40_s1/I1
6.726 0.814 tINS FF 1 u_hpram_top/u_hpram_sync/n40_s1/F
7.437 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/lock_cnt_11_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 31 clk_ibuf/O
20.538 0.538 tNET RR 1 u_hpram_top/u_hpram_sync/lock_cnt_11_s1/CLK
20.242 -0.296 tSu 1 u_hpram_top/u_hpram_sync/lock_cnt_11_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.003, 43.522%; route: 3.557, 51.555%; tC2Q: 0.340, 4.923%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 5

Path Summary:
Slack 12.950
Data Arrival Time 7.292
Data Required Time 20.242
From u_hpram_top/u_hpram_sync/cs_memsync_5_s0
To u_hpram_top/u_hpram_sync/flag_0_s4
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 31 clk_ibuf/O
0.538 0.538 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_5_s0/CLK
0.878 0.340 tC2Q RF 8 u_hpram_top/u_hpram_sync/cs_memsync_5_s0/Q
1.589 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/flag_d_1_s17/I1
2.403 0.814 tINS FF 3 u_hpram_top/u_hpram_sync/flag_d_1_s17/F
3.115 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/flag_d_1_s12/I3
3.579 0.464 tINS FF 3 u_hpram_top/u_hpram_sync/flag_d_1_s12/F
4.290 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/flag_d_0_s12/I1
5.104 0.814 tINS FF 1 u_hpram_top/u_hpram_sync/flag_d_0_s12/F
5.816 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/flag_d_0_s13/I0
6.580 0.765 tINS FF 1 u_hpram_top/u_hpram_sync/flag_d_0_s13/F
7.292 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/flag_0_s4/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 31 clk_ibuf/O
20.538 0.538 tNET RR 1 u_hpram_top/u_hpram_sync/flag_0_s4/CLK
20.242 -0.296 tSu 1 u_hpram_top/u_hpram_sync/flag_0_s4
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 2.857, 42.307%; route: 3.557, 52.664%; tC2Q: 0.340, 5.029%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%