Synthesis Messages

Report Title GowinSynthesis Report
Design File F:\EMB_pub\embedded\arm\cortex_m3 (GW1NS-4C)\ref_design\2.1\FPGA_RefDesign\DK_START_GW1NSR4C_QN48P_V1.1\gowin_empu\cm3_fifo_demo\src\fifo_top\temp\FIFO\fifo_define.v
F:\EMB_pub\embedded\arm\cortex_m3 (GW1NS-4C)\ref_design\2.1\FPGA_RefDesign\DK_START_GW1NSR4C_QN48P_V1.1\gowin_empu\cm3_fifo_demo\src\fifo_top\temp\FIFO\fifo_parameter.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\edc.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.03 (64-bit)
Part Number GW1NSR-LV4CQN48PC7/I6
Device GW1NSR-4C
Created Time Fri Aug 1 11:22:24 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module fifo_top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.775s, Peak memory usage = 64.387MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 64.387MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 64.387MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 64.387MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 64.387MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 64.387MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 64.387MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 64.387MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 64.387MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 64.387MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 64.387MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 64.387MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.288s, Peak memory usage = 85.461MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.095s, Peak memory usage = 85.461MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.14s, Peak memory usage = 85.461MB
Total Time and Memory Usage CPU time = 0h 0m 0.654s, Elapsed time = 0h 0m 1s, Peak memory usage = 85.461MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 83
I/O Buf 83
    IBUF 37
    OBUF 46
Register 56
    DFFP 6
    DFFC 50
LUT 45
    LUT2 14
    LUT3 12
    LUT4 19
ALU 14
    ALU 14
INV 2
    INV 2
BSRAM 1
    SDPB 1

Resource Utilization Summary

Resource Usage Utilization
Logic 61(47 LUT, 14 ALU) / 4608 2%
Register 56 / 3573 2%
  --Register as Latch 0 / 3573 0%
  --Register as FF 56 / 3573 2%
BSRAM 1 / 10 10%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 RdClk Base 20.000 50.000 0.000 10.000 RdClk_ibuf/I
2 WrClk Base 20.000 50.000 0.000 10.000 WrClk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 50.000(MHz) 111.445(MHz) 7 TOP
2 WrClk 50.000(MHz) 109.403(MHz) 7 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 10.860
Data Arrival Time 9.382
Data Required Time 20.242
From fifo_inst/Equal.wq2_rptr_3_s0
To fifo_inst/Almost_Full_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.000 0.000 tINS RR 29 WrClk_ibuf/O
0.538 0.538 tNET RR 1 fifo_inst/Equal.wq2_rptr_3_s0/CLK
0.878 0.340 tC2Q RF 4 fifo_inst/Equal.wq2_rptr_3_s0/Q
1.589 0.711 tNET FF 1 fifo_inst/Equal.rcount_w_1_s1/I1
2.403 0.814 tINS FF 2 fifo_inst/Equal.rcount_w_1_s1/F
3.115 0.711 tNET FF 1 fifo_inst/Equal.rcount_w_0_s0/I0
3.879 0.765 tINS FF 1 fifo_inst/Equal.rcount_w_0_s0/F
4.591 0.711 tNET FF 2 fifo_inst/wcnt_sub_0_s/I1
5.365 0.774 tINS FF 1 fifo_inst/wcnt_sub_0_s/COUT
5.365 0.000 tNET FF 2 fifo_inst/wcnt_sub_1_s/CIN
5.407 0.042 tINS FF 1 fifo_inst/wcnt_sub_1_s/COUT
5.407 0.000 tNET FF 2 fifo_inst/wcnt_sub_2_s/CIN
5.825 0.417 tINS FF 2 fifo_inst/wcnt_sub_2_s/SUM
6.536 0.711 tNET FF 1 fifo_inst/awfull_val_s1/I2
7.145 0.609 tINS FF 1 fifo_inst/awfull_val_s1/F
7.856 0.711 tNET FF 1 fifo_inst/awfull_val_s0/I1
8.671 0.814 tINS FF 1 fifo_inst/awfull_val_s0/F
9.382 0.711 tNET FF 1 fifo_inst/Almost_Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 WrClk
20.000 0.000 tCL RR 1 WrClk_ibuf/I
20.000 0.000 tINS RR 29 WrClk_ibuf/O
20.538 0.538 tNET RR 1 fifo_inst/Almost_Full_s0/CLK
20.242 -0.296 tSu 1 fifo_inst/Almost_Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 4.236, 47.900%; route: 4.268, 48.260%; tC2Q: 0.340, 3.840%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 2

Path Summary:
Slack 11.027
Data Arrival Time 9.215
Data Required Time 20.242
From fifo_inst/Equal.rq2_wptr_3_s0
To fifo_inst/Almost_Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 29 RdClk_ibuf/O
0.538 0.538 tNET RR 1 fifo_inst/Equal.rq2_wptr_3_s0/CLK
0.878 0.340 tC2Q RF 4 fifo_inst/Equal.rq2_wptr_3_s0/Q
1.589 0.711 tNET FF 1 fifo_inst/Equal.wcount_r_1_s1/I1
2.403 0.814 tINS FF 2 fifo_inst/Equal.wcount_r_1_s1/F
3.115 0.711 tNET FF 1 fifo_inst/Equal.wcount_r_0_s0/I0
3.879 0.765 tINS FF 1 fifo_inst/Equal.wcount_r_0_s0/F
4.591 0.711 tNET FF 2 fifo_inst/rcnt_sub_0_s/I0
5.301 0.710 tINS FF 1 fifo_inst/rcnt_sub_0_s/COUT
5.301 0.000 tNET FF 2 fifo_inst/rcnt_sub_1_s/CIN
5.343 0.042 tINS FF 1 fifo_inst/rcnt_sub_1_s/COUT
5.343 0.000 tNET FF 2 fifo_inst/rcnt_sub_2_s/CIN
5.385 0.042 tINS FF 1 fifo_inst/rcnt_sub_2_s/COUT
5.385 0.000 tNET FF 2 fifo_inst/rcnt_sub_3_s/CIN
5.802 0.417 tINS FF 2 fifo_inst/rcnt_sub_3_s/SUM
6.514 0.711 tNET FF 1 fifo_inst/arempty_val_s1/I1
7.328 0.814 tINS FF 1 fifo_inst/arempty_val_s1/F
8.039 0.711 tNET FF 1 fifo_inst/arempty_val_s0/I3
8.503 0.464 tINS FF 1 fifo_inst/arempty_val_s0/F
9.215 0.711 tNET FF 1 fifo_inst/Almost_Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 RdClk
20.000 0.000 tCL RR 1 RdClk_ibuf/I
20.000 0.000 tINS RR 29 RdClk_ibuf/O
20.538 0.538 tNET RR 1 fifo_inst/Almost_Empty_s0/CLK
20.242 -0.296 tSu 1 fifo_inst/Almost_Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 4.069, 46.894%; route: 4.268, 49.192%; tC2Q: 0.340, 3.914%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 3

Path Summary:
Slack 12.669
Data Arrival Time 7.573
Data Required Time 20.242
From fifo_inst/Empty_s0
To fifo_inst/Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 29 RdClk_ibuf/O
0.538 0.538 tNET RR 1 fifo_inst/Empty_s0/CLK
0.878 0.340 tC2Q RF 6 fifo_inst/Empty_s0/Q
1.589 0.711 tNET FF 1 fifo_inst/rbin_num_next_1_s4/I0
2.354 0.765 tINS FF 3 fifo_inst/rbin_num_next_1_s4/F
3.065 0.711 tNET FF 1 fifo_inst/Equal.rgraynext_1_s0/I1
3.879 0.814 tINS FF 2 fifo_inst/Equal.rgraynext_1_s0/F
4.591 0.711 tNET FF 2 fifo_inst/n174_s0/I0
5.301 0.710 tINS FF 1 fifo_inst/n174_s0/COUT
5.301 0.000 tNET FF 2 fifo_inst/n175_s0/CIN
5.343 0.042 tINS FF 1 fifo_inst/n175_s0/COUT
5.343 0.000 tNET FF 2 fifo_inst/n176_s0/CIN
5.385 0.042 tINS FF 1 fifo_inst/n176_s0/COUT
6.096 0.711 tNET FF 1 fifo_inst/rempty_val_s1/I0
6.861 0.765 tINS FF 1 fifo_inst/rempty_val_s1/F
7.573 0.711 tNET FF 1 fifo_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 RdClk
20.000 0.000 tCL RR 1 RdClk_ibuf/I
20.000 0.000 tINS RR 29 RdClk_ibuf/O
20.538 0.538 tNET RR 1 fifo_inst/Empty_s0/CLK
20.242 -0.296 tSu 1 fifo_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.138, 44.610%; route: 3.557, 50.562%; tC2Q: 0.340, 4.828%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 4

Path Summary:
Slack 13.621
Data Arrival Time 6.620
Data Required Time 20.242
From fifo_inst/Equal.wq2_rptr_3_s0
To fifo_inst/Wnum_4_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.000 0.000 tINS RR 29 WrClk_ibuf/O
0.538 0.538 tNET RR 1 fifo_inst/Equal.wq2_rptr_3_s0/CLK
0.878 0.340 tC2Q RF 4 fifo_inst/Equal.wq2_rptr_3_s0/Q
1.589 0.711 tNET FF 1 fifo_inst/Equal.rcount_w_1_s1/I1
2.403 0.814 tINS FF 2 fifo_inst/Equal.rcount_w_1_s1/F
3.115 0.711 tNET FF 1 fifo_inst/Equal.rcount_w_0_s0/I0
3.879 0.765 tINS FF 1 fifo_inst/Equal.rcount_w_0_s0/F
4.591 0.711 tNET FF 2 fifo_inst/wcnt_sub_0_s/I1
5.365 0.774 tINS FF 1 fifo_inst/wcnt_sub_0_s/COUT
5.365 0.000 tNET FF 2 fifo_inst/wcnt_sub_1_s/CIN
5.407 0.042 tINS FF 1 fifo_inst/wcnt_sub_1_s/COUT
5.407 0.000 tNET FF 2 fifo_inst/wcnt_sub_2_s/CIN
5.450 0.042 tINS FF 1 fifo_inst/wcnt_sub_2_s/COUT
5.450 0.000 tNET FF 2 fifo_inst/wcnt_sub_3_s/CIN
5.492 0.042 tINS FF 1 fifo_inst/wcnt_sub_3_s/COUT
5.492 0.000 tNET FF 2 fifo_inst/wcnt_sub_4_s/CIN
5.909 0.417 tINS FF 2 fifo_inst/wcnt_sub_4_s/SUM
6.620 0.711 tNET FF 1 fifo_inst/Wnum_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 WrClk
20.000 0.000 tCL RR 1 WrClk_ibuf/I
20.000 0.000 tINS RR 29 WrClk_ibuf/O
20.538 0.538 tNET RR 1 fifo_inst/Wnum_4_s0/CLK
20.242 -0.296 tSu 1 fifo_inst/Wnum_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 2.897, 47.634%; route: 2.845, 46.782%; tC2Q: 0.340, 5.584%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 5

Path Summary:
Slack 13.663
Data Arrival Time 6.578
Data Required Time 20.242
From fifo_inst/Equal.wq2_rptr_3_s0
To fifo_inst/Wnum_3_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.000 0.000 tINS RR 29 WrClk_ibuf/O
0.538 0.538 tNET RR 1 fifo_inst/Equal.wq2_rptr_3_s0/CLK
0.878 0.340 tC2Q RF 4 fifo_inst/Equal.wq2_rptr_3_s0/Q
1.589 0.711 tNET FF 1 fifo_inst/Equal.rcount_w_1_s1/I1
2.403 0.814 tINS FF 2 fifo_inst/Equal.rcount_w_1_s1/F
3.115 0.711 tNET FF 1 fifo_inst/Equal.rcount_w_0_s0/I0
3.879 0.765 tINS FF 1 fifo_inst/Equal.rcount_w_0_s0/F
4.591 0.711 tNET FF 2 fifo_inst/wcnt_sub_0_s/I1
5.365 0.774 tINS FF 1 fifo_inst/wcnt_sub_0_s/COUT
5.365 0.000 tNET FF 2 fifo_inst/wcnt_sub_1_s/CIN
5.407 0.042 tINS FF 1 fifo_inst/wcnt_sub_1_s/COUT
5.407 0.000 tNET FF 2 fifo_inst/wcnt_sub_2_s/CIN
5.450 0.042 tINS FF 1 fifo_inst/wcnt_sub_2_s/COUT
5.450 0.000 tNET FF 2 fifo_inst/wcnt_sub_3_s/CIN
5.867 0.417 tINS FF 2 fifo_inst/wcnt_sub_3_s/SUM
6.578 0.711 tNET FF 1 fifo_inst/Wnum_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 WrClk
20.000 0.000 tCL RR 1 WrClk_ibuf/I
20.000 0.000 tINS RR 29 WrClk_ibuf/O
20.538 0.538 tNET RR 1 fifo_inst/Wnum_3_s0/CLK
20.242 -0.296 tSu 1 fifo_inst/Wnum_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 2.855, 47.268%; route: 2.845, 47.109%; tC2Q: 0.340, 5.623%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%