Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\PSRAM_HS\psram_hs_1ch\PSRAM_TOP.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\PSRAM_HS\psram_hs_1ch\psram_code.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.03 (64-bit)
Part Number GW1NSR-LV4CMG64PC7/I6
Device GW1NSR-4C
Created Time Fri Aug 1 14:53:05 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module PSRAM_Memory_Interface_HS_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.321s, Peak memory usage = 60.609MB
Running netlist conversion:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 60.609MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.097s, Peak memory usage = 60.609MB
    Optimizing Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 60.609MB
    Optimizing Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.105s, Peak memory usage = 60.609MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 60.609MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 60.609MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 60.609MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 60.609MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.101s, Peak memory usage = 60.609MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 60.609MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 60.609MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 90.543MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.226s, Peak memory usage = 90.543MB
Generate output files:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.093s, Peak memory usage = 90.543MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 90.543MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 166
Embedded Port 26
I/O Buf 191
    IBUF 99
    OBUF 73
    IOBUF 18
    ELVDS_OBUF 1
Register 561
    DFF 1
    DFFP 3
    DFFPE 8
    DFFC 300
    DFFCE 249
LUT 997
    LUT2 247
    LUT3 265
    LUT4 485
ALU 46
    ALU 46
INV 13
    INV 13
IOLOGIC 58
    IDES4 16
    OSER4 23
    IODELAY 19
BSRAM 4
    SDPB 2
    SDPX9B 2
CLOCK 2
    CLKDIV 1
    DHCEN 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1056(1010 LUT, 46 ALU) / 4608 23%
Register 561 / 3702 16%
  --Register as Latch 0 / 3702 0%
  --Register as FF 561 / 3702 16%
BSRAM 4 / 10 40%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 memory_clk Base 20.000 50.000 0.000 10.000 memory_clk_ibuf/I
2 clk Base 20.000 50.000 0.000 10.000 clk_ibuf/I
3 u_psram_top/clkdiv/CLKOUT.default_gen_clk Generated 40.000 25.000 0.000 20.000 memory_clk_ibuf/I memory_clk u_psram_top/clkdiv/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 135.124(MHz) 5 TOP
2 u_psram_top/clkdiv/CLKOUT.default_gen_clk 25.000(MHz) 119.614(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 8.904
Data Arrival Time 1.589
Data Required Time 10.493
From u_psram_top/u_psram_sync/cs_memsync_4_s0
To u_psram_top/u_dqce_clk_x2
Launch Clk clk[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 31 clk_ibuf/O
0.538 0.538 tNET RR 1 u_psram_top/u_psram_sync/cs_memsync_4_s0/CLK
0.878 0.340 tC2Q RF 8 u_psram_top/u_psram_sync/cs_memsync_4_s0/Q
1.589 0.711 tNET FF 1 u_psram_top/u_dqce_clk_x2/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 memory_clk
10.000 0.000 tCL FF 1 memory_clk_ibuf/I
10.000 0.000 tINS FF 1 memory_clk_ibuf/O
10.711 0.711 tNET FF 3 u_psram_top/u_dqce_clk_x2/CLKIN
10.681 -0.030 tUnc u_psram_top/u_dqce_clk_x2
10.493 -0.188 tSu 1 u_psram_top/u_dqce_clk_x2
Path Statistics:
Clock Skew: 0.173
Setup Relationship: 10.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.711, 67.685%; tC2Q: 0.340, 32.315%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 2

Path Summary:
Slack 12.599
Data Arrival Time 7.642
Data Required Time 20.242
From u_psram_top/u_psram_sync/cs_memsync_5_s0
To u_psram_top/u_psram_sync/cs_memsync_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 31 clk_ibuf/O
0.538 0.538 tNET RR 1 u_psram_top/u_psram_sync/cs_memsync_5_s0/CLK
0.878 0.340 tC2Q RF 8 u_psram_top/u_psram_sync/cs_memsync_5_s0/Q
1.589 0.711 tNET FF 1 u_psram_top/u_psram_sync/flag_d_1_s18/I1
2.403 0.814 tINS FF 1 u_psram_top/u_psram_sync/flag_d_1_s18/F
3.115 0.711 tNET FF 1 u_psram_top/u_psram_sync/flag_d_1_s13/I1
3.929 0.814 tINS FF 4 u_psram_top/u_psram_sync/flag_d_1_s13/F
4.640 0.711 tNET FF 1 u_psram_top/u_psram_sync/ns_memsync_1_s13/I1
5.455 0.814 tINS FF 1 u_psram_top/u_psram_sync/ns_memsync_1_s13/F
6.166 0.711 tNET FF 1 u_psram_top/u_psram_sync/ns_memsync_1_s12/I0
6.931 0.765 tINS FF 1 u_psram_top/u_psram_sync/ns_memsync_1_s12/F
7.642 0.711 tNET FF 1 u_psram_top/u_psram_sync/cs_memsync_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 31 clk_ibuf/O
20.538 0.538 tNET RR 1 u_psram_top/u_psram_sync/cs_memsync_1_s0/CLK
20.242 -0.296 tSu 1 u_psram_top/u_psram_sync/cs_memsync_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.208, 45.153%; route: 3.557, 50.066%; tC2Q: 0.340, 4.781%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 3

Path Summary:
Slack 12.755
Data Arrival Time 7.487
Data Required Time 20.242
From u_psram_top/u_psram_sync/flag_0_s5
To u_psram_top/u_psram_sync/cs_memsync_2_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 31 clk_ibuf/O
0.538 0.538 tNET RR 1 u_psram_top/u_psram_sync/flag_0_s5/CLK
0.878 0.340 tC2Q RF 7 u_psram_top/u_psram_sync/flag_0_s5/Q
1.589 0.711 tNET FF 1 u_psram_top/u_psram_sync/ns_memsync_2_s16/I1
2.403 0.814 tINS FF 1 u_psram_top/u_psram_sync/ns_memsync_2_s16/F
3.115 0.711 tNET FF 1 u_psram_top/u_psram_sync/ns_memsync_2_s14/I1
3.929 0.814 tINS FF 2 u_psram_top/u_psram_sync/ns_memsync_2_s14/F
4.640 0.711 tNET FF 1 u_psram_top/u_psram_sync/ns_memsync_2_s13/I1
5.455 0.814 tINS FF 1 u_psram_top/u_psram_sync/ns_memsync_2_s13/F
6.166 0.711 tNET FF 1 u_psram_top/u_psram_sync/ns_memsync_2_s12/I2
6.775 0.609 tINS FF 1 u_psram_top/u_psram_sync/ns_memsync_2_s12/F
7.487 0.711 tNET FF 1 u_psram_top/u_psram_sync/cs_memsync_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 31 clk_ibuf/O
20.538 0.538 tNET RR 1 u_psram_top/u_psram_sync/cs_memsync_2_s0/CLK
20.242 -0.296 tSu 1 u_psram_top/u_psram_sync/cs_memsync_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.052, 43.925%; route: 3.557, 51.187%; tC2Q: 0.340, 4.888%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 4

Path Summary:
Slack 12.805
Data Arrival Time 7.437
Data Required Time 20.242
From u_psram_top/u_psram_sync/lock_cnt_1_s3
To u_psram_top/u_psram_sync/lock_cnt_13_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 31 clk_ibuf/O
0.538 0.538 tNET RR 1 u_psram_top/u_psram_sync/lock_cnt_1_s3/CLK
0.878 0.340 tC2Q RF 5 u_psram_top/u_psram_sync/lock_cnt_1_s3/Q
1.589 0.711 tNET FF 1 u_psram_top/u_psram_sync/n47_s2/I1
2.403 0.814 tINS FF 5 u_psram_top/u_psram_sync/n47_s2/F
3.115 0.711 tNET FF 1 u_psram_top/u_psram_sync/n43_s2/I2
3.724 0.609 tINS FF 6 u_psram_top/u_psram_sync/n43_s2/F
4.435 0.711 tNET FF 1 u_psram_top/u_psram_sync/n39_s2/I0
5.200 0.765 tINS FF 1 u_psram_top/u_psram_sync/n39_s2/F
5.911 0.711 tNET FF 1 u_psram_top/u_psram_sync/n38_s1/I1
6.726 0.814 tINS FF 1 u_psram_top/u_psram_sync/n38_s1/F
7.437 0.711 tNET FF 1 u_psram_top/u_psram_sync/lock_cnt_13_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 31 clk_ibuf/O
20.538 0.538 tNET RR 1 u_psram_top/u_psram_sync/lock_cnt_13_s1/CLK
20.242 -0.296 tSu 1 u_psram_top/u_psram_sync/lock_cnt_13_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.003, 43.522%; route: 3.557, 51.555%; tC2Q: 0.340, 4.923%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 5

Path Summary:
Slack 12.805
Data Arrival Time 7.437
Data Required Time 20.242
From u_psram_top/u_psram_sync/cs_memsync_5_s0
To u_psram_top/u_psram_sync/flag_0_s5
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 31 clk_ibuf/O
0.538 0.538 tNET RR 1 u_psram_top/u_psram_sync/cs_memsync_5_s0/CLK
0.878 0.340 tC2Q RF 8 u_psram_top/u_psram_sync/cs_memsync_5_s0/Q
1.589 0.711 tNET FF 1 u_psram_top/u_psram_sync/ns_memsync_1_s14/I1
2.403 0.814 tINS FF 4 u_psram_top/u_psram_sync/ns_memsync_1_s14/F
3.115 0.711 tNET FF 1 u_psram_top/u_psram_sync/flag_d_0_s13/I2
3.724 0.609 tINS FF 2 u_psram_top/u_psram_sync/flag_d_0_s13/F
4.435 0.711 tNET FF 1 u_psram_top/u_psram_sync/flag_d_0_s12/I1
5.249 0.814 tINS FF 1 u_psram_top/u_psram_sync/flag_d_0_s12/F
5.961 0.711 tNET FF 1 u_psram_top/u_psram_sync/flag_d_0_s15/I0
6.726 0.765 tINS FF 1 u_psram_top/u_psram_sync/flag_d_0_s15/F
7.437 0.711 tNET FF 1 u_psram_top/u_psram_sync/flag_0_s5/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 31 clk_ibuf/O
20.538 0.538 tNET RR 1 u_psram_top/u_psram_sync/flag_0_s5/CLK
20.242 -0.296 tSu 1 u_psram_top/u_psram_sync/flag_0_s5
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.003, 43.522%; route: 3.557, 51.555%; tC2Q: 0.340, 4.923%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%