Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.8.10\IDE\ipcore\RiscVN25\data\AE250.v
D:\Gowin\Gowin_V1.9.8.10\IDE\ipcore\RiscVN25\data\ae250_chip_wrap.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.10
Part Number GW2A-LV55PG484C8/I7
Device GW2A-55
Device Version C
Created Time Wed Dec 21 14:54:39 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module RiscV_AE250_Top
Synthesis Process Running parser:
    CPU time = 0h 1m 42s, Elapsed time = 0h 1m 42s, Peak memory usage = 1280.449MB
Running netlist conversion:
    CPU time = 0h 0m 0.859s, Elapsed time = 0h 0m 0.877s, Peak memory usage = 1280.449MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 1280.449MB
    Optimizing Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1280.449MB
    Optimizing Phase 2: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 1280.449MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1280.449MB
    Inferring Phase 1: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.207s, Peak memory usage = 1280.449MB
    Inferring Phase 2: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.228s, Peak memory usage = 1280.449MB
    Inferring Phase 3: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 1280.449MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 1280.449MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1280.449MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1280.449MB
    Tech-Mapping Phase 3: CPU time = 0h 1m 30s, Elapsed time = 0h 1m 30s, Peak memory usage = 1280.449MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 1280.449MB
Generate output files:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1280.449MB
Total Time and Memory Usage CPU time = 0h 3m 35s, Elapsed time = 0h 3m 35s, Peak memory usage = 1280.449MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 139
I/O Buf 127
    IBUF 10
    OBUF 73
    TBUF 35
    IOBUF 9
Register 6639
    DFF 4
    DFFE 1882
    DFFSE 10
    DFFRE 500
    DFFP 52
    DFFPE 120
    DFFC 390
    DFFCE 3675
    DFFNC 1
    DFFNCE 3
    DL 1
    DLN 1
LUT 17016
    LUT2 1282
    LUT3 5855
    LUT4 9879
ALU 1276
    ALU 1276
SSRAM 42
    RAM16SDP4 42
INV 37
    INV 37
DSP 1
    MULTALU36X18 1
BSRAM 64
    SP 64

Resource Utilization Summary

Resource Usage Utilization
Logic 18581(17053 LUTs, 1276 ALUs, 42 SSRAMs) / 54720 34%
Register 6639 / 41997 16%
  --Register as Latch 2 / 41997 <1%
  --Register as FF 6637 / 41997 16%
BSRAM 64 / 140 46%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
X_oschin Base 10.000 100.0 0.000 5.000 X_oschin_ibuf/I
X_osclin Base 10.000 100.0 0.000 5.000 X_osclin_ibuf/I
X_tck Base 10.000 100.0 0.000 5.000 X_tck_ibuf/I
spi_r_clk Base 10.000 100.0 0.000 5.000 ae250_chip/gen_SPI1_SUPPORT.u_spi1/u_spi_spiif/n314_s0/F

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 X_oschin 100.0(MHz) 64.8(MHz) 25 TOP
2 X_osclin 100.0(MHz) 1984.1(MHz) 1 TOP
3 X_tck 100.0(MHz) 191.3(MHz) 4 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -5.438
Data Arrival Time 16.265
Data Required Time 10.828
From ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig1.reg_trig1_addr_1_s0
To ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_reg_0_s0
Launch Clk X_oschin[R]
Latch Clk X_oschin[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 X_oschin
0.000 0.000 tCL RR 1 X_oschin_ibuf/I
0.683 0.683 tINS RR 6641 X_oschin_ibuf/O
0.863 0.180 tNET RR 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig1.reg_trig1_addr_1_s0/CLK
1.095 0.232 tC2Q RF 8 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig1.reg_trig1_addr_1_s0/Q
1.332 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4886_s1/I1
1.887 0.555 tINS FF 4 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4886_s1/F
2.124 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4882_s3/I3
2.495 0.371 tINS FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4882_s3/F
2.732 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4888_s2/I2
3.185 0.453 tINS FF 5 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4888_s2/F
3.422 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4890_s2/I3
3.793 0.371 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4890_s2/F
4.030 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4890_s3/I0
4.547 0.517 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4890_s3/F
4.784 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4889_s1/I3
5.155 0.371 tINS FF 4 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4889_s1/F
5.392 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4888_s1/I2
5.845 0.453 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4888_s1/F
6.082 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4882_s1/I0
6.599 0.517 tINS FF 9 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4882_s1/F
6.836 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4885_s1/I3
7.207 0.371 tINS FF 4 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4885_s1/F
7.444 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4885_s0/I0
7.961 0.517 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4885_s0/F
8.198 0.237 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4949_s0/I0
8.747 0.549 tINS FR 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4949_s0/COUT
8.747 0.000 tNET RR 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4950_s0/CIN
8.782 0.035 tINS RF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4950_s0/COUT
8.782 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4951_s0/CIN
8.817 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4951_s0/COUT
8.817 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4952_s0/CIN
8.852 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4952_s0/COUT
8.852 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4953_s0/CIN
8.887 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4953_s0/COUT
8.887 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4954_s0/CIN
8.923 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4954_s0/COUT
8.923 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4955_s0/CIN
8.958 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4955_s0/COUT
8.958 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4956_s0/CIN
8.993 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4956_s0/COUT
8.993 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4957_s0/CIN
9.028 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4957_s0/COUT
9.028 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4958_s0/CIN
9.063 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4958_s0/COUT
9.063 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4959_s0/CIN
9.099 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4959_s0/COUT
9.099 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4960_s0/CIN
9.134 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4960_s0/COUT
9.134 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4961_s0/CIN
9.169 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4961_s0/COUT
9.169 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4962_s0/CIN
9.204 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4962_s0/COUT
9.204 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4963_s0/CIN
9.239 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4963_s0/COUT
9.239 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4964_s0/CIN
9.275 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4964_s0/COUT
9.275 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4965_s0/CIN
9.310 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4965_s0/COUT
9.310 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4966_s0/CIN
9.345 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4966_s0/COUT
9.345 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4967_s0/CIN
9.380 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4967_s0/COUT
9.380 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4968_s0/CIN
9.415 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4968_s0/COUT
9.415 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4969_s0/CIN
9.451 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4969_s0/COUT
9.451 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4970_s0/CIN
9.486 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4970_s0/COUT
9.486 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4971_s0/CIN
9.521 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4971_s0/COUT
9.521 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4972_s0/CIN
9.556 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4972_s0/COUT
9.556 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4973_s0/CIN
9.591 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4973_s0/COUT
9.591 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4974_s0/CIN
9.627 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4974_s0/COUT
9.627 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4975_s0/CIN
9.662 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4975_s0/COUT
9.662 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4976_s0/CIN
9.697 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4976_s0/COUT
9.697 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4977_s0/CIN
9.732 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4977_s0/COUT
9.969 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s13/I0
10.486 0.517 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s13/F
10.723 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s9/I3
11.094 0.371 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s9/F
11.331 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s3/I3
11.702 0.371 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s3/F
11.939 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/gen_reg_insert_hss.reg_mm_trigm_halt_after_set_s52/I3
12.310 0.371 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/gen_reg_insert_hss.reg_mm_trigm_halt_after_set_s52/F
12.547 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/gen_reg_insert_hss.reg_mm_trigm_halt_after_set_s9/I2
13.000 0.453 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/gen_reg_insert_hss.reg_mm_trigm_halt_after_set_s9/F
13.237 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/mm_xcpt_s4/I2
13.690 0.453 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/mm_xcpt_s4/F
13.927 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/vc_biu_path/path0_sync_addr_0_s1/I0
14.444 0.517 tINS FF 44 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/vc_biu_path/path0_sync_addr_0_s1/F
14.681 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n878_s0/I1
15.236 0.555 tINS FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n878_s0/F
15.473 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n705_s1/I1
16.028 0.555 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n705_s1/F
16.265 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_reg_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 X_oschin
10.000 0.000 tCL RR 1 X_oschin_ibuf/I
10.682 0.683 tINS RR 6641 X_oschin_ibuf/O
10.863 0.180 tNET RR 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_reg_0_s0/CLK
10.828 -0.035 tSu 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_reg_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 25
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 10.194, 66.181%; route: 4.977, 32.313%; tC2Q: 0.232, 1.506%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack -5.438
Data Arrival Time 16.265
Data Required Time 10.828
From ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig1.reg_trig1_addr_1_s0
To ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_reg_1_s0
Launch Clk X_oschin[R]
Latch Clk X_oschin[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 X_oschin
0.000 0.000 tCL RR 1 X_oschin_ibuf/I
0.683 0.683 tINS RR 6641 X_oschin_ibuf/O
0.863 0.180 tNET RR 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig1.reg_trig1_addr_1_s0/CLK
1.095 0.232 tC2Q RF 8 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig1.reg_trig1_addr_1_s0/Q
1.332 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4886_s1/I1
1.887 0.555 tINS FF 4 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4886_s1/F
2.124 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4882_s3/I3
2.495 0.371 tINS FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4882_s3/F
2.732 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4888_s2/I2
3.185 0.453 tINS FF 5 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4888_s2/F
3.422 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4890_s2/I3
3.793 0.371 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4890_s2/F
4.030 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4890_s3/I0
4.547 0.517 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4890_s3/F
4.784 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4889_s1/I3
5.155 0.371 tINS FF 4 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4889_s1/F
5.392 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4888_s1/I2
5.845 0.453 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4888_s1/F
6.082 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4882_s1/I0
6.599 0.517 tINS FF 9 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4882_s1/F
6.836 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4885_s1/I3
7.207 0.371 tINS FF 4 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4885_s1/F
7.444 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4885_s0/I0
7.961 0.517 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4885_s0/F
8.198 0.237 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4949_s0/I0
8.747 0.549 tINS FR 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4949_s0/COUT
8.747 0.000 tNET RR 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4950_s0/CIN
8.782 0.035 tINS RF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4950_s0/COUT
8.782 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4951_s0/CIN
8.817 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4951_s0/COUT
8.817 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4952_s0/CIN
8.852 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4952_s0/COUT
8.852 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4953_s0/CIN
8.887 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4953_s0/COUT
8.887 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4954_s0/CIN
8.923 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4954_s0/COUT
8.923 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4955_s0/CIN
8.958 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4955_s0/COUT
8.958 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4956_s0/CIN
8.993 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4956_s0/COUT
8.993 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4957_s0/CIN
9.028 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4957_s0/COUT
9.028 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4958_s0/CIN
9.063 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4958_s0/COUT
9.063 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4959_s0/CIN
9.099 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4959_s0/COUT
9.099 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4960_s0/CIN
9.134 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4960_s0/COUT
9.134 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4961_s0/CIN
9.169 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4961_s0/COUT
9.169 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4962_s0/CIN
9.204 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4962_s0/COUT
9.204 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4963_s0/CIN
9.239 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4963_s0/COUT
9.239 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4964_s0/CIN
9.275 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4964_s0/COUT
9.275 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4965_s0/CIN
9.310 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4965_s0/COUT
9.310 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4966_s0/CIN
9.345 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4966_s0/COUT
9.345 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4967_s0/CIN
9.380 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4967_s0/COUT
9.380 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4968_s0/CIN
9.415 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4968_s0/COUT
9.415 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4969_s0/CIN
9.451 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4969_s0/COUT
9.451 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4970_s0/CIN
9.486 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4970_s0/COUT
9.486 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4971_s0/CIN
9.521 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4971_s0/COUT
9.521 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4972_s0/CIN
9.556 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4972_s0/COUT
9.556 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4973_s0/CIN
9.591 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4973_s0/COUT
9.591 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4974_s0/CIN
9.627 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4974_s0/COUT
9.627 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4975_s0/CIN
9.662 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4975_s0/COUT
9.662 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4976_s0/CIN
9.697 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4976_s0/COUT
9.697 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4977_s0/CIN
9.732 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4977_s0/COUT
9.969 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s13/I0
10.486 0.517 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s13/F
10.723 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s9/I3
11.094 0.371 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s9/F
11.331 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s3/I3
11.702 0.371 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s3/F
11.939 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/gen_reg_insert_hss.reg_mm_trigm_halt_after_set_s52/I3
12.310 0.371 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/gen_reg_insert_hss.reg_mm_trigm_halt_after_set_s52/F
12.547 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/gen_reg_insert_hss.reg_mm_trigm_halt_after_set_s9/I2
13.000 0.453 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/gen_reg_insert_hss.reg_mm_trigm_halt_after_set_s9/F
13.237 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/mm_xcpt_s4/I2
13.690 0.453 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/mm_xcpt_s4/F
13.927 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/vc_biu_path/path0_sync_addr_0_s1/I0
14.444 0.517 tINS FF 44 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/vc_biu_path/path0_sync_addr_0_s1/F
14.681 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n704_s3/I1
15.236 0.555 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n704_s3/F
15.473 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n704_s1/I1
16.028 0.555 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n704_s1/F
16.265 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_reg_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 X_oschin
10.000 0.000 tCL RR 1 X_oschin_ibuf/I
10.682 0.683 tINS RR 6641 X_oschin_ibuf/O
10.863 0.180 tNET RR 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_reg_1_s0/CLK
10.828 -0.035 tSu 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_reg_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 25
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 10.194, 66.181%; route: 4.977, 32.313%; tC2Q: 0.232, 1.506%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack -5.438
Data Arrival Time 16.265
Data Required Time 10.828
From ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig1.reg_trig1_addr_1_s0
To ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/mm_trigm_hit_after_s0
Launch Clk X_oschin[R]
Latch Clk X_oschin[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 X_oschin
0.000 0.000 tCL RR 1 X_oschin_ibuf/I
0.683 0.683 tINS RR 6641 X_oschin_ibuf/O
0.863 0.180 tNET RR 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig1.reg_trig1_addr_1_s0/CLK
1.095 0.232 tC2Q RF 8 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig1.reg_trig1_addr_1_s0/Q
1.332 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4886_s1/I1
1.887 0.555 tINS FF 4 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4886_s1/F
2.124 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4882_s3/I3
2.495 0.371 tINS FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4882_s3/F
2.732 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4888_s2/I2
3.185 0.453 tINS FF 5 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4888_s2/F
3.422 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4890_s2/I3
3.793 0.371 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4890_s2/F
4.030 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4890_s3/I0
4.547 0.517 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4890_s3/F
4.784 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4889_s1/I3
5.155 0.371 tINS FF 4 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4889_s1/F
5.392 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4888_s1/I2
5.845 0.453 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4888_s1/F
6.082 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4882_s1/I0
6.599 0.517 tINS FF 9 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4882_s1/F
6.836 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4885_s1/I3
7.207 0.371 tINS FF 4 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4885_s1/F
7.444 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4885_s0/I0
7.961 0.517 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4885_s0/F
8.198 0.237 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4949_s0/I0
8.747 0.549 tINS FR 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4949_s0/COUT
8.747 0.000 tNET RR 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4950_s0/CIN
8.782 0.035 tINS RF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4950_s0/COUT
8.782 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4951_s0/CIN
8.817 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4951_s0/COUT
8.817 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4952_s0/CIN
8.852 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4952_s0/COUT
8.852 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4953_s0/CIN
8.887 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4953_s0/COUT
8.887 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4954_s0/CIN
8.923 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4954_s0/COUT
8.923 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4955_s0/CIN
8.958 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4955_s0/COUT
8.958 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4956_s0/CIN
8.993 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4956_s0/COUT
8.993 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4957_s0/CIN
9.028 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4957_s0/COUT
9.028 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4958_s0/CIN
9.063 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4958_s0/COUT
9.063 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4959_s0/CIN
9.099 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4959_s0/COUT
9.099 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4960_s0/CIN
9.134 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4960_s0/COUT
9.134 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4961_s0/CIN
9.169 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4961_s0/COUT
9.169 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4962_s0/CIN
9.204 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4962_s0/COUT
9.204 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4963_s0/CIN
9.239 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4963_s0/COUT
9.239 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4964_s0/CIN
9.275 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4964_s0/COUT
9.275 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4965_s0/CIN
9.310 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4965_s0/COUT
9.310 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4966_s0/CIN
9.345 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4966_s0/COUT
9.345 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4967_s0/CIN
9.380 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4967_s0/COUT
9.380 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4968_s0/CIN
9.415 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4968_s0/COUT
9.415 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4969_s0/CIN
9.451 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4969_s0/COUT
9.451 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4970_s0/CIN
9.486 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4970_s0/COUT
9.486 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4971_s0/CIN
9.521 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4971_s0/COUT
9.521 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4972_s0/CIN
9.556 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4972_s0/COUT
9.556 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4973_s0/CIN
9.591 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4973_s0/COUT
9.591 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4974_s0/CIN
9.627 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4974_s0/COUT
9.627 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4975_s0/CIN
9.662 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4975_s0/COUT
9.662 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4976_s0/CIN
9.697 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4976_s0/COUT
9.697 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4977_s0/CIN
9.732 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4977_s0/COUT
9.969 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s13/I0
10.486 0.517 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s13/F
10.723 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s9/I3
11.094 0.371 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s9/F
11.331 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s3/I3
11.702 0.371 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s3/F
11.939 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/gen_reg_insert_hss.reg_mm_trigm_halt_after_set_s52/I3
12.310 0.371 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/gen_reg_insert_hss.reg_mm_trigm_halt_after_set_s52/F
12.547 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/gen_reg_insert_hss.reg_mm_trigm_halt_after_set_s9/I2
13.000 0.453 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/gen_reg_insert_hss.reg_mm_trigm_halt_after_set_s9/F
13.237 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/gen_reg_insert_hss.reg_mm_trigm_halt_after_set_s6/I1
13.792 0.555 tINS FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/gen_reg_insert_hss.reg_mm_trigm_halt_after_set_s6/F
14.029 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/mm_trigm_hit_after_nx_s6/I0
14.546 0.517 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/mm_trigm_hit_after_nx_s6/F
14.783 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/mm_trigm_hit_after_nx_s3/I1
15.338 0.555 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/mm_trigm_hit_after_nx_s3/F
15.575 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/mm_trigm_hit_after_nx_s0/I2
16.028 0.453 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/mm_trigm_hit_after_nx_s0/F
16.265 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/mm_trigm_hit_after_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 X_oschin
10.000 0.000 tCL RR 1 X_oschin_ibuf/I
10.682 0.683 tINS RR 6641 X_oschin_ibuf/O
10.863 0.180 tNET RR 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/mm_trigm_hit_after_s0/CLK
10.828 -0.035 tSu 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/mm_trigm_hit_after_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 25
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 10.194, 66.181%; route: 4.977, 32.313%; tC2Q: 0.232, 1.506%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack -5.400
Data Arrival Time 16.227
Data Required Time 10.828
From ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig1.reg_trig1_addr_1_s0
To ae250_chip/uncore/vc_core_mem/vc_core/vc_dcu/biu_load_issued_s4
Launch Clk X_oschin[R]
Latch Clk X_oschin[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 X_oschin
0.000 0.000 tCL RR 1 X_oschin_ibuf/I
0.683 0.683 tINS RR 6641 X_oschin_ibuf/O
0.863 0.180 tNET RR 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig1.reg_trig1_addr_1_s0/CLK
1.095 0.232 tC2Q RF 8 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig1.reg_trig1_addr_1_s0/Q
1.332 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4886_s1/I1
1.887 0.555 tINS FF 4 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4886_s1/F
2.124 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4882_s3/I3
2.495 0.371 tINS FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4882_s3/F
2.732 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4888_s2/I2
3.185 0.453 tINS FF 5 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4888_s2/F
3.422 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4890_s2/I3
3.793 0.371 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4890_s2/F
4.030 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4890_s3/I0
4.547 0.517 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4890_s3/F
4.784 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4889_s1/I3
5.155 0.371 tINS FF 4 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4889_s1/F
5.392 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4888_s1/I2
5.845 0.453 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4888_s1/F
6.082 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4882_s1/I0
6.599 0.517 tINS FF 9 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4882_s1/F
6.836 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4885_s1/I3
7.207 0.371 tINS FF 4 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4885_s1/F
7.444 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4885_s0/I0
7.961 0.517 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4885_s0/F
8.198 0.237 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4949_s0/I0
8.747 0.549 tINS FR 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4949_s0/COUT
8.747 0.000 tNET RR 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4950_s0/CIN
8.782 0.035 tINS RF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4950_s0/COUT
8.782 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4951_s0/CIN
8.817 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4951_s0/COUT
8.817 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4952_s0/CIN
8.852 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4952_s0/COUT
8.852 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4953_s0/CIN
8.887 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4953_s0/COUT
8.887 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4954_s0/CIN
8.923 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4954_s0/COUT
8.923 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4955_s0/CIN
8.958 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4955_s0/COUT
8.958 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4956_s0/CIN
8.993 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4956_s0/COUT
8.993 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4957_s0/CIN
9.028 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4957_s0/COUT
9.028 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4958_s0/CIN
9.063 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4958_s0/COUT
9.063 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4959_s0/CIN
9.099 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4959_s0/COUT
9.099 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4960_s0/CIN
9.134 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4960_s0/COUT
9.134 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4961_s0/CIN
9.169 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4961_s0/COUT
9.169 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4962_s0/CIN
9.204 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4962_s0/COUT
9.204 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4963_s0/CIN
9.239 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4963_s0/COUT
9.239 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4964_s0/CIN
9.275 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4964_s0/COUT
9.275 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4965_s0/CIN
9.310 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4965_s0/COUT
9.310 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4966_s0/CIN
9.345 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4966_s0/COUT
9.345 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4967_s0/CIN
9.380 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4967_s0/COUT
9.380 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4968_s0/CIN
9.415 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4968_s0/COUT
9.415 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4969_s0/CIN
9.451 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4969_s0/COUT
9.451 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4970_s0/CIN
9.486 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4970_s0/COUT
9.486 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4971_s0/CIN
9.521 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4971_s0/COUT
9.521 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4972_s0/CIN
9.556 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4972_s0/COUT
9.556 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4973_s0/CIN
9.591 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4973_s0/COUT
9.591 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4974_s0/CIN
9.627 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4974_s0/COUT
9.627 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4975_s0/CIN
9.662 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4975_s0/COUT
9.662 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4976_s0/CIN
9.697 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4976_s0/COUT
9.697 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4977_s0/CIN
9.732 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4977_s0/COUT
9.969 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s13/I0
10.486 0.517 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s13/F
10.723 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s9/I3
11.094 0.371 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s9/F
11.331 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s3/I3
11.702 0.371 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s3/F
11.939 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/gen_reg_insert_hss.reg_mm_trigm_halt_after_set_s52/I3
12.310 0.371 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/gen_reg_insert_hss.reg_mm_trigm_halt_after_set_s52/F
12.547 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/gen_reg_insert_hss.reg_mm_trigm_halt_after_set_s9/I2
13.000 0.453 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/gen_reg_insert_hss.reg_mm_trigm_halt_after_set_s9/F
13.237 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/mm_xcpt_s4/I2
13.690 0.453 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/mm_xcpt_s4/F
13.927 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/vc_biu_path/path0_sync_addr_0_s1/I0
14.444 0.517 tINS FF 44 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/vc_biu_path/path0_sync_addr_0_s1/F
14.681 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_dcu/biu_load_issued_set_s3/I0
15.198 0.517 tINS FF 7 ae250_chip/uncore/vc_core_mem/vc_core/vc_dcu/biu_load_issued_set_s3/F
15.435 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_dcu/biu_miss_req_issued_set_s1/I1
15.990 0.555 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_dcu/biu_miss_req_issued_set_s1/F
16.227 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_dcu/biu_load_issued_s4/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 X_oschin
10.000 0.000 tCL RR 1 X_oschin_ibuf/I
10.682 0.683 tINS RR 6641 X_oschin_ibuf/O
10.863 0.180 tNET RR 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_dcu/biu_load_issued_s4/CLK
10.828 -0.035 tSu 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_dcu/biu_load_issued_s4
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 25
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 10.156, 66.097%; route: 4.977, 32.393%; tC2Q: 0.232, 1.510%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack -5.400
Data Arrival Time 16.227
Data Required Time 10.828
From ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig1.reg_trig1_addr_1_s0
To ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_valid_s1
Launch Clk X_oschin[R]
Latch Clk X_oschin[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 X_oschin
0.000 0.000 tCL RR 1 X_oschin_ibuf/I
0.683 0.683 tINS RR 6641 X_oschin_ibuf/O
0.863 0.180 tNET RR 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig1.reg_trig1_addr_1_s0/CLK
1.095 0.232 tC2Q RF 8 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig1.reg_trig1_addr_1_s0/Q
1.332 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4886_s1/I1
1.887 0.555 tINS FF 4 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4886_s1/F
2.124 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4882_s3/I3
2.495 0.371 tINS FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4882_s3/F
2.732 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4888_s2/I2
3.185 0.453 tINS FF 5 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4888_s2/F
3.422 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4890_s2/I3
3.793 0.371 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4890_s2/F
4.030 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4890_s3/I0
4.547 0.517 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4890_s3/F
4.784 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4889_s1/I3
5.155 0.371 tINS FF 4 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4889_s1/F
5.392 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4888_s1/I2
5.845 0.453 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4888_s1/F
6.082 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4882_s1/I0
6.599 0.517 tINS FF 9 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4882_s1/F
6.836 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4885_s1/I3
7.207 0.371 tINS FF 4 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4885_s1/F
7.444 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4885_s0/I0
7.961 0.517 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4885_s0/F
8.198 0.237 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4949_s0/I0
8.747 0.549 tINS FR 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4949_s0/COUT
8.747 0.000 tNET RR 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4950_s0/CIN
8.782 0.035 tINS RF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4950_s0/COUT
8.782 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4951_s0/CIN
8.817 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4951_s0/COUT
8.817 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4952_s0/CIN
8.852 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4952_s0/COUT
8.852 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4953_s0/CIN
8.887 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4953_s0/COUT
8.887 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4954_s0/CIN
8.923 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4954_s0/COUT
8.923 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4955_s0/CIN
8.958 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4955_s0/COUT
8.958 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4956_s0/CIN
8.993 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4956_s0/COUT
8.993 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4957_s0/CIN
9.028 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4957_s0/COUT
9.028 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4958_s0/CIN
9.063 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4958_s0/COUT
9.063 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4959_s0/CIN
9.099 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4959_s0/COUT
9.099 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4960_s0/CIN
9.134 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4960_s0/COUT
9.134 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4961_s0/CIN
9.169 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4961_s0/COUT
9.169 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4962_s0/CIN
9.204 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4962_s0/COUT
9.204 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4963_s0/CIN
9.239 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4963_s0/COUT
9.239 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4964_s0/CIN
9.275 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4964_s0/COUT
9.275 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4965_s0/CIN
9.310 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4965_s0/COUT
9.310 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4966_s0/CIN
9.345 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4966_s0/COUT
9.345 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4967_s0/CIN
9.380 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4967_s0/COUT
9.380 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4968_s0/CIN
9.415 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4968_s0/COUT
9.415 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4969_s0/CIN
9.451 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4969_s0/COUT
9.451 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4970_s0/CIN
9.486 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4970_s0/COUT
9.486 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4971_s0/CIN
9.521 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4971_s0/COUT
9.521 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4972_s0/CIN
9.556 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4972_s0/COUT
9.556 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4973_s0/CIN
9.591 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4973_s0/COUT
9.591 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4974_s0/CIN
9.627 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4974_s0/COUT
9.627 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4975_s0/CIN
9.662 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4975_s0/COUT
9.662 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4976_s0/CIN
9.697 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4976_s0/COUT
9.697 0.000 tNET FF 2 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4977_s0/CIN
9.732 0.035 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4977_s0/COUT
9.969 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s13/I0
10.486 0.517 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s13/F
10.723 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s9/I3
11.094 0.371 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s9/F
11.331 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s3/I3
11.702 0.371 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s3/F
11.939 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/gen_reg_insert_hss.reg_mm_trigm_halt_after_set_s52/I3
12.310 0.371 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/gen_reg_insert_hss.reg_mm_trigm_halt_after_set_s52/F
12.547 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/gen_reg_insert_hss.reg_mm_trigm_halt_after_set_s9/I2
13.000 0.453 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/gen_reg_insert_hss.reg_mm_trigm_halt_after_set_s9/F
13.237 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/mm_xcpt_s4/I2
13.690 0.453 tINS FF 3 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/mm_xcpt_s4/F
13.927 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_trap_ret_nx_s1/I0
14.444 0.517 tINS FF 7 ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_trap_ret_nx_s1/F
14.681 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/ahb_cmd_en_s1/I0
15.198 0.517 tINS FF 5 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/ahb_cmd_en_s1/F
15.435 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n914_s0/I1
15.990 0.555 tINS FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n914_s0/F
16.227 0.237 tNET FF 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_valid_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 X_oschin
10.000 0.000 tCL RR 1 X_oschin_ibuf/I
10.682 0.683 tINS RR 6641 X_oschin_ibuf/O
10.863 0.180 tNET RR 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_valid_s1/CLK
10.828 -0.035 tSu 1 ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_valid_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 25
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 10.156, 66.097%; route: 4.977, 32.393%; tC2Q: 0.232, 1.510%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%