Synthesis Messages

Report Title	GowinSynthesis Report
Design File	D:\Gowin\Gowin_V1.9.8.10\IDE\ipcore\RiscVN25\data\AE250.v D:\Gowin\Gowin_V1.9.8.10\IDE\ipcore\RiscVN25\data\ae250_chip_wrap.v
GowinSynthesis Constraints File	---
Version	GowinSynthesis V1.9.8.10
Part Number	GW2A-LV18PG256C8/I7
Device	GW2A-18
Device Version	C
Created Time	Wed Dec 21 09:57:03 2022
Legal Announcement	Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	RiscV_AE250_Top
Synthesis Process	Running parser:     CPU time = 0h 1m 47s, Elapsed time = 0h 1m 48s, Peak memory usage = 1279.793MB Running netlist conversion:     CPU time = 0h 0m 0.89s, Elapsed time = 0h 0m 0.934s, Peak memory usage = 1279.793MB Running device independent optimization:     Optimizing Phase 0: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 1279.793MB     Optimizing Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1279.793MB     Optimizing Phase 2: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 1279.793MB Running inference:     Inferring Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1279.793MB     Inferring Phase 1: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.244s, Peak memory usage = 1279.793MB     Inferring Phase 2: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.232s, Peak memory usage = 1279.793MB     Inferring Phase 3: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.062s, Peak memory usage = 1279.793MB Running technical mapping:     Tech-Mapping Phase 0: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 1279.793MB     Tech-Mapping Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1279.793MB     Tech-Mapping Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1279.793MB     Tech-Mapping Phase 3: CPU time = 0h 1m 32s, Elapsed time = 0h 1m 33s, Peak memory usage = 1279.793MB     Tech-Mapping Phase 4: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 1279.793MB Generate output files:     CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 1279.793MB
Total Time and Memory Usage	CPU time = 0h 3m 42s, Elapsed time = 0h 3m 45s, Peak memory usage = 1279.793MB

Resource

Resource Usage Summary

Resource	Usage
I/O Port	139
I/O Buf	127
IBUF	10
OBUF	73
TBUF	35
IOBUF	9
Register	6639
DFF	4
DFFE	1882
DFFSE	10
DFFRE	500
DFFP	51
DFFPE	121
DFFC	394
DFFCE	3671
DFFNC	1
DFFNCE	3
DL	1
DLN	1
LUT	17124
LUT2	1287
LUT3	6085
LUT4	9752
ALU	1277
ALU	1277
SSRAM	42
RAM16SDP4	42
INV	35
INV	35
DSP	1
MULTALU36X18	1
BSRAM	32
SP	32

Resource Utilization Summary

Resource	Usage	Utilization
Logic	18688(17159 LUTs, 1277 ALUs, 42 SSRAMs) / 20736	91%
Register	6639 / 16173	42%
--Register as Latch	2 / 16173	<1%
--Register as FF	6637 / 16173	42%
BSRAM	32 / 46	70%

Timing

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Object
X_oschin	Base	10.000	100.0	0.000	5.000			X_oschin_ibuf/I
X_osclin	Base	10.000	100.0	0.000	5.000			X_osclin_ibuf/I
X_tck	Base	10.000	100.0	0.000	5.000			X_tck_ibuf/I
spi_r_clk	Base	10.000	100.0	0.000	5.000			ae250_chip/gen_SPI1_SUPPORT.u_spi1/u_spi_spiif/n314_s0/F

Max Frequency Summary:

No.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	X_oschin	100.0(MHz)	66.3(MHz)	24	TOP
2	X_osclin	100.0(MHz)	1984.1(MHz)	1	TOP
3	X_tck	100.0(MHz)	148.5(MHz)	5	TOP

Detail Timing Paths Information

Path 1

Path Summary:

Slack	-5.073
Data Arrival Time	15.900
Data Required Time	10.828
From	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig0.reg_trig0_addr_1_s0
To	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_reg_0_s0
Launch Clk	X_oschin[R]
Latch Clk	X_oschin[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				X_oschin
0.000	0.000	tCL	RR	1	X_oschin_ibuf/I
0.683	0.683	tINS	RR	6609	X_oschin_ibuf/O
0.863	0.180	tNET	RR	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig0.reg_trig0_addr_1_s0/CLK
1.095	0.232	tC2Q	RF	8	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig0.reg_trig0_addr_1_s0/Q
1.332	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4526_s1/I1
1.887	0.555	tINS	FF	4	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4526_s1/F
2.124	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4522_s3/I3
2.495	0.371	tINS	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4522_s3/F
2.732	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4528_s2/I2
3.185	0.453	tINS	FF	5	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4528_s2/F
3.422	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4530_s2/I3
3.793	0.371	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4530_s2/F
4.030	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4530_s3/I0
4.547	0.517	tINS	FF	3	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4530_s3/F
4.784	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4529_s1/I3
5.155	0.371	tINS	FF	4	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4529_s1/F
5.392	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4528_s1/I2
5.845	0.453	tINS	FF	3	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4528_s1/F
6.082	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4522_s1/I0
6.599	0.517	tINS	FF	9	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4522_s1/F
6.836	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4525_s1/I3
7.207	0.371	tINS	FF	4	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4525_s1/F
7.444	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4557_s2/I0
7.961	0.517	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4557_s2/F
8.198	0.237	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4589_s0/I1
8.768	0.570	tINS	FR	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4589_s0/COUT
8.768	0.000	tNET	RR	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4590_s0/CIN
8.803	0.035	tINS	RF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4590_s0/COUT
8.803	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4591_s0/CIN
8.838	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4591_s0/COUT
8.838	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4592_s0/CIN
8.873	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4592_s0/COUT
8.873	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4593_s0/CIN
8.908	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4593_s0/COUT
8.908	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4594_s0/CIN
8.944	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4594_s0/COUT
8.944	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4595_s0/CIN
8.979	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4595_s0/COUT
8.979	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4596_s0/CIN
9.014	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4596_s0/COUT
9.014	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4597_s0/CIN
9.049	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4597_s0/COUT
9.049	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4598_s0/CIN
9.084	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4598_s0/COUT
9.084	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4599_s0/CIN
9.120	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4599_s0/COUT
9.120	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4600_s0/CIN
9.155	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4600_s0/COUT
9.155	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4601_s0/CIN
9.190	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4601_s0/COUT
9.190	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4602_s0/CIN
9.225	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4602_s0/COUT
9.225	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4603_s0/CIN
9.260	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4603_s0/COUT
9.260	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4604_s0/CIN
9.296	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4604_s0/COUT
9.296	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4605_s0/CIN
9.331	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4605_s0/COUT
9.331	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4606_s0/CIN
9.366	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4606_s0/COUT
9.366	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4607_s0/CIN
9.401	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4607_s0/COUT
9.401	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4608_s0/CIN
9.436	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4608_s0/COUT
9.436	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4609_s0/CIN
9.472	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4609_s0/COUT
9.472	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4610_s0/CIN
9.507	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4610_s0/COUT
9.507	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4611_s0/CIN
9.542	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4611_s0/COUT
9.542	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4612_s0/CIN
9.577	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4612_s0/COUT
9.577	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4613_s0/CIN
9.612	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4613_s0/COUT
9.612	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4614_s0/CIN
9.648	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4614_s0/COUT
9.648	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4615_s0/CIN
9.683	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4615_s0/COUT
9.683	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4616_s0/CIN
9.718	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4616_s0/COUT
9.718	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4617_s0/CIN
9.753	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4617_s0/COUT
9.990	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s23/I0
10.507	0.517	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s23/F
10.744	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s14/I2
11.197	0.453	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s14/F
11.434	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s7/I3
11.805	0.371	tINS	FF	6	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s7/F
12.042	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n878_s7/I1
12.597	0.555	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n878_s7/F
12.834	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n878_s1/I2
13.287	0.453	tINS	FF	8	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n878_s1/F
13.524	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/vc_biu_path/path0_sync_addr_0_s1/I1
14.079	0.555	tINS	FF	8	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/vc_biu_path/path0_sync_addr_0_s1/F
14.316	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n705_s2/I1
14.871	0.555	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n705_s2/F
15.108	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n705_s1/I1
15.663	0.555	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n705_s1/F
15.900	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_reg_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				X_oschin
10.000	0.000	tCL	RR	1	X_oschin_ibuf/I
10.682	0.683	tINS	RR	6609	X_oschin_ibuf/O
10.863	0.180	tNET	RR	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_reg_0_s0/CLK
10.828	-0.035	tSu		1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_reg_0_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	24
Arrival Clock Path Delay:	cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay:	cell: 10.066, 66.936%; route: 4.740, 31.521%; tC2Q: 0.232, 1.543%
Required Clock Path Delay:	cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:

Slack	-5.073
Data Arrival Time	15.900
Data Required Time	10.828
From	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig0.reg_trig0_addr_1_s0
To	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_reg_1_s0
Launch Clk	X_oschin[R]
Latch Clk	X_oschin[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				X_oschin
0.000	0.000	tCL	RR	1	X_oschin_ibuf/I
0.683	0.683	tINS	RR	6609	X_oschin_ibuf/O
0.863	0.180	tNET	RR	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig0.reg_trig0_addr_1_s0/CLK
1.095	0.232	tC2Q	RF	8	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig0.reg_trig0_addr_1_s0/Q
1.332	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4526_s1/I1
1.887	0.555	tINS	FF	4	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4526_s1/F
2.124	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4522_s3/I3
2.495	0.371	tINS	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4522_s3/F
2.732	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4528_s2/I2
3.185	0.453	tINS	FF	5	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4528_s2/F
3.422	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4530_s2/I3
3.793	0.371	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4530_s2/F
4.030	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4530_s3/I0
4.547	0.517	tINS	FF	3	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4530_s3/F
4.784	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4529_s1/I3
5.155	0.371	tINS	FF	4	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4529_s1/F
5.392	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4528_s1/I2
5.845	0.453	tINS	FF	3	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4528_s1/F
6.082	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4522_s1/I0
6.599	0.517	tINS	FF	9	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4522_s1/F
6.836	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4525_s1/I3
7.207	0.371	tINS	FF	4	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4525_s1/F
7.444	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4557_s2/I0
7.961	0.517	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4557_s2/F
8.198	0.237	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4589_s0/I1
8.768	0.570	tINS	FR	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4589_s0/COUT
8.768	0.000	tNET	RR	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4590_s0/CIN
8.803	0.035	tINS	RF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4590_s0/COUT
8.803	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4591_s0/CIN
8.838	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4591_s0/COUT
8.838	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4592_s0/CIN
8.873	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4592_s0/COUT
8.873	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4593_s0/CIN
8.908	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4593_s0/COUT
8.908	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4594_s0/CIN
8.944	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4594_s0/COUT
8.944	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4595_s0/CIN
8.979	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4595_s0/COUT
8.979	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4596_s0/CIN
9.014	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4596_s0/COUT
9.014	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4597_s0/CIN
9.049	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4597_s0/COUT
9.049	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4598_s0/CIN
9.084	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4598_s0/COUT
9.084	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4599_s0/CIN
9.120	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4599_s0/COUT
9.120	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4600_s0/CIN
9.155	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4600_s0/COUT
9.155	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4601_s0/CIN
9.190	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4601_s0/COUT
9.190	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4602_s0/CIN
9.225	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4602_s0/COUT
9.225	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4603_s0/CIN
9.260	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4603_s0/COUT
9.260	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4604_s0/CIN
9.296	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4604_s0/COUT
9.296	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4605_s0/CIN
9.331	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4605_s0/COUT
9.331	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4606_s0/CIN
9.366	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4606_s0/COUT
9.366	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4607_s0/CIN
9.401	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4607_s0/COUT
9.401	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4608_s0/CIN
9.436	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4608_s0/COUT
9.436	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4609_s0/CIN
9.472	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4609_s0/COUT
9.472	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4610_s0/CIN
9.507	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4610_s0/COUT
9.507	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4611_s0/CIN
9.542	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4611_s0/COUT
9.542	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4612_s0/CIN
9.577	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4612_s0/COUT
9.577	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4613_s0/CIN
9.612	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4613_s0/COUT
9.612	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4614_s0/CIN
9.648	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4614_s0/COUT
9.648	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4615_s0/CIN
9.683	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4615_s0/COUT
9.683	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4616_s0/CIN
9.718	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4616_s0/COUT
9.718	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4617_s0/CIN
9.753	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4617_s0/COUT
9.990	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s23/I0
10.507	0.517	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s23/F
10.744	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s14/I2
11.197	0.453	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s14/F
11.434	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s7/I3
11.805	0.371	tINS	FF	6	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s7/F
12.042	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n878_s7/I1
12.597	0.555	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n878_s7/F
12.834	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n878_s1/I2
13.287	0.453	tINS	FF	8	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n878_s1/F
13.524	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/vc_biu_path/path0_sync_addr_0_s1/I1
14.079	0.555	tINS	FF	8	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/vc_biu_path/path0_sync_addr_0_s1/F
14.316	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n704_s3/I1
14.871	0.555	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n704_s3/F
15.108	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n704_s1/I1
15.663	0.555	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n704_s1/F
15.900	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_reg_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				X_oschin
10.000	0.000	tCL	RR	1	X_oschin_ibuf/I
10.682	0.683	tINS	RR	6609	X_oschin_ibuf/O
10.863	0.180	tNET	RR	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_reg_1_s0/CLK
10.828	-0.035	tSu		1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_reg_1_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	24
Arrival Clock Path Delay:	cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay:	cell: 10.066, 66.936%; route: 4.740, 31.521%; tC2Q: 0.232, 1.543%
Required Clock Path Delay:	cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:

Slack	-5.035
Data Arrival Time	15.862
Data Required Time	10.828
From	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig0.reg_trig0_addr_1_s0
To	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/hprot_reg_2_s0
Launch Clk	X_oschin[R]
Latch Clk	X_oschin[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				X_oschin
0.000	0.000	tCL	RR	1	X_oschin_ibuf/I
0.683	0.683	tINS	RR	6609	X_oschin_ibuf/O
0.863	0.180	tNET	RR	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig0.reg_trig0_addr_1_s0/CLK
1.095	0.232	tC2Q	RF	8	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig0.reg_trig0_addr_1_s0/Q
1.332	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4526_s1/I1
1.887	0.555	tINS	FF	4	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4526_s1/F
2.124	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4522_s3/I3
2.495	0.371	tINS	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4522_s3/F
2.732	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4528_s2/I2
3.185	0.453	tINS	FF	5	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4528_s2/F
3.422	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4530_s2/I3
3.793	0.371	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4530_s2/F
4.030	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4530_s3/I0
4.547	0.517	tINS	FF	3	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4530_s3/F
4.784	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4529_s1/I3
5.155	0.371	tINS	FF	4	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4529_s1/F
5.392	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4528_s1/I2
5.845	0.453	tINS	FF	3	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4528_s1/F
6.082	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4522_s1/I0
6.599	0.517	tINS	FF	9	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4522_s1/F
6.836	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4525_s1/I3
7.207	0.371	tINS	FF	4	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4525_s1/F
7.444	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4557_s2/I0
7.961	0.517	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4557_s2/F
8.198	0.237	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4589_s0/I1
8.768	0.570	tINS	FR	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4589_s0/COUT
8.768	0.000	tNET	RR	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4590_s0/CIN
8.803	0.035	tINS	RF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4590_s0/COUT
8.803	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4591_s0/CIN
8.838	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4591_s0/COUT
8.838	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4592_s0/CIN
8.873	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4592_s0/COUT
8.873	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4593_s0/CIN
8.908	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4593_s0/COUT
8.908	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4594_s0/CIN
8.944	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4594_s0/COUT
8.944	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4595_s0/CIN
8.979	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4595_s0/COUT
8.979	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4596_s0/CIN
9.014	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4596_s0/COUT
9.014	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4597_s0/CIN
9.049	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4597_s0/COUT
9.049	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4598_s0/CIN
9.084	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4598_s0/COUT
9.084	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4599_s0/CIN
9.120	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4599_s0/COUT
9.120	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4600_s0/CIN
9.155	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4600_s0/COUT
9.155	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4601_s0/CIN
9.190	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4601_s0/COUT
9.190	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4602_s0/CIN
9.225	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4602_s0/COUT
9.225	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4603_s0/CIN
9.260	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4603_s0/COUT
9.260	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4604_s0/CIN
9.296	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4604_s0/COUT
9.296	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4605_s0/CIN
9.331	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4605_s0/COUT
9.331	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4606_s0/CIN
9.366	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4606_s0/COUT
9.366	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4607_s0/CIN
9.401	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4607_s0/COUT
9.401	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4608_s0/CIN
9.436	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4608_s0/COUT
9.436	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4609_s0/CIN
9.472	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4609_s0/COUT
9.472	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4610_s0/CIN
9.507	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4610_s0/COUT
9.507	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4611_s0/CIN
9.542	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4611_s0/COUT
9.542	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4612_s0/CIN
9.577	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4612_s0/COUT
9.577	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4613_s0/CIN
9.612	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4613_s0/COUT
9.612	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4614_s0/CIN
9.648	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4614_s0/COUT
9.648	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4615_s0/CIN
9.683	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4615_s0/COUT
9.683	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4616_s0/CIN
9.718	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4616_s0/COUT
9.718	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4617_s0/CIN
9.753	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4617_s0/COUT
9.990	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s23/I0
10.507	0.517	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s23/F
10.744	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s14/I2
11.197	0.453	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s14/F
11.434	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s7/I3
11.805	0.371	tINS	FF	6	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s7/F
12.042	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n878_s7/I1
12.597	0.555	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n878_s7/F
12.834	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n878_s1/I2
13.287	0.453	tINS	FF	8	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n878_s1/F
13.524	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_dcu/biu_load_issued_set_s3/I0
14.041	0.517	tINS	FF	38	ae250_chip/uncore/vc_core_mem/vc_core/vc_dcu/biu_load_issued_set_s3/F
14.278	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/vc_biu_path/path0_sync_cacheability_0_s0/I1
14.833	0.555	tINS	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/vc_biu_path/path0_sync_cacheability_0_s0/F
15.070	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/hprot_out_2_s3/I1
15.625	0.555	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/hprot_out_2_s3/F
15.862	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/hprot_reg_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				X_oschin
10.000	0.000	tCL	RR	1	X_oschin_ibuf/I
10.682	0.683	tINS	RR	6609	X_oschin_ibuf/O
10.863	0.180	tNET	RR	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/hprot_reg_2_s0/CLK
10.828	-0.035	tSu		1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/hprot_reg_2_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	24
Arrival Clock Path Delay:	cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay:	cell: 10.028, 66.852%; route: 4.740, 31.601%; tC2Q: 0.232, 1.547%
Required Clock Path Delay:	cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:

Slack	-5.035
Data Arrival Time	15.862
Data Required Time	10.828
From	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig0.reg_trig0_addr_1_s0
To	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_reg_2_s0
Launch Clk	X_oschin[R]
Latch Clk	X_oschin[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				X_oschin
0.000	0.000	tCL	RR	1	X_oschin_ibuf/I
0.683	0.683	tINS	RR	6609	X_oschin_ibuf/O
0.863	0.180	tNET	RR	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig0.reg_trig0_addr_1_s0/CLK
1.095	0.232	tC2Q	RF	8	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig0.reg_trig0_addr_1_s0/Q
1.332	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4526_s1/I1
1.887	0.555	tINS	FF	4	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4526_s1/F
2.124	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4522_s3/I3
2.495	0.371	tINS	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4522_s3/F
2.732	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4528_s2/I2
3.185	0.453	tINS	FF	5	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4528_s2/F
3.422	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4530_s2/I3
3.793	0.371	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4530_s2/F
4.030	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4530_s3/I0
4.547	0.517	tINS	FF	3	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4530_s3/F
4.784	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4529_s1/I3
5.155	0.371	tINS	FF	4	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4529_s1/F
5.392	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4528_s1/I2
5.845	0.453	tINS	FF	3	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4528_s1/F
6.082	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4522_s1/I0
6.599	0.517	tINS	FF	9	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4522_s1/F
6.836	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4525_s1/I3
7.207	0.371	tINS	FF	4	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4525_s1/F
7.444	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4557_s2/I0
7.961	0.517	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4557_s2/F
8.198	0.237	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4589_s0/I1
8.768	0.570	tINS	FR	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4589_s0/COUT
8.768	0.000	tNET	RR	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4590_s0/CIN
8.803	0.035	tINS	RF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4590_s0/COUT
8.803	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4591_s0/CIN
8.838	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4591_s0/COUT
8.838	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4592_s0/CIN
8.873	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4592_s0/COUT
8.873	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4593_s0/CIN
8.908	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4593_s0/COUT
8.908	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4594_s0/CIN
8.944	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4594_s0/COUT
8.944	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4595_s0/CIN
8.979	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4595_s0/COUT
8.979	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4596_s0/CIN
9.014	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4596_s0/COUT
9.014	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4597_s0/CIN
9.049	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4597_s0/COUT
9.049	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4598_s0/CIN
9.084	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4598_s0/COUT
9.084	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4599_s0/CIN
9.120	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4599_s0/COUT
9.120	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4600_s0/CIN
9.155	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4600_s0/COUT
9.155	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4601_s0/CIN
9.190	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4601_s0/COUT
9.190	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4602_s0/CIN
9.225	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4602_s0/COUT
9.225	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4603_s0/CIN
9.260	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4603_s0/COUT
9.260	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4604_s0/CIN
9.296	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4604_s0/COUT
9.296	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4605_s0/CIN
9.331	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4605_s0/COUT
9.331	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4606_s0/CIN
9.366	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4606_s0/COUT
9.366	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4607_s0/CIN
9.401	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4607_s0/COUT
9.401	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4608_s0/CIN
9.436	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4608_s0/COUT
9.436	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4609_s0/CIN
9.472	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4609_s0/COUT
9.472	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4610_s0/CIN
9.507	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4610_s0/COUT
9.507	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4611_s0/CIN
9.542	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4611_s0/COUT
9.542	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4612_s0/CIN
9.577	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4612_s0/COUT
9.577	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4613_s0/CIN
9.612	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4613_s0/COUT
9.612	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4614_s0/CIN
9.648	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4614_s0/COUT
9.648	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4615_s0/CIN
9.683	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4615_s0/COUT
9.683	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4616_s0/CIN
9.718	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4616_s0/COUT
9.718	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4617_s0/CIN
9.753	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4617_s0/COUT
9.990	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s23/I0
10.507	0.517	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s23/F
10.744	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s14/I2
11.197	0.453	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s14/F
11.434	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s7/I3
11.805	0.371	tINS	FF	6	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s7/F
12.042	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n878_s7/I1
12.597	0.555	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n878_s7/F
12.834	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n878_s1/I2
13.287	0.453	tINS	FF	8	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n878_s1/F
13.524	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/vc_biu_path/path0_sync_addr_0_s1/I1
14.079	0.555	tINS	FF	8	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/vc_biu_path/path0_sync_addr_0_s1/F
14.316	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_2_0_2_s1/I1
14.871	0.555	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_2_0_2_s1/F
15.108	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_2_0_2_s0/I0
15.625	0.517	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_2_0_2_s0/F
15.862	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_reg_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				X_oschin
10.000	0.000	tCL	RR	1	X_oschin_ibuf/I
10.682	0.683	tINS	RR	6609	X_oschin_ibuf/O
10.863	0.180	tNET	RR	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_reg_2_s0/CLK
10.828	-0.035	tSu		1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_reg_2_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	24
Arrival Clock Path Delay:	cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay:	cell: 10.028, 66.852%; route: 4.740, 31.601%; tC2Q: 0.232, 1.547%
Required Clock Path Delay:	cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:

Slack	-4.997
Data Arrival Time	15.824
Data Required Time	10.828
From	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig0.reg_trig0_addr_1_s0
To	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_valid_s1
Launch Clk	X_oschin[R]
Latch Clk	X_oschin[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				X_oschin
0.000	0.000	tCL	RR	1	X_oschin_ibuf/I
0.683	0.683	tINS	RR	6609	X_oschin_ibuf/O
0.863	0.180	tNET	RR	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig0.reg_trig0_addr_1_s0/CLK
1.095	0.232	tC2Q	RF	8	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/gen_reg_trig0.reg_trig0_addr_1_s0/Q
1.332	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4526_s1/I1
1.887	0.555	tINS	FF	4	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4526_s1/F
2.124	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4522_s3/I3
2.495	0.371	tINS	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4522_s3/F
2.732	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4528_s2/I2
3.185	0.453	tINS	FF	5	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4528_s2/F
3.422	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4530_s2/I3
3.793	0.371	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4530_s2/F
4.030	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4530_s3/I0
4.547	0.517	tINS	FF	3	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4530_s3/F
4.784	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4529_s1/I3
5.155	0.371	tINS	FF	4	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4529_s1/F
5.392	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4528_s1/I2
5.845	0.453	tINS	FF	3	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4528_s1/F
6.082	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4522_s1/I0
6.599	0.517	tINS	FF	9	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4522_s1/F
6.836	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4525_s1/I3
7.207	0.371	tINS	FF	4	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4525_s1/F
7.444	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4557_s2/I0
7.961	0.517	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4557_s2/F
8.198	0.237	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4589_s0/I1
8.768	0.570	tINS	FR	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4589_s0/COUT
8.768	0.000	tNET	RR	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4590_s0/CIN
8.803	0.035	tINS	RF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4590_s0/COUT
8.803	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4591_s0/CIN
8.838	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4591_s0/COUT
8.838	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4592_s0/CIN
8.873	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4592_s0/COUT
8.873	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4593_s0/CIN
8.908	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4593_s0/COUT
8.908	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4594_s0/CIN
8.944	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4594_s0/COUT
8.944	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4595_s0/CIN
8.979	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4595_s0/COUT
8.979	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4596_s0/CIN
9.014	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4596_s0/COUT
9.014	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4597_s0/CIN
9.049	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4597_s0/COUT
9.049	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4598_s0/CIN
9.084	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4598_s0/COUT
9.084	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4599_s0/CIN
9.120	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4599_s0/COUT
9.120	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4600_s0/CIN
9.155	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4600_s0/COUT
9.155	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4601_s0/CIN
9.190	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4601_s0/COUT
9.190	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4602_s0/CIN
9.225	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4602_s0/COUT
9.225	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4603_s0/CIN
9.260	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4603_s0/COUT
9.260	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4604_s0/CIN
9.296	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4604_s0/COUT
9.296	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4605_s0/CIN
9.331	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4605_s0/COUT
9.331	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4606_s0/CIN
9.366	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4606_s0/COUT
9.366	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4607_s0/CIN
9.401	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4607_s0/COUT
9.401	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4608_s0/CIN
9.436	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4608_s0/COUT
9.436	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4609_s0/CIN
9.472	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4609_s0/COUT
9.472	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4610_s0/CIN
9.507	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4610_s0/COUT
9.507	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4611_s0/CIN
9.542	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4611_s0/COUT
9.542	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4612_s0/CIN
9.577	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4612_s0/COUT
9.577	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4613_s0/CIN
9.612	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4613_s0/COUT
9.612	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4614_s0/CIN
9.648	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4614_s0/COUT
9.648	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4615_s0/CIN
9.683	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4615_s0/COUT
9.683	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4616_s0/CIN
9.718	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4616_s0/COUT
9.718	0.000	tNET	FF	2	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4617_s0/CIN
9.753	0.035	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_trigm/n4617_s0/COUT
9.990	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s23/I0
10.507	0.517	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s23/F
10.744	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s14/I2
11.197	0.453	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s14/F
11.434	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s7/I3
11.805	0.371	tINS	FF	6	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_tval_sel_addr_nx_s7/F
12.042	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n878_s7/I1
12.597	0.555	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n878_s7/F
12.834	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n878_s1/I2
13.287	0.453	tINS	FF	8	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n878_s1/F
13.524	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_trap_ret_nx_s1/I0
14.041	0.517	tINS	FF	7	ae250_chip/uncore/vc_core_mem/vc_core/vc_ipipe/wb_reg_trap_ret_nx_s1/F
14.278	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/ahb_cmd_en_s1/I0
14.795	0.517	tINS	FF	5	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/ahb_cmd_en_s1/F
15.032	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n914_s0/I1
15.587	0.555	tINS	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/n914_s0/F
15.824	0.237	tNET	FF	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_valid_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				X_oschin
10.000	0.000	tCL	RR	1	X_oschin_ibuf/I
10.682	0.683	tINS	RR	6609	X_oschin_ibuf/O
10.863	0.180	tNET	RR	1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_valid_s1/CLK
10.828	-0.035	tSu		1	ae250_chip/uncore/vc_core_mem/vc_core/vc_biu/gen_ahb_wrapper.vc_biu_ahb_wrapper0/haddr_valid_s1

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	24
Arrival Clock Path Delay:	cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay:	cell: 9.990, 66.768%; route: 4.740, 31.681%; tC2Q: 0.232, 1.551%
Required Clock Path Delay:	cell: 0.683, 79.130%; route: 0.180, 20.870%