Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picorv32.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\advspi.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\ahb_bus.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_dtcm.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_itcm.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_bus.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_brancher.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbgpio.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbi2c.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbspi.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbuart.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\simpleuart.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\dm.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.01 (64-bit) |
| Part Number | GW5A-LV25UG324C2/I1 |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Tue Feb 10 14:17:35 2026 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Gowin_PicoRV32_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 136.238MB Running netlist conversion: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.162s, Peak memory usage = 136.238MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 136.238MB Optimizing Phase 1: CPU time = 0h 0m 0.531s, Elapsed time = 0h 0m 0.534s, Peak memory usage = 136.238MB Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 136.238MB Running inference: Inferring Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 136.238MB Inferring Phase 1: CPU time = 0h 0m 0.578s, Elapsed time = 0h 0m 0.575s, Peak memory usage = 136.238MB Inferring Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.087s, Peak memory usage = 136.238MB Inferring Phase 3: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 136.238MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 136.238MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.578s, Elapsed time = 0h 0m 0.585s, Peak memory usage = 136.238MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.609s, Elapsed time = 0h 0m 0.62s, Peak memory usage = 136.238MB Tech-Mapping Phase 3: CPU time = 0h 0m 26s, Elapsed time = 0h 0m 26s, Peak memory usage = 151.500MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.843s, Elapsed time = 0h 0m 0.979s, Peak memory usage = 151.500MB Generate output files: CPU time = 0h 0m 0.921s, Elapsed time = 0h 0m 1s, Peak memory usage = 196.043MB |
| Total Time and Memory Usage | CPU time = 0h 0m 35s, Elapsed time = 0h 0m 35s, Peak memory usage = 196.043MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 241 |
| I/O Buf | 239 |
| IBUF | 84 |
| OBUF | 147 |
| TBUF | 1 |
| IOBUF | 7 |
| Register | 4537 |
| DFFSE | 96 |
| DFFRE | 3069 |
| DFFPE | 17 |
| DFFCE | 1355 |
| LUT | 6650 |
| LUT2 | 410 |
| LUT3 | 2235 |
| LUT4 | 4005 |
| ALU | 630 |
| ALU | 630 |
| INV | 27 |
| INV | 27 |
| DSP | |
| MULT27X36 | 2 |
| BSRAM | 32 |
| SDPB | 32 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 7307(6677 LUT, 630 ALU) / 23040 | 32% |
| Register | 4537 / 23685 | 20% |
| --Register as Latch | 0 / 23685 | 0% |
| --Register as FF | 4537 / 23685 | 20% |
| BSRAM | 32 / 56 | 58% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk_in | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_in_ibuf/I | ||
| 2 | jtag_TCK | Base | 10.000 | 100.000 | 0.000 | 5.000 | jtag_TCK_ibuf/I | ||
| 3 | u_dualportspi/u_atcspi/u_spi_spiif/n316_3 | Base | 10.000 | 100.000 | 0.000 | 5.000 | u_dualportspi/u_atcspi/u_spi_spiif/n316_s0/F |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk_in | 100.000(MHz) | 70.592(MHz) | 11 | TOP |
| 2 | jtag_TCK | 100.000(MHz) | 126.008(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -2.931 |
| Data Arrival Time | 13.180 |
| Data Required Time | 10.249 |
| From | core/mem_addr_26_s0 |
| To | core/mem_rdata_q_20_s0 |
| Launch Clk | clk_in[R] |
| Latch Clk | clk_in[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_in | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 4417 | clk_in_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | core/mem_addr_26_s0/CLK |
| 0.606 | 0.306 | tC2Q | RR | 3 | core/mem_addr_26_s0/Q |
| 0.906 | 0.300 | tNET | RR | 1 | itcm_valid_s2/I0 |
| 1.327 | 0.421 | tINS | RR | 5 | itcm_valid_s2/F |
| 1.627 | 0.300 | tNET | RR | 1 | itcm_valid_s3/I3 |
| 1.837 | 0.210 | tINS | RR | 4 | itcm_valid_s3/F |
| 2.137 | 0.300 | tNET | RR | 1 | core/n1614_s3/I0 |
| 2.558 | 0.421 | tINS | RR | 5 | core/n1614_s3/F |
| 2.858 | 0.300 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I1 |
| 3.271 | 0.413 | tINS | RR | 40 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
| 3.571 | 0.300 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
| 3.781 | 0.210 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
| 4.081 | 0.300 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
| 4.450 | 0.369 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
| 4.750 | 0.300 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_20_s4/I2 |
| 5.119 | 0.369 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_20_s4/F |
| 5.419 | 0.300 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_20_s1/I0 |
| 5.528 | 0.109 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_20_s1/O |
| 5.828 | 0.300 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_20_s/I1 |
| 5.897 | 0.069 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_20_s/O |
| 6.197 | 0.300 | tNET | RR | 1 | mem_rdata_20_s3/I0 |
| 6.618 | 0.421 | tINS | RR | 1 | mem_rdata_20_s3/F |
| 6.918 | 0.300 | tNET | RR | 1 | mem_rdata_20_s1/I0 |
| 7.339 | 0.421 | tINS | RR | 1 | mem_rdata_20_s1/F |
| 7.639 | 0.300 | tNET | RR | 1 | mem_rdata_20_s8/I0 |
| 8.060 | 0.421 | tINS | RR | 4 | mem_rdata_20_s8/F |
| 8.360 | 0.300 | tNET | RR | 1 | core/mem_rdata_latched_20_s0/I1 |
| 8.773 | 0.413 | tINS | RR | 6 | core/mem_rdata_latched_20_s0/F |
| 9.073 | 0.300 | tNET | RR | 1 | core/mem_rdata_latched_4_s1/I3 |
| 9.283 | 0.210 | tINS | RR | 17 | core/mem_rdata_latched_4_s1/F |
| 9.583 | 0.300 | tNET | RR | 1 | core/n5248_s4/I0 |
| 10.004 | 0.421 | tINS | RR | 3 | core/n5248_s4/F |
| 10.304 | 0.300 | tNET | RR | 1 | core/n2082_s9/I1 |
| 10.717 | 0.413 | tINS | RR | 1 | core/n2082_s9/F |
| 11.017 | 0.300 | tNET | RR | 1 | core/n2082_s5/I0 |
| 11.438 | 0.421 | tINS | RR | 3 | core/n2082_s5/F |
| 11.738 | 0.300 | tNET | RR | 1 | core/n2082_s1/I0 |
| 12.159 | 0.421 | tINS | RR | 3 | core/n2082_s1/F |
| 12.459 | 0.300 | tNET | RR | 1 | core/n2086_s0/I0 |
| 12.880 | 0.421 | tINS | RR | 1 | core/n2086_s0/F |
| 13.180 | 0.300 | tNET | RR | 1 | core/mem_rdata_q_20_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_in | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 4417 | clk_in_ibuf/O |
| 10.300 | 0.300 | tNET | RR | 1 | core/mem_rdata_q_20_s0/CLK |
| 10.249 | -0.051 | tSu | 1 | core/mem_rdata_q_20_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 18 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 6.574, 51.040%; route: 6.000, 46.584%; tC2Q: 0.306, 2.376% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 2
Path Summary:| Slack | -2.931 |
| Data Arrival Time | 13.180 |
| Data Required Time | 10.249 |
| From | core/mem_addr_26_s0 |
| To | core/mem_rdata_q_21_s0 |
| Launch Clk | clk_in[R] |
| Latch Clk | clk_in[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_in | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 4417 | clk_in_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | core/mem_addr_26_s0/CLK |
| 0.606 | 0.306 | tC2Q | RR | 3 | core/mem_addr_26_s0/Q |
| 0.906 | 0.300 | tNET | RR | 1 | itcm_valid_s2/I0 |
| 1.327 | 0.421 | tINS | RR | 5 | itcm_valid_s2/F |
| 1.627 | 0.300 | tNET | RR | 1 | itcm_valid_s3/I3 |
| 1.837 | 0.210 | tINS | RR | 4 | itcm_valid_s3/F |
| 2.137 | 0.300 | tNET | RR | 1 | core/n1614_s3/I0 |
| 2.558 | 0.421 | tINS | RR | 5 | core/n1614_s3/F |
| 2.858 | 0.300 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I1 |
| 3.271 | 0.413 | tINS | RR | 40 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
| 3.571 | 0.300 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
| 3.781 | 0.210 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
| 4.081 | 0.300 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
| 4.450 | 0.369 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
| 4.750 | 0.300 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_20_s4/I2 |
| 5.119 | 0.369 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_20_s4/F |
| 5.419 | 0.300 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_20_s1/I0 |
| 5.528 | 0.109 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_20_s1/O |
| 5.828 | 0.300 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_20_s/I1 |
| 5.897 | 0.069 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_20_s/O |
| 6.197 | 0.300 | tNET | RR | 1 | mem_rdata_20_s3/I0 |
| 6.618 | 0.421 | tINS | RR | 1 | mem_rdata_20_s3/F |
| 6.918 | 0.300 | tNET | RR | 1 | mem_rdata_20_s1/I0 |
| 7.339 | 0.421 | tINS | RR | 1 | mem_rdata_20_s1/F |
| 7.639 | 0.300 | tNET | RR | 1 | mem_rdata_20_s8/I0 |
| 8.060 | 0.421 | tINS | RR | 4 | mem_rdata_20_s8/F |
| 8.360 | 0.300 | tNET | RR | 1 | core/mem_rdata_latched_20_s0/I1 |
| 8.773 | 0.413 | tINS | RR | 6 | core/mem_rdata_latched_20_s0/F |
| 9.073 | 0.300 | tNET | RR | 1 | core/mem_rdata_latched_4_s1/I3 |
| 9.283 | 0.210 | tINS | RR | 17 | core/mem_rdata_latched_4_s1/F |
| 9.583 | 0.300 | tNET | RR | 1 | core/n5248_s4/I0 |
| 10.004 | 0.421 | tINS | RR | 3 | core/n5248_s4/F |
| 10.304 | 0.300 | tNET | RR | 1 | core/n2082_s9/I1 |
| 10.717 | 0.413 | tINS | RR | 1 | core/n2082_s9/F |
| 11.017 | 0.300 | tNET | RR | 1 | core/n2082_s5/I0 |
| 11.438 | 0.421 | tINS | RR | 3 | core/n2082_s5/F |
| 11.738 | 0.300 | tNET | RR | 1 | core/n2082_s1/I0 |
| 12.159 | 0.421 | tINS | RR | 3 | core/n2082_s1/F |
| 12.459 | 0.300 | tNET | RR | 1 | core/n2085_s0/I0 |
| 12.880 | 0.421 | tINS | RR | 1 | core/n2085_s0/F |
| 13.180 | 0.300 | tNET | RR | 1 | core/mem_rdata_q_21_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_in | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 4417 | clk_in_ibuf/O |
| 10.300 | 0.300 | tNET | RR | 1 | core/mem_rdata_q_21_s0/CLK |
| 10.249 | -0.051 | tSu | 1 | core/mem_rdata_q_21_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 18 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 6.574, 51.040%; route: 6.000, 46.584%; tC2Q: 0.306, 2.376% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 3
Path Summary:| Slack | -2.931 |
| Data Arrival Time | 13.180 |
| Data Required Time | 10.249 |
| From | core/mem_addr_26_s0 |
| To | core/mem_rdata_q_24_s0 |
| Launch Clk | clk_in[R] |
| Latch Clk | clk_in[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_in | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 4417 | clk_in_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | core/mem_addr_26_s0/CLK |
| 0.606 | 0.306 | tC2Q | RR | 3 | core/mem_addr_26_s0/Q |
| 0.906 | 0.300 | tNET | RR | 1 | itcm_valid_s2/I0 |
| 1.327 | 0.421 | tINS | RR | 5 | itcm_valid_s2/F |
| 1.627 | 0.300 | tNET | RR | 1 | itcm_valid_s3/I3 |
| 1.837 | 0.210 | tINS | RR | 4 | itcm_valid_s3/F |
| 2.137 | 0.300 | tNET | RR | 1 | core/n1614_s3/I0 |
| 2.558 | 0.421 | tINS | RR | 5 | core/n1614_s3/F |
| 2.858 | 0.300 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I1 |
| 3.271 | 0.413 | tINS | RR | 40 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
| 3.571 | 0.300 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
| 3.781 | 0.210 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
| 4.081 | 0.300 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
| 4.450 | 0.369 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
| 4.750 | 0.300 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_20_s4/I2 |
| 5.119 | 0.369 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_20_s4/F |
| 5.419 | 0.300 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_20_s1/I0 |
| 5.528 | 0.109 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_20_s1/O |
| 5.828 | 0.300 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_20_s/I1 |
| 5.897 | 0.069 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_20_s/O |
| 6.197 | 0.300 | tNET | RR | 1 | mem_rdata_20_s3/I0 |
| 6.618 | 0.421 | tINS | RR | 1 | mem_rdata_20_s3/F |
| 6.918 | 0.300 | tNET | RR | 1 | mem_rdata_20_s1/I0 |
| 7.339 | 0.421 | tINS | RR | 1 | mem_rdata_20_s1/F |
| 7.639 | 0.300 | tNET | RR | 1 | mem_rdata_20_s8/I0 |
| 8.060 | 0.421 | tINS | RR | 4 | mem_rdata_20_s8/F |
| 8.360 | 0.300 | tNET | RR | 1 | core/mem_rdata_latched_20_s0/I1 |
| 8.773 | 0.413 | tINS | RR | 6 | core/mem_rdata_latched_20_s0/F |
| 9.073 | 0.300 | tNET | RR | 1 | core/mem_rdata_latched_4_s1/I3 |
| 9.283 | 0.210 | tINS | RR | 17 | core/mem_rdata_latched_4_s1/F |
| 9.583 | 0.300 | tNET | RR | 1 | core/n5248_s4/I0 |
| 10.004 | 0.421 | tINS | RR | 3 | core/n5248_s4/F |
| 10.304 | 0.300 | tNET | RR | 1 | core/n2082_s9/I1 |
| 10.717 | 0.413 | tINS | RR | 1 | core/n2082_s9/F |
| 11.017 | 0.300 | tNET | RR | 1 | core/n2082_s5/I0 |
| 11.438 | 0.421 | tINS | RR | 3 | core/n2082_s5/F |
| 11.738 | 0.300 | tNET | RR | 1 | core/n2082_s1/I0 |
| 12.159 | 0.421 | tINS | RR | 3 | core/n2082_s1/F |
| 12.459 | 0.300 | tNET | RR | 1 | core/n2082_s0/I0 |
| 12.880 | 0.421 | tINS | RR | 1 | core/n2082_s0/F |
| 13.180 | 0.300 | tNET | RR | 1 | core/mem_rdata_q_24_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_in | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 4417 | clk_in_ibuf/O |
| 10.300 | 0.300 | tNET | RR | 1 | core/mem_rdata_q_24_s0/CLK |
| 10.249 | -0.051 | tSu | 1 | core/mem_rdata_q_24_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 18 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 6.574, 51.040%; route: 6.000, 46.584%; tC2Q: 0.306, 2.376% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 4
Path Summary:| Slack | -2.895 |
| Data Arrival Time | 13.144 |
| Data Required Time | 10.249 |
| From | core/mem_addr_26_s0 |
| To | core/decoded_rs1_3_s0 |
| Launch Clk | clk_in[R] |
| Latch Clk | clk_in[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_in | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 4417 | clk_in_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | core/mem_addr_26_s0/CLK |
| 0.606 | 0.306 | tC2Q | RR | 3 | core/mem_addr_26_s0/Q |
| 0.906 | 0.300 | tNET | RR | 1 | itcm_valid_s2/I0 |
| 1.327 | 0.421 | tINS | RR | 5 | itcm_valid_s2/F |
| 1.627 | 0.300 | tNET | RR | 1 | itcm_valid_s3/I3 |
| 1.837 | 0.210 | tINS | RR | 4 | itcm_valid_s3/F |
| 2.137 | 0.300 | tNET | RR | 1 | core/n1614_s3/I0 |
| 2.558 | 0.421 | tINS | RR | 5 | core/n1614_s3/F |
| 2.858 | 0.300 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I1 |
| 3.271 | 0.413 | tINS | RR | 40 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
| 3.571 | 0.300 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
| 3.781 | 0.210 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
| 4.081 | 0.300 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
| 4.450 | 0.369 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
| 4.750 | 0.300 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_22_s4/I2 |
| 5.119 | 0.369 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_22_s4/F |
| 5.419 | 0.300 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_22_s1/I0 |
| 5.528 | 0.109 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_22_s1/O |
| 5.828 | 0.300 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_22_s/I1 |
| 5.897 | 0.069 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_22_s/O |
| 6.197 | 0.300 | tNET | RR | 1 | mem_rdata_22_s3/I2 |
| 6.566 | 0.369 | tINS | RR | 1 | mem_rdata_22_s3/F |
| 6.866 | 0.300 | tNET | RR | 1 | mem_rdata_22_s1/I0 |
| 7.287 | 0.421 | tINS | RR | 1 | mem_rdata_22_s1/F |
| 7.587 | 0.300 | tNET | RR | 1 | mem_rdata_22_s0/I0 |
| 8.008 | 0.421 | tINS | RR | 5 | mem_rdata_22_s0/F |
| 8.308 | 0.300 | tNET | RR | 1 | core/mem_rdata_latched_6_s13/I3 |
| 8.518 | 0.210 | tINS | RR | 1 | core/mem_rdata_latched_6_s13/F |
| 8.818 | 0.300 | tNET | RR | 1 | core/mem_rdata_latched_6_s1/I0 |
| 9.239 | 0.421 | tINS | RR | 18 | core/mem_rdata_latched_6_s1/F |
| 9.539 | 0.300 | tNET | RR | 1 | core/n5189_s5/I0 |
| 9.960 | 0.421 | tINS | RR | 6 | core/n5189_s5/F |
| 10.260 | 0.300 | tNET | RR | 1 | core/n5638_s5/I0 |
| 10.681 | 0.421 | tINS | RR | 11 | core/n5638_s5/F |
| 10.981 | 0.300 | tNET | RR | 1 | core/n5584_s6/I0 |
| 11.402 | 0.421 | tINS | RR | 4 | core/n5584_s6/F |
| 11.702 | 0.300 | tNET | RR | 1 | core/n5585_s1/I0 |
| 12.123 | 0.421 | tINS | RR | 1 | core/n5585_s1/F |
| 12.423 | 0.300 | tNET | RR | 1 | core/n5585_s0/I0 |
| 12.844 | 0.421 | tINS | RR | 1 | core/n5585_s0/F |
| 13.144 | 0.300 | tNET | RR | 1 | core/decoded_rs1_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_in | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 4417 | clk_in_ibuf/O |
| 10.300 | 0.300 | tNET | RR | 1 | core/decoded_rs1_3_s0/CLK |
| 10.249 | -0.051 | tSu | 1 | core/decoded_rs1_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 18 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 6.538, 50.904%; route: 6.000, 46.714%; tC2Q: 0.306, 2.382% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 5
Path Summary:| Slack | -2.887 |
| Data Arrival Time | 13.136 |
| Data Required Time | 10.249 |
| From | core/mem_addr_26_s0 |
| To | core/decoded_rs1_4_s0 |
| Launch Clk | clk_in[R] |
| Latch Clk | clk_in[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_in | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 4417 | clk_in_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | core/mem_addr_26_s0/CLK |
| 0.606 | 0.306 | tC2Q | RR | 3 | core/mem_addr_26_s0/Q |
| 0.906 | 0.300 | tNET | RR | 1 | itcm_valid_s2/I0 |
| 1.327 | 0.421 | tINS | RR | 5 | itcm_valid_s2/F |
| 1.627 | 0.300 | tNET | RR | 1 | itcm_valid_s3/I3 |
| 1.837 | 0.210 | tINS | RR | 4 | itcm_valid_s3/F |
| 2.137 | 0.300 | tNET | RR | 1 | core/n1614_s3/I0 |
| 2.558 | 0.421 | tINS | RR | 5 | core/n1614_s3/F |
| 2.858 | 0.300 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I1 |
| 3.271 | 0.413 | tINS | RR | 40 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
| 3.571 | 0.300 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
| 3.781 | 0.210 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
| 4.081 | 0.300 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
| 4.450 | 0.369 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
| 4.750 | 0.300 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_22_s4/I2 |
| 5.119 | 0.369 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_22_s4/F |
| 5.419 | 0.300 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_22_s1/I0 |
| 5.528 | 0.109 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_22_s1/O |
| 5.828 | 0.300 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_22_s/I1 |
| 5.897 | 0.069 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_22_s/O |
| 6.197 | 0.300 | tNET | RR | 1 | mem_rdata_22_s3/I2 |
| 6.566 | 0.369 | tINS | RR | 1 | mem_rdata_22_s3/F |
| 6.866 | 0.300 | tNET | RR | 1 | mem_rdata_22_s1/I0 |
| 7.287 | 0.421 | tINS | RR | 1 | mem_rdata_22_s1/F |
| 7.587 | 0.300 | tNET | RR | 1 | mem_rdata_22_s0/I0 |
| 8.008 | 0.421 | tINS | RR | 5 | mem_rdata_22_s0/F |
| 8.308 | 0.300 | tNET | RR | 1 | core/mem_rdata_latched_6_s13/I3 |
| 8.518 | 0.210 | tINS | RR | 1 | core/mem_rdata_latched_6_s13/F |
| 8.818 | 0.300 | tNET | RR | 1 | core/mem_rdata_latched_6_s1/I0 |
| 9.239 | 0.421 | tINS | RR | 18 | core/mem_rdata_latched_6_s1/F |
| 9.539 | 0.300 | tNET | RR | 1 | core/n5189_s5/I0 |
| 9.960 | 0.421 | tINS | RR | 6 | core/n5189_s5/F |
| 10.260 | 0.300 | tNET | RR | 1 | core/n5638_s5/I0 |
| 10.681 | 0.421 | tINS | RR | 11 | core/n5638_s5/F |
| 10.981 | 0.300 | tNET | RR | 1 | core/n5582_s9/I0 |
| 11.402 | 0.421 | tINS | RR | 3 | core/n5582_s9/F |
| 11.702 | 0.300 | tNET | RR | 1 | core/n5584_s2/I0 |
| 12.123 | 0.421 | tINS | RR | 2 | core/n5584_s2/F |
| 12.423 | 0.300 | tNET | RR | 1 | core/n5584_s0/I1 |
| 12.836 | 0.413 | tINS | RR | 1 | core/n5584_s0/F |
| 13.136 | 0.300 | tNET | RR | 1 | core/decoded_rs1_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_in | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 4417 | clk_in_ibuf/O |
| 10.300 | 0.300 | tNET | RR | 1 | core/decoded_rs1_4_s0/CLK |
| 10.249 | -0.051 | tSu | 1 | core/decoded_rs1_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 18 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 6.530, 50.872%; route: 6.000, 46.744%; tC2Q: 0.306, 2.384% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |