Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picorv32.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\advspi.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\ahb_bus.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_dtcm.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_itcm.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_bus.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_brancher.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbgpio.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbi2c.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbspi.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbuart.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\simpleuart.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\dm.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.01 (64-bit) |
| Part Number | GW5AST-LV138FPG676AC1/I0 |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Tue Feb 10 11:36:30 2026 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Gowin_PicoRV32_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 135.219MB Running netlist conversion: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.144s, Peak memory usage = 135.219MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 135.219MB Optimizing Phase 1: CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.415s, Peak memory usage = 135.219MB Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 135.219MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.953s, Elapsed time = 0h 0m 0.972s, Peak memory usage = 135.219MB Inferring Phase 1: CPU time = 0h 0m 0.578s, Elapsed time = 0h 0m 0.577s, Peak memory usage = 135.219MB Inferring Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.088s, Peak memory usage = 135.219MB Inferring Phase 3: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 135.219MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 135.219MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.544s, Peak memory usage = 135.219MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.578s, Elapsed time = 0h 0m 0.569s, Peak memory usage = 135.219MB Tech-Mapping Phase 3: CPU time = 0h 0m 26s, Elapsed time = 0h 0m 26s, Peak memory usage = 148.223MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.75s, Elapsed time = 0h 0m 0.912s, Peak memory usage = 148.223MB Generate output files: CPU time = 0h 0m 0.984s, Elapsed time = 0h 0m 1s, Peak memory usage = 196.176MB |
| Total Time and Memory Usage | CPU time = 0h 0m 35s, Elapsed time = 0h 0m 35s, Peak memory usage = 196.176MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 241 |
| I/O Buf | 239 |
| IBUF | 84 |
| OBUF | 147 |
| TBUF | 1 |
| IOBUF | 7 |
| Register | 4537 |
| DFFSE | 98 |
| DFFRE | 3067 |
| DFFPE | 17 |
| DFFCE | 1355 |
| LUT | 6608 |
| LUT2 | 446 |
| LUT3 | 2232 |
| LUT4 | 3930 |
| ALU | 630 |
| ALU | 630 |
| INV | 28 |
| INV | 28 |
| DSP | |
| MULT27X36 | 2 |
| BSRAM | 32 |
| SDPB | 32 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 7266(6636 LUT, 630 ALU) / 138240 | 6% |
| Register | 4537 / 139140 | 4% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 4537 / 139140 | 4% |
| BSRAM | 32 / 340 | 10% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk_in | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_in_ibuf/I | ||
| 2 | jtag_TCK | Base | 10.000 | 100.000 | 0.000 | 5.000 | jtag_TCK_ibuf/I | ||
| 3 | u_dualportspi/u_atcspi/u_spi_spiif/n316_3 | Base | 10.000 | 100.000 | 0.000 | 5.000 | u_dualportspi/u_atcspi/u_spi_spiif/n316_s0/F |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk_in | 100.000(MHz) | 52.924(MHz) | 11 | TOP |
| 2 | jtag_TCK | 100.000(MHz) | 104.932(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -8.151 |
| Data Arrival Time | 18.500 |
| Data Required Time | 10.349 |
| From | core/mem_addr_28_s0 |
| To | core/mem_rdata_q_28_s0 |
| Launch Clk | clk_in[R] |
| Latch Clk | clk_in[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_in | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 4417 | clk_in_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | core/mem_addr_28_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 4 | core/mem_addr_28_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | itcm_valid_s2/I0 |
| 1.786 | 0.579 | tINS | RR | 6 | itcm_valid_s2/F |
| 2.199 | 0.413 | tNET | RR | 1 | itcm_valid_s1/I1 |
| 2.766 | 0.567 | tINS | RR | 6 | itcm_valid_s1/F |
| 3.179 | 0.413 | tNET | RR | 1 | core/n1614_s1/I2 |
| 3.686 | 0.507 | tINS | RR | 3 | core/n1614_s1/F |
| 4.099 | 0.413 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I1 |
| 4.666 | 0.567 | tINS | RR | 40 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
| 5.079 | 0.413 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
| 5.368 | 0.289 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
| 5.780 | 0.413 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
| 6.288 | 0.507 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
| 6.700 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s4/I2 |
| 7.208 | 0.507 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s4/F |
| 7.620 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s1/I0 |
| 7.770 | 0.150 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s1/O |
| 8.183 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s/I1 |
| 8.269 | 0.086 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_7_s/O |
| 8.681 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_23_s6/I0 |
| 9.260 | 0.579 | tINS | RR | 1 | core/mem_rdata_latched_23_s6/F |
| 9.673 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_23_s3/I0 |
| 10.251 | 0.579 | tINS | RR | 1 | core/mem_rdata_latched_23_s3/F |
| 10.664 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_23_s1/I0 |
| 11.243 | 0.579 | tINS | RR | 4 | core/mem_rdata_latched_23_s1/F |
| 11.655 | 0.413 | tNET | RR | 1 | core/n2099_s7/I0 |
| 12.234 | 0.579 | tINS | RR | 1 | core/n2099_s7/F |
| 12.646 | 0.413 | tNET | RR | 1 | core/n2099_s3/I2 |
| 13.154 | 0.507 | tINS | RR | 15 | core/n2099_s3/F |
| 13.566 | 0.413 | tNET | RR | 1 | core/n2092_s9/I1 |
| 14.134 | 0.567 | tINS | RR | 3 | core/n2092_s9/F |
| 14.546 | 0.413 | tNET | RR | 1 | core/n2092_s13/I0 |
| 15.125 | 0.579 | tINS | RR | 10 | core/n2092_s13/F |
| 15.538 | 0.413 | tNET | RR | 1 | core/n2078_s5/I1 |
| 16.105 | 0.567 | tINS | RR | 2 | core/n2078_s5/F |
| 16.518 | 0.413 | tNET | RR | 1 | core/n2078_s1/I0 |
| 17.096 | 0.579 | tINS | RR | 1 | core/n2078_s1/F |
| 17.509 | 0.413 | tNET | RR | 1 | core/n2078_s0/I0 |
| 18.088 | 0.579 | tINS | RR | 1 | core/n2078_s0/F |
| 18.500 | 0.413 | tNET | RR | 1 | core/mem_rdata_q_28_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_in | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 4417 | clk_in_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | core/mem_rdata_q_28_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | core/mem_rdata_q_28_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 18 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 9.455, 52.273%; route: 8.250, 45.612%; tC2Q: 0.382, 2.115% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:| Slack | -8.140 |
| Data Arrival Time | 18.489 |
| Data Required Time | 10.349 |
| From | core/mem_addr_28_s0 |
| To | core/mem_rdata_q_20_s0 |
| Launch Clk | clk_in[R] |
| Latch Clk | clk_in[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_in | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 4417 | clk_in_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | core/mem_addr_28_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 4 | core/mem_addr_28_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | itcm_valid_s2/I0 |
| 1.786 | 0.579 | tINS | RR | 6 | itcm_valid_s2/F |
| 2.199 | 0.413 | tNET | RR | 1 | itcm_valid_s1/I1 |
| 2.766 | 0.567 | tINS | RR | 6 | itcm_valid_s1/F |
| 3.179 | 0.413 | tNET | RR | 1 | core/n1614_s1/I2 |
| 3.686 | 0.507 | tINS | RR | 3 | core/n1614_s1/F |
| 4.099 | 0.413 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I1 |
| 4.666 | 0.567 | tINS | RR | 40 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
| 5.079 | 0.413 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
| 5.368 | 0.289 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
| 5.780 | 0.413 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
| 6.288 | 0.507 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
| 6.700 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s4/I2 |
| 7.208 | 0.507 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s4/F |
| 7.620 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s1/I0 |
| 7.770 | 0.150 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s1/O |
| 8.183 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s/I1 |
| 8.269 | 0.086 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_7_s/O |
| 8.681 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_23_s6/I0 |
| 9.260 | 0.579 | tINS | RR | 1 | core/mem_rdata_latched_23_s6/F |
| 9.673 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_23_s3/I0 |
| 10.251 | 0.579 | tINS | RR | 1 | core/mem_rdata_latched_23_s3/F |
| 10.664 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_23_s1/I0 |
| 11.243 | 0.579 | tINS | RR | 4 | core/mem_rdata_latched_23_s1/F |
| 11.655 | 0.413 | tNET | RR | 1 | core/n2099_s7/I0 |
| 12.234 | 0.579 | tINS | RR | 1 | core/n2099_s7/F |
| 12.646 | 0.413 | tNET | RR | 1 | core/n2099_s3/I2 |
| 13.154 | 0.507 | tINS | RR | 15 | core/n2099_s3/F |
| 13.566 | 0.413 | tNET | RR | 1 | core/n2092_s9/I1 |
| 14.134 | 0.567 | tINS | RR | 3 | core/n2092_s9/F |
| 14.546 | 0.413 | tNET | RR | 1 | core/n2092_s13/I0 |
| 15.125 | 0.579 | tINS | RR | 10 | core/n2092_s13/F |
| 15.538 | 0.413 | tNET | RR | 1 | core/n2086_s3/I0 |
| 16.116 | 0.579 | tINS | RR | 1 | core/n2086_s3/F |
| 16.529 | 0.413 | tNET | RR | 1 | core/n2086_s1/I1 |
| 17.096 | 0.567 | tINS | RR | 1 | core/n2086_s1/F |
| 17.509 | 0.413 | tNET | RR | 1 | core/n2086_s0/I1 |
| 18.076 | 0.567 | tINS | RR | 1 | core/n2086_s0/F |
| 18.489 | 0.413 | tNET | RR | 1 | core/mem_rdata_q_20_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_in | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 4417 | clk_in_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | core/mem_rdata_q_20_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | core/mem_rdata_q_20_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 18 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 9.444, 52.244%; route: 8.250, 45.640%; tC2Q: 0.382, 2.116% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:| Slack | -8.140 |
| Data Arrival Time | 18.489 |
| Data Required Time | 10.349 |
| From | core/mem_addr_28_s0 |
| To | core/mem_rdata_q_21_s0 |
| Launch Clk | clk_in[R] |
| Latch Clk | clk_in[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_in | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 4417 | clk_in_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | core/mem_addr_28_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 4 | core/mem_addr_28_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | itcm_valid_s2/I0 |
| 1.786 | 0.579 | tINS | RR | 6 | itcm_valid_s2/F |
| 2.199 | 0.413 | tNET | RR | 1 | itcm_valid_s1/I1 |
| 2.766 | 0.567 | tINS | RR | 6 | itcm_valid_s1/F |
| 3.179 | 0.413 | tNET | RR | 1 | core/n1614_s1/I2 |
| 3.686 | 0.507 | tINS | RR | 3 | core/n1614_s1/F |
| 4.099 | 0.413 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I1 |
| 4.666 | 0.567 | tINS | RR | 40 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
| 5.079 | 0.413 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
| 5.368 | 0.289 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
| 5.780 | 0.413 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
| 6.288 | 0.507 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
| 6.700 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s4/I2 |
| 7.208 | 0.507 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s4/F |
| 7.620 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s1/I0 |
| 7.770 | 0.150 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s1/O |
| 8.183 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s/I1 |
| 8.269 | 0.086 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_7_s/O |
| 8.681 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_23_s6/I0 |
| 9.260 | 0.579 | tINS | RR | 1 | core/mem_rdata_latched_23_s6/F |
| 9.673 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_23_s3/I0 |
| 10.251 | 0.579 | tINS | RR | 1 | core/mem_rdata_latched_23_s3/F |
| 10.664 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_23_s1/I0 |
| 11.243 | 0.579 | tINS | RR | 4 | core/mem_rdata_latched_23_s1/F |
| 11.655 | 0.413 | tNET | RR | 1 | core/n2099_s7/I0 |
| 12.234 | 0.579 | tINS | RR | 1 | core/n2099_s7/F |
| 12.646 | 0.413 | tNET | RR | 1 | core/n2099_s3/I2 |
| 13.154 | 0.507 | tINS | RR | 15 | core/n2099_s3/F |
| 13.566 | 0.413 | tNET | RR | 1 | core/n2092_s9/I1 |
| 14.134 | 0.567 | tINS | RR | 3 | core/n2092_s9/F |
| 14.546 | 0.413 | tNET | RR | 1 | core/n2092_s13/I0 |
| 15.125 | 0.579 | tINS | RR | 10 | core/n2092_s13/F |
| 15.538 | 0.413 | tNET | RR | 1 | core/n2085_s4/I0 |
| 16.116 | 0.579 | tINS | RR | 1 | core/n2085_s4/F |
| 16.529 | 0.413 | tNET | RR | 1 | core/n2085_s1/I1 |
| 17.096 | 0.567 | tINS | RR | 1 | core/n2085_s1/F |
| 17.509 | 0.413 | tNET | RR | 1 | core/n2085_s0/I1 |
| 18.076 | 0.567 | tINS | RR | 1 | core/n2085_s0/F |
| 18.489 | 0.413 | tNET | RR | 1 | core/mem_rdata_q_21_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_in | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 4417 | clk_in_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | core/mem_rdata_q_21_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | core/mem_rdata_q_21_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 18 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 9.444, 52.244%; route: 8.250, 45.640%; tC2Q: 0.382, 2.116% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:| Slack | -8.140 |
| Data Arrival Time | 18.489 |
| Data Required Time | 10.349 |
| From | core/mem_addr_28_s0 |
| To | core/mem_rdata_q_22_s0 |
| Launch Clk | clk_in[R] |
| Latch Clk | clk_in[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_in | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 4417 | clk_in_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | core/mem_addr_28_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 4 | core/mem_addr_28_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | itcm_valid_s2/I0 |
| 1.786 | 0.579 | tINS | RR | 6 | itcm_valid_s2/F |
| 2.199 | 0.413 | tNET | RR | 1 | itcm_valid_s1/I1 |
| 2.766 | 0.567 | tINS | RR | 6 | itcm_valid_s1/F |
| 3.179 | 0.413 | tNET | RR | 1 | core/n1614_s1/I2 |
| 3.686 | 0.507 | tINS | RR | 3 | core/n1614_s1/F |
| 4.099 | 0.413 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I1 |
| 4.666 | 0.567 | tINS | RR | 40 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
| 5.079 | 0.413 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
| 5.368 | 0.289 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
| 5.780 | 0.413 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
| 6.288 | 0.507 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
| 6.700 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s4/I2 |
| 7.208 | 0.507 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s4/F |
| 7.620 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s1/I0 |
| 7.770 | 0.150 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s1/O |
| 8.183 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s/I1 |
| 8.269 | 0.086 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_7_s/O |
| 8.681 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_23_s6/I0 |
| 9.260 | 0.579 | tINS | RR | 1 | core/mem_rdata_latched_23_s6/F |
| 9.673 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_23_s3/I0 |
| 10.251 | 0.579 | tINS | RR | 1 | core/mem_rdata_latched_23_s3/F |
| 10.664 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_23_s1/I0 |
| 11.243 | 0.579 | tINS | RR | 4 | core/mem_rdata_latched_23_s1/F |
| 11.655 | 0.413 | tNET | RR | 1 | core/n2099_s7/I0 |
| 12.234 | 0.579 | tINS | RR | 1 | core/n2099_s7/F |
| 12.646 | 0.413 | tNET | RR | 1 | core/n2099_s3/I2 |
| 13.154 | 0.507 | tINS | RR | 15 | core/n2099_s3/F |
| 13.566 | 0.413 | tNET | RR | 1 | core/n2092_s9/I1 |
| 14.134 | 0.567 | tINS | RR | 3 | core/n2092_s9/F |
| 14.546 | 0.413 | tNET | RR | 1 | core/n2092_s13/I0 |
| 15.125 | 0.579 | tINS | RR | 10 | core/n2092_s13/F |
| 15.538 | 0.413 | tNET | RR | 1 | core/n2084_s7/I0 |
| 16.116 | 0.579 | tINS | RR | 1 | core/n2084_s7/F |
| 16.529 | 0.413 | tNET | RR | 1 | core/n2084_s2/I1 |
| 17.096 | 0.567 | tINS | RR | 1 | core/n2084_s2/F |
| 17.509 | 0.413 | tNET | RR | 1 | core/n2084_s0/I1 |
| 18.076 | 0.567 | tINS | RR | 1 | core/n2084_s0/F |
| 18.489 | 0.413 | tNET | RR | 1 | core/mem_rdata_q_22_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_in | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 4417 | clk_in_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | core/mem_rdata_q_22_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | core/mem_rdata_q_22_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 18 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 9.444, 52.244%; route: 8.250, 45.640%; tC2Q: 0.382, 2.116% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:| Slack | -8.140 |
| Data Arrival Time | 18.489 |
| Data Required Time | 10.349 |
| From | core/mem_addr_28_s0 |
| To | core/mem_rdata_q_23_s0 |
| Launch Clk | clk_in[R] |
| Latch Clk | clk_in[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_in | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 4417 | clk_in_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | core/mem_addr_28_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 4 | core/mem_addr_28_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | itcm_valid_s2/I0 |
| 1.786 | 0.579 | tINS | RR | 6 | itcm_valid_s2/F |
| 2.199 | 0.413 | tNET | RR | 1 | itcm_valid_s1/I1 |
| 2.766 | 0.567 | tINS | RR | 6 | itcm_valid_s1/F |
| 3.179 | 0.413 | tNET | RR | 1 | core/n1614_s1/I2 |
| 3.686 | 0.507 | tINS | RR | 3 | core/n1614_s1/F |
| 4.099 | 0.413 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I1 |
| 4.666 | 0.567 | tINS | RR | 40 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
| 5.079 | 0.413 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
| 5.368 | 0.289 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
| 5.780 | 0.413 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
| 6.288 | 0.507 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
| 6.700 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s4/I2 |
| 7.208 | 0.507 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s4/F |
| 7.620 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s1/I0 |
| 7.770 | 0.150 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s1/O |
| 8.183 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_7_s/I1 |
| 8.269 | 0.086 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_7_s/O |
| 8.681 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_23_s6/I0 |
| 9.260 | 0.579 | tINS | RR | 1 | core/mem_rdata_latched_23_s6/F |
| 9.673 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_23_s3/I0 |
| 10.251 | 0.579 | tINS | RR | 1 | core/mem_rdata_latched_23_s3/F |
| 10.664 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_23_s1/I0 |
| 11.243 | 0.579 | tINS | RR | 4 | core/mem_rdata_latched_23_s1/F |
| 11.655 | 0.413 | tNET | RR | 1 | core/n2099_s7/I0 |
| 12.234 | 0.579 | tINS | RR | 1 | core/n2099_s7/F |
| 12.646 | 0.413 | tNET | RR | 1 | core/n2099_s3/I2 |
| 13.154 | 0.507 | tINS | RR | 15 | core/n2099_s3/F |
| 13.566 | 0.413 | tNET | RR | 1 | core/n2092_s9/I1 |
| 14.134 | 0.567 | tINS | RR | 3 | core/n2092_s9/F |
| 14.546 | 0.413 | tNET | RR | 1 | core/n2092_s13/I0 |
| 15.125 | 0.579 | tINS | RR | 10 | core/n2092_s13/F |
| 15.538 | 0.413 | tNET | RR | 1 | core/n2083_s7/I1 |
| 16.105 | 0.567 | tINS | RR | 1 | core/n2083_s7/F |
| 16.518 | 0.413 | tNET | RR | 1 | core/n2083_s2/I0 |
| 17.096 | 0.579 | tINS | RR | 1 | core/n2083_s2/F |
| 17.509 | 0.413 | tNET | RR | 1 | core/n2083_s0/I1 |
| 18.076 | 0.567 | tINS | RR | 1 | core/n2083_s0/F |
| 18.489 | 0.413 | tNET | RR | 1 | core/mem_rdata_q_23_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_in | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 4417 | clk_in_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | core/mem_rdata_q_23_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | core/mem_rdata_q_23_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 18 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 9.444, 52.244%; route: 8.250, 45.640%; tC2Q: 0.382, 2.116% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |