Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picorv32.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\advspi.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\ahb_bus.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_dtcm.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_itcm.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_bus.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_brancher.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbgpio.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbi2c.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbspi.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbuart.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\simpleuart.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\dm.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.01 (64-bit) |
| Part Number | GW2A-LV55PG484C8/I7 |
| Device | GW2A-55 |
| Device Version | C |
| Created Time | Tue Feb 10 10:39:58 2026 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Gowin_PicoRV32_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 126.801MB Running netlist conversion: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.146s, Peak memory usage = 126.801MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.984s, Elapsed time = 0h 0m 0.996s, Peak memory usage = 126.801MB Optimizing Phase 1: CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.41s, Peak memory usage = 126.801MB Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 126.801MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.937s, Elapsed time = 0h 0m 0.942s, Peak memory usage = 126.801MB Inferring Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.078s, Peak memory usage = 126.801MB Inferring Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.079s, Peak memory usage = 126.801MB Inferring Phase 3: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.045s, Peak memory usage = 126.801MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 126.801MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.334s, Peak memory usage = 126.801MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.5s, Elapsed time = 0h 0m 0.512s, Peak memory usage = 126.801MB Tech-Mapping Phase 3: CPU time = 0h 0m 26s, Elapsed time = 0h 0m 26s, Peak memory usage = 144.785MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.859s, Elapsed time = 0h 0m 0.947s, Peak memory usage = 144.785MB Generate output files: CPU time = 0h 0m 0.75s, Elapsed time = 0h 0m 0.791s, Peak memory usage = 172.441MB |
| Total Time and Memory Usage | CPU time = 0h 0m 34s, Elapsed time = 0h 0m 34s, Peak memory usage = 172.441MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 241 |
| I/O Buf | 239 |
| IBUF | 84 |
| OBUF | 147 |
| TBUF | 1 |
| IOBUF | 7 |
| Register | 4013 |
| DFF | 217 |
| DFFE | 1841 |
| DFFS | 20 |
| DFFSE | 78 |
| DFFR | 168 |
| DFFRE | 569 |
| DFFP | 6 |
| DFFPE | 11 |
| DFFC | 160 |
| DFFCE | 943 |
| LUT | 6275 |
| LUT2 | 519 |
| LUT3 | 1977 |
| LUT4 | 3779 |
| ALU | 592 |
| ALU | 592 |
| SSRAM | 24 |
| RAM16SDP4 | 24 |
| INV | 26 |
| INV | 26 |
| DSP | |
| MULT36X36 | 1 |
| BSRAM | 32 |
| SDPB | 32 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 7037(6301 LUT, 592 ALU, 24 RAM16) / 54720 | 13% |
| Register | 4013 / 42000 | 10% |
| --Register as Latch | 0 / 42000 | 0% |
| --Register as FF | 4013 / 42000 | 10% |
| BSRAM | 32 / 140 | 23% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk_in | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_in_ibuf/I | ||
| 2 | jtag_TCK | Base | 10.000 | 100.000 | 0.000 | 5.000 | jtag_TCK_ibuf/I | ||
| 3 | u_dualportspi/u_atcspi/u_spi_spiif/n316_3 | Base | 10.000 | 100.000 | 0.000 | 5.000 | u_dualportspi/u_atcspi/u_spi_spiif/n316_s0/F |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk_in | 100.000(MHz) | 46.369(MHz) | 11 | TOP |
| 2 | jtag_TCK | 100.000(MHz) | 88.090(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -8.404 |
| Data Arrival Time | 18.729 |
| Data Required Time | 10.325 |
| From | core/mem_addr_27_s0 |
| To | core/decoded_rs1_0_s0 |
| Launch Clk | clk_in[R] |
| Latch Clk | clk_in[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_in | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3916 | clk_in_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | core/mem_addr_27_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 3 | core/mem_addr_27_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | itcm_valid_s2/I1 |
| 1.621 | 0.555 | tINS | FF | 3 | itcm_valid_s2/F |
| 2.095 | 0.474 | tNET | FF | 1 | itcm_valid_s3/I3 |
| 2.466 | 0.371 | tINS | FF | 6 | itcm_valid_s3/F |
| 2.940 | 0.474 | tNET | FF | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0 |
| 3.457 | 0.517 | tINS | FF | 4 | u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F |
| 3.931 | 0.474 | tNET | FF | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0 |
| 4.448 | 0.517 | tINS | FF | 40 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
| 4.922 | 0.474 | tNET | FF | 1 | u_dm/ram_addr_2_s2/I3 |
| 5.293 | 0.371 | tINS | FF | 70 | u_dm/ram_addr_2_s2/F |
| 5.767 | 0.474 | tNET | FF | 1 | u_dm/ram_addr_0_s0/I2 |
| 6.220 | 0.453 | tINS | FF | 103 | u_dm/ram_addr_0_s0/F |
| 6.694 | 0.474 | tNET | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s4/I2 |
| 7.147 | 0.453 | tINS | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s4/F |
| 7.621 | 0.474 | tNET | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s1/I0 |
| 7.724 | 0.103 | tINS | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s1/O |
| 8.198 | 0.474 | tNET | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s/I1 |
| 8.301 | 0.103 | tINS | FF | 2 | u_dm/u_s_debug_ram/ram_dout_Z_11_s/O |
| 8.775 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s12/I0 |
| 9.292 | 0.517 | tINS | FF | 1 | core/mem_rdata_latched_27_s12/F |
| 9.766 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s8/I3 |
| 10.137 | 0.371 | tINS | FF | 1 | core/mem_rdata_latched_27_s8/F |
| 10.611 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s4/I0 |
| 11.128 | 0.517 | tINS | FF | 1 | core/mem_rdata_latched_27_s4/F |
| 11.602 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s3/I0 |
| 12.119 | 0.517 | tINS | FF | 4 | core/mem_rdata_latched_27_s3/F |
| 12.593 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s2/I1 |
| 13.148 | 0.555 | tINS | FF | 2 | core/mem_rdata_latched_27_s2/F |
| 13.622 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_11_s1/I1 |
| 14.177 | 0.555 | tINS | FF | 23 | core/mem_rdata_latched_11_s1/F |
| 14.651 | 0.474 | tNET | FF | 1 | core/n5231_s11/I0 |
| 15.168 | 0.517 | tINS | FF | 4 | core/n5231_s11/F |
| 15.642 | 0.474 | tNET | FF | 1 | core/n5231_s7/I1 |
| 16.197 | 0.555 | tINS | FF | 7 | core/n5231_s7/F |
| 16.671 | 0.474 | tNET | FF | 1 | core/n5585_s2/I1 |
| 17.226 | 0.555 | tINS | FF | 3 | core/n5585_s2/F |
| 17.700 | 0.474 | tNET | FF | 1 | core/n5588_s0/I1 |
| 18.255 | 0.555 | tINS | FF | 1 | core/n5588_s0/F |
| 18.729 | 0.474 | tNET | FF | 1 | core/decoded_rs1_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_in | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 3916 | clk_in_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | core/decoded_rs1_0_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | core/decoded_rs1_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 18 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 8.657, 47.128%; route: 9.480, 51.609%; tC2Q: 0.232, 1.263% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 2
Path Summary:| Slack | -8.404 |
| Data Arrival Time | 18.729 |
| Data Required Time | 10.325 |
| From | core/mem_addr_27_s0 |
| To | core/decoded_rs1_2_s0 |
| Launch Clk | clk_in[R] |
| Latch Clk | clk_in[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_in | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3916 | clk_in_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | core/mem_addr_27_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 3 | core/mem_addr_27_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | itcm_valid_s2/I1 |
| 1.621 | 0.555 | tINS | FF | 3 | itcm_valid_s2/F |
| 2.095 | 0.474 | tNET | FF | 1 | itcm_valid_s3/I3 |
| 2.466 | 0.371 | tINS | FF | 6 | itcm_valid_s3/F |
| 2.940 | 0.474 | tNET | FF | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0 |
| 3.457 | 0.517 | tINS | FF | 4 | u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F |
| 3.931 | 0.474 | tNET | FF | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0 |
| 4.448 | 0.517 | tINS | FF | 40 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
| 4.922 | 0.474 | tNET | FF | 1 | u_dm/ram_addr_2_s2/I3 |
| 5.293 | 0.371 | tINS | FF | 70 | u_dm/ram_addr_2_s2/F |
| 5.767 | 0.474 | tNET | FF | 1 | u_dm/ram_addr_0_s0/I2 |
| 6.220 | 0.453 | tINS | FF | 103 | u_dm/ram_addr_0_s0/F |
| 6.694 | 0.474 | tNET | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s4/I2 |
| 7.147 | 0.453 | tINS | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s4/F |
| 7.621 | 0.474 | tNET | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s1/I0 |
| 7.724 | 0.103 | tINS | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s1/O |
| 8.198 | 0.474 | tNET | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s/I1 |
| 8.301 | 0.103 | tINS | FF | 2 | u_dm/u_s_debug_ram/ram_dout_Z_11_s/O |
| 8.775 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s12/I0 |
| 9.292 | 0.517 | tINS | FF | 1 | core/mem_rdata_latched_27_s12/F |
| 9.766 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s8/I3 |
| 10.137 | 0.371 | tINS | FF | 1 | core/mem_rdata_latched_27_s8/F |
| 10.611 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s4/I0 |
| 11.128 | 0.517 | tINS | FF | 1 | core/mem_rdata_latched_27_s4/F |
| 11.602 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s3/I0 |
| 12.119 | 0.517 | tINS | FF | 4 | core/mem_rdata_latched_27_s3/F |
| 12.593 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s2/I1 |
| 13.148 | 0.555 | tINS | FF | 2 | core/mem_rdata_latched_27_s2/F |
| 13.622 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_11_s1/I1 |
| 14.177 | 0.555 | tINS | FF | 23 | core/mem_rdata_latched_11_s1/F |
| 14.651 | 0.474 | tNET | FF | 1 | core/n5231_s11/I0 |
| 15.168 | 0.517 | tINS | FF | 4 | core/n5231_s11/F |
| 15.642 | 0.474 | tNET | FF | 1 | core/n5231_s7/I1 |
| 16.197 | 0.555 | tINS | FF | 7 | core/n5231_s7/F |
| 16.671 | 0.474 | tNET | FF | 1 | core/n5585_s2/I1 |
| 17.226 | 0.555 | tINS | FF | 3 | core/n5585_s2/F |
| 17.700 | 0.474 | tNET | FF | 1 | core/n5586_s0/I1 |
| 18.255 | 0.555 | tINS | FF | 1 | core/n5586_s0/F |
| 18.729 | 0.474 | tNET | FF | 1 | core/decoded_rs1_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_in | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 3916 | clk_in_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | core/decoded_rs1_2_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | core/decoded_rs1_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 18 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 8.657, 47.128%; route: 9.480, 51.609%; tC2Q: 0.232, 1.263% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 3
Path Summary:| Slack | -8.404 |
| Data Arrival Time | 18.729 |
| Data Required Time | 10.325 |
| From | core/mem_addr_27_s0 |
| To | core/decoded_rd_0_s0 |
| Launch Clk | clk_in[R] |
| Latch Clk | clk_in[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_in | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3916 | clk_in_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | core/mem_addr_27_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 3 | core/mem_addr_27_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | itcm_valid_s2/I1 |
| 1.621 | 0.555 | tINS | FF | 3 | itcm_valid_s2/F |
| 2.095 | 0.474 | tNET | FF | 1 | itcm_valid_s3/I3 |
| 2.466 | 0.371 | tINS | FF | 6 | itcm_valid_s3/F |
| 2.940 | 0.474 | tNET | FF | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0 |
| 3.457 | 0.517 | tINS | FF | 4 | u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F |
| 3.931 | 0.474 | tNET | FF | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0 |
| 4.448 | 0.517 | tINS | FF | 40 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
| 4.922 | 0.474 | tNET | FF | 1 | u_dm/ram_addr_2_s2/I3 |
| 5.293 | 0.371 | tINS | FF | 70 | u_dm/ram_addr_2_s2/F |
| 5.767 | 0.474 | tNET | FF | 1 | u_dm/ram_addr_0_s0/I2 |
| 6.220 | 0.453 | tINS | FF | 103 | u_dm/ram_addr_0_s0/F |
| 6.694 | 0.474 | tNET | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s4/I2 |
| 7.147 | 0.453 | tINS | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s4/F |
| 7.621 | 0.474 | tNET | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s1/I0 |
| 7.724 | 0.103 | tINS | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s1/O |
| 8.198 | 0.474 | tNET | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s/I1 |
| 8.301 | 0.103 | tINS | FF | 2 | u_dm/u_s_debug_ram/ram_dout_Z_11_s/O |
| 8.775 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s12/I0 |
| 9.292 | 0.517 | tINS | FF | 1 | core/mem_rdata_latched_27_s12/F |
| 9.766 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s8/I3 |
| 10.137 | 0.371 | tINS | FF | 1 | core/mem_rdata_latched_27_s8/F |
| 10.611 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s4/I0 |
| 11.128 | 0.517 | tINS | FF | 1 | core/mem_rdata_latched_27_s4/F |
| 11.602 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s3/I0 |
| 12.119 | 0.517 | tINS | FF | 4 | core/mem_rdata_latched_27_s3/F |
| 12.593 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s2/I1 |
| 13.148 | 0.555 | tINS | FF | 2 | core/mem_rdata_latched_27_s2/F |
| 13.622 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_11_s1/I1 |
| 14.177 | 0.555 | tINS | FF | 23 | core/mem_rdata_latched_11_s1/F |
| 14.651 | 0.474 | tNET | FF | 1 | core/n5579_s3/I1 |
| 15.206 | 0.555 | tINS | FF | 3 | core/n5579_s3/F |
| 15.680 | 0.474 | tNET | FF | 1 | core/n5579_s2/I1 |
| 16.235 | 0.555 | tINS | FF | 1 | core/n5579_s2/F |
| 16.709 | 0.474 | tNET | FF | 1 | core/n5582_s1/I1 |
| 17.264 | 0.555 | tINS | FF | 1 | core/n5582_s1/F |
| 17.738 | 0.474 | tNET | FF | 1 | core/n5582_s0/I0 |
| 18.255 | 0.517 | tINS | FF | 1 | core/n5582_s0/F |
| 18.729 | 0.474 | tNET | FF | 1 | core/decoded_rd_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_in | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 3916 | clk_in_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | core/decoded_rd_0_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | core/decoded_rd_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 18 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 8.657, 47.128%; route: 9.480, 51.609%; tC2Q: 0.232, 1.263% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 4
Path Summary:| Slack | -8.366 |
| Data Arrival Time | 18.691 |
| Data Required Time | 10.325 |
| From | core/mem_addr_27_s0 |
| To | core/mem_rdata_q_22_s0 |
| Launch Clk | clk_in[R] |
| Latch Clk | clk_in[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_in | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3916 | clk_in_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | core/mem_addr_27_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 3 | core/mem_addr_27_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | itcm_valid_s2/I1 |
| 1.621 | 0.555 | tINS | FF | 3 | itcm_valid_s2/F |
| 2.095 | 0.474 | tNET | FF | 1 | itcm_valid_s3/I3 |
| 2.466 | 0.371 | tINS | FF | 6 | itcm_valid_s3/F |
| 2.940 | 0.474 | tNET | FF | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0 |
| 3.457 | 0.517 | tINS | FF | 4 | u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F |
| 3.931 | 0.474 | tNET | FF | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0 |
| 4.448 | 0.517 | tINS | FF | 40 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
| 4.922 | 0.474 | tNET | FF | 1 | u_dm/ram_addr_2_s2/I3 |
| 5.293 | 0.371 | tINS | FF | 70 | u_dm/ram_addr_2_s2/F |
| 5.767 | 0.474 | tNET | FF | 1 | u_dm/ram_addr_0_s0/I2 |
| 6.220 | 0.453 | tINS | FF | 103 | u_dm/ram_addr_0_s0/F |
| 6.694 | 0.474 | tNET | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s4/I2 |
| 7.147 | 0.453 | tINS | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s4/F |
| 7.621 | 0.474 | tNET | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s1/I0 |
| 7.724 | 0.103 | tINS | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s1/O |
| 8.198 | 0.474 | tNET | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s/I1 |
| 8.301 | 0.103 | tINS | FF | 2 | u_dm/u_s_debug_ram/ram_dout_Z_11_s/O |
| 8.775 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s12/I0 |
| 9.292 | 0.517 | tINS | FF | 1 | core/mem_rdata_latched_27_s12/F |
| 9.766 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s8/I3 |
| 10.137 | 0.371 | tINS | FF | 1 | core/mem_rdata_latched_27_s8/F |
| 10.611 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s4/I0 |
| 11.128 | 0.517 | tINS | FF | 1 | core/mem_rdata_latched_27_s4/F |
| 11.602 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s3/I0 |
| 12.119 | 0.517 | tINS | FF | 4 | core/mem_rdata_latched_27_s3/F |
| 12.593 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s2/I1 |
| 13.148 | 0.555 | tINS | FF | 2 | core/mem_rdata_latched_27_s2/F |
| 13.622 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_11_s1/I1 |
| 14.177 | 0.555 | tINS | FF | 23 | core/mem_rdata_latched_11_s1/F |
| 14.651 | 0.474 | tNET | FF | 1 | core/n2079_s5/I0 |
| 15.168 | 0.517 | tINS | FF | 12 | core/n2079_s5/F |
| 15.642 | 0.474 | tNET | FF | 1 | core/n2083_s7/I0 |
| 16.159 | 0.517 | tINS | FF | 4 | core/n2083_s7/F |
| 16.633 | 0.474 | tNET | FF | 1 | core/n2084_s2/I1 |
| 17.188 | 0.555 | tINS | FF | 1 | core/n2084_s2/F |
| 17.662 | 0.474 | tNET | FF | 1 | core/n2084_s0/I1 |
| 18.217 | 0.555 | tINS | FF | 1 | core/n2084_s0/F |
| 18.691 | 0.474 | tNET | FF | 1 | core/mem_rdata_q_22_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_in | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 3916 | clk_in_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | core/mem_rdata_q_22_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | core/mem_rdata_q_22_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 18 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 8.619, 47.019%; route: 9.480, 51.715%; tC2Q: 0.232, 1.266% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 5
Path Summary:| Slack | -8.366 |
| Data Arrival Time | 18.691 |
| Data Required Time | 10.325 |
| From | core/mem_addr_27_s0 |
| To | core/mem_rdata_q_28_s0 |
| Launch Clk | clk_in[R] |
| Latch Clk | clk_in[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_in | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3916 | clk_in_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | core/mem_addr_27_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 3 | core/mem_addr_27_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | itcm_valid_s2/I1 |
| 1.621 | 0.555 | tINS | FF | 3 | itcm_valid_s2/F |
| 2.095 | 0.474 | tNET | FF | 1 | itcm_valid_s3/I3 |
| 2.466 | 0.371 | tINS | FF | 6 | itcm_valid_s3/F |
| 2.940 | 0.474 | tNET | FF | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0 |
| 3.457 | 0.517 | tINS | FF | 4 | u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F |
| 3.931 | 0.474 | tNET | FF | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0 |
| 4.448 | 0.517 | tINS | FF | 40 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
| 4.922 | 0.474 | tNET | FF | 1 | u_dm/ram_addr_2_s2/I3 |
| 5.293 | 0.371 | tINS | FF | 70 | u_dm/ram_addr_2_s2/F |
| 5.767 | 0.474 | tNET | FF | 1 | u_dm/ram_addr_0_s0/I2 |
| 6.220 | 0.453 | tINS | FF | 103 | u_dm/ram_addr_0_s0/F |
| 6.694 | 0.474 | tNET | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s4/I2 |
| 7.147 | 0.453 | tINS | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s4/F |
| 7.621 | 0.474 | tNET | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s1/I0 |
| 7.724 | 0.103 | tINS | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s1/O |
| 8.198 | 0.474 | tNET | FF | 1 | u_dm/u_s_debug_ram/ram_dout_Z_11_s/I1 |
| 8.301 | 0.103 | tINS | FF | 2 | u_dm/u_s_debug_ram/ram_dout_Z_11_s/O |
| 8.775 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s12/I0 |
| 9.292 | 0.517 | tINS | FF | 1 | core/mem_rdata_latched_27_s12/F |
| 9.766 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s8/I3 |
| 10.137 | 0.371 | tINS | FF | 1 | core/mem_rdata_latched_27_s8/F |
| 10.611 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s4/I0 |
| 11.128 | 0.517 | tINS | FF | 1 | core/mem_rdata_latched_27_s4/F |
| 11.602 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s3/I0 |
| 12.119 | 0.517 | tINS | FF | 4 | core/mem_rdata_latched_27_s3/F |
| 12.593 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_27_s2/I1 |
| 13.148 | 0.555 | tINS | FF | 2 | core/mem_rdata_latched_27_s2/F |
| 13.622 | 0.474 | tNET | FF | 1 | core/mem_rdata_latched_11_s1/I1 |
| 14.177 | 0.555 | tINS | FF | 23 | core/mem_rdata_latched_11_s1/F |
| 14.651 | 0.474 | tNET | FF | 1 | core/n2079_s5/I0 |
| 15.168 | 0.517 | tINS | FF | 12 | core/n2079_s5/F |
| 15.642 | 0.474 | tNET | FF | 1 | core/n2078_s6/I0 |
| 16.159 | 0.517 | tINS | FF | 2 | core/n2078_s6/F |
| 16.633 | 0.474 | tNET | FF | 1 | core/n2078_s2/I1 |
| 17.188 | 0.555 | tINS | FF | 1 | core/n2078_s2/F |
| 17.662 | 0.474 | tNET | FF | 1 | core/n2078_s0/I1 |
| 18.217 | 0.555 | tINS | FF | 1 | core/n2078_s0/F |
| 18.691 | 0.474 | tNET | FF | 1 | core/mem_rdata_q_28_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_in | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 3916 | clk_in_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | core/mem_rdata_q_28_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | core/mem_rdata_q_28_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 18 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 8.619, 47.019%; route: 9.480, 51.715%; tC2Q: 0.232, 1.266% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |