Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_top.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_soc.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_ddr3.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_flash.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\RiscV_AE350_SOC\data\ddr3_1_4code_hs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\RiscV_AE350_SOC\data\DDR3_TOP.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\RiscV_AE350_SOC\data\fifo_top_32to128.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\RiscV_AE350_SOC\data\fifo_top_128to32.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\RiscV_AE350_SOC\data\gw_dtcm.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\RiscV_AE350_SOC\data\gw_itcm.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9.03 (64-bit) |
| Part Number | GW5AST-LV138FPG676AES |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Tue May 14 09:59:51 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | RiscV_AE350_SOC_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 186.582MB Running netlist conversion: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.127s, Peak memory usage = 186.582MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.89s, Elapsed time = 0h 0m 0.882s, Peak memory usage = 186.582MB Optimizing Phase 1: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.436s, Peak memory usage = 186.582MB Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 186.582MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.781s, Elapsed time = 0h 0m 0.789s, Peak memory usage = 186.582MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 186.582MB Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.07s, Peak memory usage = 186.582MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 186.582MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 186.582MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.466s, Peak memory usage = 186.582MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.413s, Peak memory usage = 186.582MB Tech-Mapping Phase 3: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 189.395MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.703s, Elapsed time = 0h 0m 0.76s, Peak memory usage = 189.395MB Generate output files: CPU time = 0h 0m 0.656s, Elapsed time = 0h 0m 0.748s, Peak memory usage = 200.469MB |
| Total Time and Memory Usage | CPU time = 0h 0m 14s, Elapsed time = 0h 0m 14s, Peak memory usage = 200.469MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 115 |
| I/O Buf | 112 |
| IBUF | 20 |
| OBUF | 33 |
| TBUF | 2 |
| IOBUF | 54 |
| ELVDS_OBUF | 1 |
| ELVDS_IOBUF | 2 |
| Register | 4250 |
| DFFSE | 1 |
| DFFRE | 430 |
| DFFPE | 88 |
| DFFCE | 3730 |
| DLCE | 1 |
| LUT | 3422 |
| LUT2 | 505 |
| LUT3 | 1471 |
| LUT4 | 1446 |
| ALU | 219 |
| ALU | 219 |
| SSRAM | 64 |
| RAM16SDP4 | 64 |
| INV | 129 |
| INV | 129 |
| IOLOGIC | 76 |
| IDES8_MEM | 16 |
| OSER8 | 24 |
| OSER8_MEM | 20 |
| IODELAY | 16 |
| BSRAM | 16 |
| SDPB | 4 |
| SDPX9B | 12 |
| CLOCK | 4 |
| CLKDIV | 1 |
| DQS | 2 |
| DDRDLL | 1 |
| AE350_SOC | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 4154(3551 LUT, 219 ALU, 64 RAM16) / 138240 | 4% |
| Register | 4250 / 139140 | 4% |
| --Register as Latch | 1 / 139140 | <1% |
| --Register as FF | 4249 / 139140 | 4% |
| BSRAM | 16 / 340 | 5% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| DDR3_MEMORY_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | DDR3_MEMORY_CLK_ibuf/I | ||
| AHB_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | AHB_CLK_ibuf/I | ||
| FLASH_SPI_CLK_iobuf/I | Base | 10.000 | 100.0 | 0.000 | 5.000 | FLASH_SPI_CLK_iobuf/I | ||
| DDR3_CLK_IN | Base | 10.000 | 100.0 | 0.000 | 5.000 | DDR3_CLK_IN_ibuf/I | ||
| DDR_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | DDR_CLK_ibuf/I | ||
| FLASH_SPI_CLK_in | Base | 10.000 | 100.0 | 0.000 | 5.000 | FLASH_SPI_CLK_iobuf/O | ||
| u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | DDR3_MEMORY_CLK_ibuf/I | DDR3_MEMORY_CLK | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | DDR3_MEMORY_CLK | 100.000(MHz) | 1115.449(MHz) | 1 | TOP |
| 2 | AHB_CLK | 100.000(MHz) | 74.669(MHz) | 7 | TOP |
| 3 | DDR3_CLK_IN | 100.000(MHz) | 163.066(MHz) | 7 | TOP |
| 4 | DDR_CLK | 100.000(MHz) | 221.117(MHz) | 5 | TOP |
| 5 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 25.000(MHz) | 161.225(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -1.696 |
| Data Arrival Time | 7.073 |
| Data Required Time | 5.376 |
| From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s1 |
| To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_d_en_r_s0 |
| Launch Clk | AHB_CLK[F] |
| Latch Clk | AHB_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | AHB_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 290 | AHB_CLK_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s1/CLK |
| 0.795 | 0.382 | tC2Q | RR | 7 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s1/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s13/I0 |
| 1.786 | 0.579 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s13/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s19/I0 |
| 2.778 | 0.579 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s19/F |
| 3.190 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_0_s19/I0 |
| 3.769 | 0.579 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_0_s19/F |
| 4.181 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_0_s10/I0 |
| 4.760 | 0.579 | tINS | RR | 7 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_0_s10/F |
| 5.173 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s2/I2 |
| 5.680 | 0.507 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s2/F |
| 6.093 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s1/I1 |
| 6.660 | 0.567 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s1/F |
| 7.073 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_d_en_r_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | AHB_CLK | |||
| 5.000 | 0.000 | tCL | FF | 1 | AHB_CLK_ibuf/I |
| 5.000 | 0.000 | tINS | FF | 290 | AHB_CLK_ibuf/O |
| 5.385 | 0.385 | tNET | FF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_d_en_r_s0/CLK |
| 5.376 | -0.009 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_d_en_r_s0 |
| Clock Skew: | -0.028 |
| Setup Relationship: | 5.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.390, 50.901%; route: 2.887, 43.356%; tC2Q: 0.382, 5.743% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:| Slack | -1.726 |
| Data Arrival Time | 11.828 |
| Data Required Time | 10.101 |
| From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s1 |
| To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1 |
| Launch Clk | AHB_CLK[R] |
| Latch Clk | AHB_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | AHB_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 290 | AHB_CLK_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s1/CLK |
| 0.795 | 0.382 | tC2Q | RR | 7 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s1/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s13/I0 |
| 1.786 | 0.579 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s13/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_0_s16/I0 |
| 2.778 | 0.579 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_0_s16/F |
| 3.190 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_0_s13/I2 |
| 3.697 | 0.507 | tINS | RR | 6 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_0_s13/F |
| 4.110 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s7/I0 |
| 4.689 | 0.579 | tINS | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s7/F |
| 5.101 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s6/I1 |
| 5.669 | 0.567 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s6/F |
| 6.081 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/I1 |
| 6.649 | 0.567 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/F |
| 7.061 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/I0 |
| 7.640 | 0.579 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/F |
| 8.053 | 0.413 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1 |
| 8.653 | 0.600 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT |
| 8.653 | 0.000 | tNET | FF | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN |
| 8.703 | 0.050 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT |
| 8.703 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN |
| 8.753 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT |
| 8.753 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN |
| 8.803 | 0.050 | tINS | RR | 12 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT |
| 9.215 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/I0 |
| 9.794 | 0.579 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/F |
| 10.206 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/I3 |
| 10.495 | 0.289 | tINS | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/F |
| 10.908 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/I2 |
| 11.415 | 0.507 | tINS | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/F |
| 11.828 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | AHB_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 290 | AHB_CLK_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1/CLK |
| 10.101 | -0.311 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 13 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 6.083, 53.285%; route: 4.950, 43.364%; tC2Q: 0.382, 3.351% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:| Slack | -1.726 |
| Data Arrival Time | 11.828 |
| Data Required Time | 10.101 |
| From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s1 |
| To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1 |
| Launch Clk | AHB_CLK[R] |
| Latch Clk | AHB_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | AHB_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 290 | AHB_CLK_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s1/CLK |
| 0.795 | 0.382 | tC2Q | RR | 7 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s1/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s13/I0 |
| 1.786 | 0.579 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s13/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_0_s16/I0 |
| 2.778 | 0.579 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_0_s16/F |
| 3.190 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_0_s13/I2 |
| 3.697 | 0.507 | tINS | RR | 6 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_0_s13/F |
| 4.110 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s7/I0 |
| 4.689 | 0.579 | tINS | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s7/F |
| 5.101 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s6/I1 |
| 5.669 | 0.567 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s6/F |
| 6.081 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/I1 |
| 6.649 | 0.567 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/F |
| 7.061 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/I0 |
| 7.640 | 0.579 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/F |
| 8.053 | 0.413 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1 |
| 8.653 | 0.600 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT |
| 8.653 | 0.000 | tNET | FF | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN |
| 8.703 | 0.050 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT |
| 8.703 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN |
| 8.753 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT |
| 8.753 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN |
| 8.803 | 0.050 | tINS | RR | 12 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT |
| 9.215 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/I0 |
| 9.794 | 0.579 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/F |
| 10.206 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/I3 |
| 10.495 | 0.289 | tINS | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/F |
| 10.908 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/I2 |
| 11.415 | 0.507 | tINS | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/F |
| 11.828 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | AHB_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 290 | AHB_CLK_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1/CLK |
| 10.101 | -0.311 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 13 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 6.083, 53.285%; route: 4.950, 43.364%; tC2Q: 0.382, 3.351% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:| Slack | -1.726 |
| Data Arrival Time | 11.828 |
| Data Required Time | 10.101 |
| From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s1 |
| To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1 |
| Launch Clk | AHB_CLK[R] |
| Latch Clk | AHB_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | AHB_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 290 | AHB_CLK_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s1/CLK |
| 0.795 | 0.382 | tC2Q | RR | 7 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s1/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s13/I0 |
| 1.786 | 0.579 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s13/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_0_s16/I0 |
| 2.778 | 0.579 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_0_s16/F |
| 3.190 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_0_s13/I2 |
| 3.697 | 0.507 | tINS | RR | 6 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_0_s13/F |
| 4.110 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s7/I0 |
| 4.689 | 0.579 | tINS | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s7/F |
| 5.101 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s6/I1 |
| 5.669 | 0.567 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s6/F |
| 6.081 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/I1 |
| 6.649 | 0.567 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/F |
| 7.061 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/I0 |
| 7.640 | 0.579 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/F |
| 8.053 | 0.413 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1 |
| 8.653 | 0.600 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT |
| 8.653 | 0.000 | tNET | FF | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN |
| 8.703 | 0.050 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT |
| 8.703 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN |
| 8.753 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT |
| 8.753 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN |
| 8.803 | 0.050 | tINS | RR | 12 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT |
| 9.215 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/I0 |
| 9.794 | 0.579 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/F |
| 10.206 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/I3 |
| 10.495 | 0.289 | tINS | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/F |
| 10.908 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/I2 |
| 11.415 | 0.507 | tINS | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/F |
| 11.828 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | AHB_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 290 | AHB_CLK_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1/CLK |
| 10.101 | -0.311 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 13 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 6.083, 53.285%; route: 4.950, 43.364%; tC2Q: 0.382, 3.351% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:| Slack | -1.726 |
| Data Arrival Time | 11.828 |
| Data Required Time | 10.101 |
| From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s1 |
| To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_3_s1 |
| Launch Clk | AHB_CLK[R] |
| Latch Clk | AHB_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | AHB_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 290 | AHB_CLK_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s1/CLK |
| 0.795 | 0.382 | tC2Q | RR | 7 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s1/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s13/I0 |
| 1.786 | 0.579 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s13/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_0_s16/I0 |
| 2.778 | 0.579 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_0_s16/F |
| 3.190 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_0_s13/I2 |
| 3.697 | 0.507 | tINS | RR | 6 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_0_s13/F |
| 4.110 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s7/I0 |
| 4.689 | 0.579 | tINS | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s7/F |
| 5.101 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s6/I1 |
| 5.669 | 0.567 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s6/F |
| 6.081 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/I1 |
| 6.649 | 0.567 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/F |
| 7.061 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/I0 |
| 7.640 | 0.579 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/F |
| 8.053 | 0.413 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1 |
| 8.653 | 0.600 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT |
| 8.653 | 0.000 | tNET | FF | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN |
| 8.703 | 0.050 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT |
| 8.703 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN |
| 8.753 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT |
| 8.753 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN |
| 8.803 | 0.050 | tINS | RR | 12 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT |
| 9.215 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/I0 |
| 9.794 | 0.579 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/F |
| 10.206 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/I3 |
| 10.495 | 0.289 | tINS | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/F |
| 10.908 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/I2 |
| 11.415 | 0.507 | tINS | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/F |
| 11.828 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_3_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | AHB_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 290 | AHB_CLK_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_3_s1/CLK |
| 10.101 | -0.311 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_3_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 13 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 6.083, 53.285%; route: 4.950, 43.364%; tC2Q: 0.382, 3.351% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |