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RiscV_AE350_SOC RTOS FPGA Reference Design Read Me File
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Frequency
    CORE clock        : 800MHz
    DDR clock         : 100MHz
    AHB clock         : 100MHz
    APB clock         : 100MHz
    RTC clock         : 10MHz
    DDR3 memory clock : 300MHz
    DDR3 input clock  : 50MHz
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Platform
    DK_START_GW5AT138_V2.1
        GW5AST-LV138FPG676AES
        GW5AST-138
        B
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Configuration
    SPI Flash Instruction Memory
    DDR3 Data Memory
      - Default DDR3 Settings
    PIT
    UART2
    GPIO
    WDT
    RTC
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FPGA IDE
    Version tested: Gowin_V1.9.9.03 (64-bit)
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