Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\ahb_def_slave.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\ahb_s_mux.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\ahb_to_sram.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\BusMatrix.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_bus_matrix.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_cdc_capt_sync.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_cdc_connect.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_cdc_random.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_clk_gate.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_code_mux.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dap_ahb_ap.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dap_ahb_ap_defs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dap_ahb_ap_mst.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dap_ahb_ap_slv.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dap_ahb_ap_sync.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dap_ahb_ap_undefs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_16bit_dec.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_32bit_dec.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_alu.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_alu_bshift.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_alu_ctl.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_alu_dp.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_alu_srtdiv.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_br_dec.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_dec.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_defs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_etmintf.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_exec.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_fetch.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_fetch_ahbintf.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_fetch_ctl.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_lsu.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_lsu_ahbintf.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_lsu_ctl.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_regbank.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_regfile.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_status.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_undefs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dwt.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dwt_apb_if.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dwt_comp.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dwt_defs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dwt_packet_gen.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dwt_packet_state.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dwt_undefs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_apb_if.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_clk_gate.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_control_reg.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_defs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_event_gen.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_fifo.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_gen.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_res_control.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_sync_count.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_trace.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_trace_out.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_trc_en.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_trig_gen.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_trigger.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_undefs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_example_pmu.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_flash_mux.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_fpb.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_fpb_defs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_fpb_undefs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_htm_port.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_itm.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_itm_arb.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_itm_emit.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_itm_fifo.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_itm_fifo_byte.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_itm_if.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_itm_ts.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_lic_defs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu_ahb_ctl.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu_align.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu_comp.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu_default.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu_defs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu_full.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu_maskgen.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu_ppb_intf.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu_region.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu_regions.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu_undefs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_bit_master.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_decode_dap.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_decode_dcore.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_decode_icore.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_defs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_input_stage_dap.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_input_stage_dcore.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_input_stage_icore.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_output_stage_dcode.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_output_stage_icode.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_output_stage_ppb.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_output_stage_sys.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_undefs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_nvic.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_nvic_cell.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_nvic_defs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_nvic_int_state.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_nvic_main.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_nvic_ppb_intf.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_nvic_preempt.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_nvic_reg.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_nvic_tree.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_nvic_undefs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_ppb_ahb_to_apb.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_ppb_decoder.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_rom_table.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_sync.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_tpiu.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_tpiu_apb_if.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_tpiu_atb_fifo.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_tpiu_atb_sync.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_tpiu_defs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_tpiu_formatter.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_tpiu_trace_clk.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_tpiu_trace_fifo.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_tpiu_trace_out.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_tpiu_trace_sync.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_tpiu_undefs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_wic.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\CM3ETM.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_ethmac.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_ethmac_miim_wrapper.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_ethmac_rx_buffer_to_ahb.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_ethmac_rx_to_buffer.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_ethmac_rx_wrapper.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_ethmac_sdp_wrapper_32bit.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_ethmac_top.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_ethmac_tx_wrapper.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_ethmac_wrapper.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_gpio.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_ahbif_ctrl.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_arbiter.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_async_fifo_clr.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_config.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_const.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_ctrl.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_eilmif_ctrl.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_fifo.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_gck.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_pad_lib.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_reg.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_regif.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_regif_ctrl.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_spiif.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_sync.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_sync_l2l.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_sync_p2p.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_to_iop.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_apb_spi.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_apb_timer.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_apb_uart.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_apb_watchdog.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_apb_watchdog_defs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_apb_watchdog_frc.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_iop_gpio.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\CORTEXM3.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\CORTEXM3INTEGRATION.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\DAPDpApbDefs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\DAPDpApbIfClamp.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\DAPDpApbSync.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\DAPDpClamp0.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\DAPDpEnSync.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\DAPDpIMux.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\DAPDpSync.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\DAPJtagDpDefs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\DAPJtagDpProtocol.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\DAPSwDpApbIf.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\DAPSwDpDefs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\DAPSwDpProtocol.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\DAPSwDpSync.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\DAPSWJDP.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\DAPSwjDpDefs.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\DAPSwjWatcher.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\ddr3_1_4code.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\DDR3_define.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\ddr3_name.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\ddr3_to_ahb_top.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\DDR3_TOP.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\dtcm.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\Gowin_EMPU_M3_top.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\GowinAhbExt.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\GowinCM3AhbExt.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\GowinCM3AhbExtWrapper.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\gw_apb_i2c.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\gw_apb_int_wrapper.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\gw_apb_sd.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\gw_gpio.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\InputStage.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\itcm.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\m3_top.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\MatrixDecodeS0.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\MatrixDecodeS1.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\MatrixDecodeS2.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\OutputArb1.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\OutputArb2.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\OutputArb3.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\OutputStage1.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\OutputStage2.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\OutputStage3.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\p_sse050_interconnect_f0_ahb_to_apb.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\p_sse050_interconnect_f0_apb_slave_mux.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\Rtc.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\RtcApbif.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\RtcControl.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\RtcCounter.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\RtcInterrupt.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\RtcParams.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\RtcRevAnd.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\RtcSynctoPCLK.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\RtcUpdate.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\sse050_int_apb_decoder.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\sse050_integration_peripherals.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\sync_p2p.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GOWIN_EMPU_M3\data\triple_speed_mac_name.v C:\Users\liukai\Desktop\gowin_empu_m3\src\gowin_empu_m3\temp\gw_empu_m3\cm3_option_defs.v C:\Users\liukai\Desktop\gowin_empu_m3\src\gowin_empu_m3\temp\gw_empu_m3\ahb_option_defs.v C:\Users\liukai\Desktop\gowin_empu_m3\src\gowin_empu_m3\temp\gw_empu_m3\triple_speed_mac_param.v C:\Users\liukai\Desktop\gowin_empu_m3\src\gowin_empu_m3\temp\gw_empu_m3\triple_speed_mac_define.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9.03 (64-bit) |
| Part Number | GW2A-LV55PG484C8/I7 |
| Device | GW2A-55 |
| Device Version | C |
| Created Time | Wed May 15 17:00:56 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Gowin_EMPU_M3_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 8s, Elapsed time = 0h 0m 14s, Peak memory usage = 492.500MB Running netlist conversion: CPU time = 0h 0m 0.718s, Elapsed time = 0h 0m 0.71s, Peak memory usage = 492.500MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 492.500MB Optimizing Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 492.500MB Optimizing Phase 2: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 492.500MB Running inference: Inferring Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 492.500MB Inferring Phase 1: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.242s, Peak memory usage = 492.500MB Inferring Phase 2: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.236s, Peak memory usage = 492.500MB Inferring Phase 3: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 492.500MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 492.500MB Tech-Mapping Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 492.500MB Tech-Mapping Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 492.500MB Tech-Mapping Phase 3: CPU time = 0h 2m 1s, Elapsed time = 0h 2m 1s, Peak memory usage = 492.500MB Tech-Mapping Phase 4: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 492.500MB Generate output files: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 492.500MB |
| Total Time and Memory Usage | CPU time = 0h 2m 34s, Elapsed time = 0h 2m 40s, Peak memory usage = 492.500MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 44 |
| I/O Buf | 44 |
| IBUF | 6 |
| OBUF | 15 |
| IOBUF | 23 |
| Register | 5514 |
| DFF | 7 |
| DFFE | 74 |
| DFFR | 3 |
| DFFP | 32 |
| DFFPE | 160 |
| DFFC | 358 |
| DFFCE | 4871 |
| DFFNPE | 7 |
| DL | 1 |
| DLN | 1 |
| LUT | 23904 |
| LUT2 | 2161 |
| LUT3 | 5898 |
| LUT4 | 15845 |
| ALU | 1323 |
| ALU | 1323 |
| SSRAM | 20 |
| RAM16S4 | 4 |
| RAM16SDP4 | 16 |
| INV | 54 |
| INV | 54 |
| DSP | |
| MULT36X36 | 1 |
| BSRAM | 64 |
| SP | 32 |
| SDPB | 32 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 25401(23958 LUT, 1323 ALU, 20 RAM16) / 54720 | 47% |
| Register | 5514 / 41997 | 14% |
| --Register as Latch | 2 / 41997 | <1% |
| --Register as FF | 5512 / 41997 | 14% |
| BSRAM | 64 / 140 | 46% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| HCLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | HCLK_ibuf/I | ||
| JTAG_9 | Base | 10.000 | 100.0 | 0.000 | 5.000 | JTAG_9_ibuf/I | ||
| u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_s9/F |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | HCLK | 100.000(MHz) | 36.836(MHz) | 29 | TOP |
| 2 | JTAG_9 | 100.000(MHz) | 75.735(MHz) | 14 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -17.148 |
| Data Arrival Time | 27.473 |
| Data Required Time | 10.325 |
| From | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_rd_a_data_ex_2_s0 |
| To | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_0_s0 |
| Launch Clk | HCLK[R] |
| Latch Clk | HCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 5294 | HCLK_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_rd_a_data_ex_2_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 19 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_rd_a_data_ex_2_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/nxt_div_srt_init_ex_0_s6/I1 |
| 1.621 | 0.555 | tINS | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/nxt_div_srt_init_ex_0_s6/F |
| 2.095 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_25_s7/I0 |
| 2.612 | 0.517 | tINS | FF | 11 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_25_s7/F |
| 3.086 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s22/I1 |
| 3.641 | 0.555 | tINS | FF | 4 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s22/F |
| 4.115 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s11/I0 |
| 4.632 | 0.517 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s11/F |
| 5.106 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s6/I1 |
| 5.661 | 0.555 | tINS | FF | 62 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s6/F |
| 6.135 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_7_s5/I0 |
| 6.652 | 0.517 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_7_s5/F |
| 7.126 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_7_s4/I2 |
| 7.579 | 0.453 | tINS | FF | 4 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_7_s4/F |
| 8.053 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s2/I1 |
| 8.608 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s2/F |
| 9.082 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s1/I1 |
| 9.637 | 0.555 | tINS | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s1/F |
| 10.111 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s15/I2 |
| 10.564 | 0.453 | tINS | FF | 3 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s15/F |
| 11.038 | 0.474 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_7_s/I1 |
| 11.608 | 0.570 | tINS | FR | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_7_s/COUT |
| 11.608 | 0.000 | tNET | RR | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_8_s/CIN |
| 11.643 | 0.035 | tINS | RF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_8_s/COUT |
| 11.643 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_9_s/CIN |
| 11.678 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_9_s/COUT |
| 11.678 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_10_s/CIN |
| 11.714 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_10_s/COUT |
| 11.714 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_11_s/CIN |
| 11.749 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_11_s/COUT |
| 11.749 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_12_s/CIN |
| 11.784 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_12_s/COUT |
| 11.784 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_13_s/CIN |
| 11.819 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_13_s/COUT |
| 11.819 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_14_s/CIN |
| 11.854 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_14_s/COUT |
| 11.854 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_15_s/CIN |
| 11.890 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_15_s/COUT |
| 11.890 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_16_s/CIN |
| 11.925 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_16_s/COUT |
| 11.925 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_17_s/CIN |
| 11.960 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_17_s/COUT |
| 11.960 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_18_s/CIN |
| 11.995 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_18_s/COUT |
| 11.995 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_19_s/CIN |
| 12.030 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_19_s/COUT |
| 12.030 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_20_s/CIN |
| 12.066 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_20_s/COUT |
| 12.066 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_21_s/CIN |
| 12.101 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_21_s/COUT |
| 12.101 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_22_s/CIN |
| 12.136 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_22_s/COUT |
| 12.136 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_23_s/CIN |
| 12.171 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_23_s/COUT |
| 12.171 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_24_s/CIN |
| 12.206 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_24_s/COUT |
| 12.206 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_25_s/CIN |
| 12.242 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_25_s/COUT |
| 12.242 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_26_s/CIN |
| 12.277 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_26_s/COUT |
| 12.277 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_27_s/CIN |
| 12.312 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_27_s/COUT |
| 12.312 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_28_s/CIN |
| 12.347 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_28_s/COUT |
| 12.347 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_29_s/CIN |
| 12.382 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_29_s/COUT |
| 12.382 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s/CIN |
| 12.418 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s/COUT |
| 12.418 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_31_s/CIN |
| 12.888 | 0.470 | tINS | FF | 9 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_31_s/SUM |
| 13.362 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n311_s37/I2 |
| 13.815 | 0.453 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n311_s37/F |
| 14.289 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n311_s25/I1 |
| 14.844 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n311_s25/F |
| 15.318 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n311_s14/I1 |
| 15.873 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n311_s14/F |
| 16.347 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n311_s7/I2 |
| 16.800 | 0.453 | tINS | FF | 5 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n311_s7/F |
| 17.274 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n311_s2/I0 |
| 17.791 | 0.517 | tINS | FF | 10 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n311_s2/F |
| 18.265 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s22/I1 |
| 18.820 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s22/F |
| 19.294 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s9/I0 |
| 19.811 | 0.517 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s9/F |
| 20.285 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s2/I0 |
| 20.802 | 0.517 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s2/F |
| 21.276 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s/I2 |
| 21.729 | 0.453 | tINS | FF | 27 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s/F |
| 22.203 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_dec/instr_sp_wr_de_Z_0_s2/I1 |
| 22.758 | 0.555 | tINS | FF | 7 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_dec/instr_sp_wr_de_Z_0_s2/F |
| 23.232 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_0_s128/I1 |
| 23.787 | 0.555 | tINS | FF | 7 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_0_s128/F |
| 24.261 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_0_s121/I1 |
| 24.816 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_0_s121/F |
| 25.290 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_0_s153/I1 |
| 25.845 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_0_s153/F |
| 26.319 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_0_s151/I0 |
| 26.422 | 0.103 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_0_s151/O |
| 26.896 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_0_s113/I0 |
| 26.999 | 0.103 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_0_s113/O |
| 27.473 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | HCLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 5294 | HCLK_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_0_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 29 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 14.083, 51.941%; route: 12.798, 47.203%; tC2Q: 0.232, 0.856% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 2
Path Summary:| Slack | -17.148 |
| Data Arrival Time | 27.473 |
| Data Required Time | 10.325 |
| From | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_rd_a_data_ex_2_s0 |
| To | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_4_s0 |
| Launch Clk | HCLK[R] |
| Latch Clk | HCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 5294 | HCLK_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_rd_a_data_ex_2_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 19 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_rd_a_data_ex_2_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/nxt_div_srt_init_ex_0_s6/I1 |
| 1.621 | 0.555 | tINS | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/nxt_div_srt_init_ex_0_s6/F |
| 2.095 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_25_s7/I0 |
| 2.612 | 0.517 | tINS | FF | 11 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_25_s7/F |
| 3.086 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s22/I1 |
| 3.641 | 0.555 | tINS | FF | 4 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s22/F |
| 4.115 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s11/I0 |
| 4.632 | 0.517 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s11/F |
| 5.106 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s6/I1 |
| 5.661 | 0.555 | tINS | FF | 62 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s6/F |
| 6.135 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_7_s5/I0 |
| 6.652 | 0.517 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_7_s5/F |
| 7.126 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_7_s4/I2 |
| 7.579 | 0.453 | tINS | FF | 4 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_7_s4/F |
| 8.053 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s2/I1 |
| 8.608 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s2/F |
| 9.082 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s1/I1 |
| 9.637 | 0.555 | tINS | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s1/F |
| 10.111 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s15/I2 |
| 10.564 | 0.453 | tINS | FF | 3 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s15/F |
| 11.038 | 0.474 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_7_s/I1 |
| 11.608 | 0.570 | tINS | FR | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_7_s/COUT |
| 11.608 | 0.000 | tNET | RR | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_8_s/CIN |
| 11.643 | 0.035 | tINS | RF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_8_s/COUT |
| 11.643 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_9_s/CIN |
| 11.678 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_9_s/COUT |
| 11.678 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_10_s/CIN |
| 11.714 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_10_s/COUT |
| 11.714 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_11_s/CIN |
| 11.749 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_11_s/COUT |
| 11.749 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_12_s/CIN |
| 11.784 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_12_s/COUT |
| 11.784 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_13_s/CIN |
| 11.819 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_13_s/COUT |
| 11.819 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_14_s/CIN |
| 11.854 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_14_s/COUT |
| 11.854 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_15_s/CIN |
| 11.890 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_15_s/COUT |
| 11.890 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_16_s/CIN |
| 11.925 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_16_s/COUT |
| 11.925 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_17_s/CIN |
| 11.960 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_17_s/COUT |
| 11.960 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_18_s/CIN |
| 11.995 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_18_s/COUT |
| 11.995 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_19_s/CIN |
| 12.030 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_19_s/COUT |
| 12.030 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_20_s/CIN |
| 12.066 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_20_s/COUT |
| 12.066 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_21_s/CIN |
| 12.101 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_21_s/COUT |
| 12.101 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_22_s/CIN |
| 12.136 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_22_s/COUT |
| 12.136 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_23_s/CIN |
| 12.171 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_23_s/COUT |
| 12.171 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_24_s/CIN |
| 12.206 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_24_s/COUT |
| 12.206 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_25_s/CIN |
| 12.242 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_25_s/COUT |
| 12.242 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_26_s/CIN |
| 12.277 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_26_s/COUT |
| 12.277 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_27_s/CIN |
| 12.312 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_27_s/COUT |
| 12.312 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_28_s/CIN |
| 12.347 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_28_s/COUT |
| 12.347 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_29_s/CIN |
| 12.382 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_29_s/COUT |
| 12.382 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s/CIN |
| 12.418 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s/COUT |
| 12.418 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_31_s/CIN |
| 12.888 | 0.470 | tINS | FF | 9 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_31_s/SUM |
| 13.362 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n311_s37/I2 |
| 13.815 | 0.453 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n311_s37/F |
| 14.289 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n311_s25/I1 |
| 14.844 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n311_s25/F |
| 15.318 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n311_s14/I1 |
| 15.873 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n311_s14/F |
| 16.347 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n311_s7/I2 |
| 16.800 | 0.453 | tINS | FF | 5 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n311_s7/F |
| 17.274 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n311_s2/I0 |
| 17.791 | 0.517 | tINS | FF | 10 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n311_s2/F |
| 18.265 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s22/I1 |
| 18.820 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s22/F |
| 19.294 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s9/I0 |
| 19.811 | 0.517 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s9/F |
| 20.285 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s2/I0 |
| 20.802 | 0.517 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s2/F |
| 21.276 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s/I2 |
| 21.729 | 0.453 | tINS | FF | 27 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s/F |
| 22.203 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_dec/instr_sp_wr_de_Z_0_s2/I1 |
| 22.758 | 0.555 | tINS | FF | 7 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_dec/instr_sp_wr_de_Z_0_s2/F |
| 23.232 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_4_s126/I1 |
| 23.787 | 0.555 | tINS | FF | 6 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_4_s126/F |
| 24.261 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_4_s132/I1 |
| 24.816 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_4_s132/F |
| 25.290 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_4_s162/I1 |
| 25.845 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_4_s162/F |
| 26.319 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_4_s159/I0 |
| 26.422 | 0.103 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_4_s159/O |
| 26.896 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_4_s117/I1 |
| 26.999 | 0.103 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_4_s117/O |
| 27.473 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | HCLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 5294 | HCLK_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_4_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 29 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 14.083, 51.941%; route: 12.798, 47.203%; tC2Q: 0.232, 0.856% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 3
Path Summary:| Slack | -17.086 |
| Data Arrival Time | 27.411 |
| Data Required Time | 10.325 |
| From | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_rd_a_data_ex_2_s0 |
| To | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_pc_fwd_ex_26_s0 |
| Launch Clk | HCLK[R] |
| Latch Clk | HCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 5294 | HCLK_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_rd_a_data_ex_2_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 19 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_rd_a_data_ex_2_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/nxt_div_srt_init_ex_0_s6/I1 |
| 1.621 | 0.555 | tINS | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/nxt_div_srt_init_ex_0_s6/F |
| 2.095 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_25_s7/I0 |
| 2.612 | 0.517 | tINS | FF | 11 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_25_s7/F |
| 3.086 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s22/I1 |
| 3.641 | 0.555 | tINS | FF | 4 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s22/F |
| 4.115 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s11/I0 |
| 4.632 | 0.517 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s11/F |
| 5.106 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s6/I1 |
| 5.661 | 0.555 | tINS | FF | 62 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s6/F |
| 6.135 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_7_s5/I0 |
| 6.652 | 0.517 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_7_s5/F |
| 7.126 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_7_s4/I2 |
| 7.579 | 0.453 | tINS | FF | 4 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_7_s4/F |
| 8.053 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s2/I1 |
| 8.608 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s2/F |
| 9.082 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s1/I1 |
| 9.637 | 0.555 | tINS | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s1/F |
| 10.111 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s15/I2 |
| 10.564 | 0.453 | tINS | FF | 3 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s15/F |
| 11.038 | 0.474 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_7_s/I1 |
| 11.608 | 0.570 | tINS | FR | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_7_s/COUT |
| 11.608 | 0.000 | tNET | RR | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_8_s/CIN |
| 11.643 | 0.035 | tINS | RF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_8_s/COUT |
| 11.643 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_9_s/CIN |
| 11.678 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_9_s/COUT |
| 11.678 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_10_s/CIN |
| 11.714 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_10_s/COUT |
| 11.714 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_11_s/CIN |
| 11.749 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_11_s/COUT |
| 11.749 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_12_s/CIN |
| 11.784 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_12_s/COUT |
| 11.784 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_13_s/CIN |
| 11.819 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_13_s/COUT |
| 11.819 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_14_s/CIN |
| 11.854 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_14_s/COUT |
| 11.854 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_15_s/CIN |
| 11.890 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_15_s/COUT |
| 11.890 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_16_s/CIN |
| 11.925 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_16_s/COUT |
| 11.925 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_17_s/CIN |
| 11.960 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_17_s/COUT |
| 11.960 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_18_s/CIN |
| 11.995 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_18_s/COUT |
| 11.995 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_19_s/CIN |
| 12.030 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_19_s/COUT |
| 12.030 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_20_s/CIN |
| 12.066 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_20_s/COUT |
| 12.066 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_21_s/CIN |
| 12.101 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_21_s/COUT |
| 12.101 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_22_s/CIN |
| 12.136 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_22_s/COUT |
| 12.136 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_23_s/CIN |
| 12.171 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_23_s/COUT |
| 12.171 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_24_s/CIN |
| 12.206 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_24_s/COUT |
| 12.206 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_25_s/CIN |
| 12.242 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_25_s/COUT |
| 12.242 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_26_s/CIN |
| 12.277 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_26_s/COUT |
| 12.277 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_27_s/CIN |
| 12.312 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_27_s/COUT |
| 12.312 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_28_s/CIN |
| 12.347 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_28_s/COUT |
| 12.347 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_29_s/CIN |
| 12.382 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_29_s/COUT |
| 12.382 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s/CIN |
| 12.418 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s/COUT |
| 12.418 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_31_s/CIN |
| 12.453 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_31_s/COUT |
| 12.927 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/alu_cout_ex_Z_s0/I2 |
| 13.380 | 0.453 | tINS | FF | 3 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/alu_cout_ex_Z_s0/F |
| 13.854 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_cin_ex_s2/I2 |
| 14.307 | 0.453 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_cin_ex_s2/F |
| 14.781 | 0.474 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_0_s/CIN |
| 14.816 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_0_s/COUT |
| 14.816 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_1_s/CIN |
| 14.851 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_1_s/COUT |
| 14.851 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_2_s/CIN |
| 15.321 | 0.470 | tINS | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_2_s/SUM |
| 15.795 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s40/I0 |
| 16.312 | 0.517 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s40/F |
| 16.786 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s39/I2 |
| 17.239 | 0.453 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s39/F |
| 17.713 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s37/I2 |
| 18.166 | 0.453 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s37/F |
| 18.640 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s27/I2 |
| 19.093 | 0.453 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s27/F |
| 19.567 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s15/I3 |
| 19.938 | 0.371 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s15/F |
| 20.412 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s7/I2 |
| 20.865 | 0.453 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s7/F |
| 21.339 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s3/I1 |
| 21.894 | 0.555 | tINS | FF | 8 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s3/F |
| 22.368 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_25_s5/I1 |
| 22.923 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_25_s5/F |
| 23.397 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_25_s3/I2 |
| 23.850 | 0.453 | tINS | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_25_s3/F |
| 24.324 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_25_s1/I1 |
| 24.879 | 0.555 | tINS | FF | 7 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_25_s1/F |
| 25.353 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_26_s1/I1 |
| 25.908 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_26_s1/F |
| 26.382 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_26_s0/I1 |
| 26.937 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_26_s0/F |
| 27.411 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_pc_fwd_ex_26_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | HCLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 5294 | HCLK_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_pc_fwd_ex_26_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_pc_fwd_ex_26_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 31 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 14.021, 51.832%; route: 12.798, 47.310%; tC2Q: 0.232, 0.858% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 4
Path Summary:| Slack | -17.086 |
| Data Arrival Time | 27.411 |
| Data Required Time | 10.325 |
| From | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_rd_a_data_ex_2_s0 |
| To | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_pc_fwd_ex_29_s0 |
| Launch Clk | HCLK[R] |
| Latch Clk | HCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 5294 | HCLK_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_rd_a_data_ex_2_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 19 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_rd_a_data_ex_2_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/nxt_div_srt_init_ex_0_s6/I1 |
| 1.621 | 0.555 | tINS | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/nxt_div_srt_init_ex_0_s6/F |
| 2.095 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_25_s7/I0 |
| 2.612 | 0.517 | tINS | FF | 11 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_25_s7/F |
| 3.086 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s22/I1 |
| 3.641 | 0.555 | tINS | FF | 4 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s22/F |
| 4.115 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s11/I0 |
| 4.632 | 0.517 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s11/F |
| 5.106 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s6/I1 |
| 5.661 | 0.555 | tINS | FF | 62 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s6/F |
| 6.135 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_7_s5/I0 |
| 6.652 | 0.517 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_7_s5/F |
| 7.126 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_7_s4/I2 |
| 7.579 | 0.453 | tINS | FF | 4 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_7_s4/F |
| 8.053 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s2/I1 |
| 8.608 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s2/F |
| 9.082 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s1/I1 |
| 9.637 | 0.555 | tINS | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s1/F |
| 10.111 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s15/I2 |
| 10.564 | 0.453 | tINS | FF | 3 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s15/F |
| 11.038 | 0.474 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_7_s/I1 |
| 11.608 | 0.570 | tINS | FR | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_7_s/COUT |
| 11.608 | 0.000 | tNET | RR | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_8_s/CIN |
| 11.643 | 0.035 | tINS | RF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_8_s/COUT |
| 11.643 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_9_s/CIN |
| 11.678 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_9_s/COUT |
| 11.678 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_10_s/CIN |
| 11.714 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_10_s/COUT |
| 11.714 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_11_s/CIN |
| 11.749 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_11_s/COUT |
| 11.749 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_12_s/CIN |
| 11.784 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_12_s/COUT |
| 11.784 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_13_s/CIN |
| 11.819 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_13_s/COUT |
| 11.819 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_14_s/CIN |
| 11.854 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_14_s/COUT |
| 11.854 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_15_s/CIN |
| 11.890 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_15_s/COUT |
| 11.890 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_16_s/CIN |
| 11.925 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_16_s/COUT |
| 11.925 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_17_s/CIN |
| 11.960 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_17_s/COUT |
| 11.960 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_18_s/CIN |
| 11.995 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_18_s/COUT |
| 11.995 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_19_s/CIN |
| 12.030 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_19_s/COUT |
| 12.030 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_20_s/CIN |
| 12.066 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_20_s/COUT |
| 12.066 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_21_s/CIN |
| 12.101 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_21_s/COUT |
| 12.101 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_22_s/CIN |
| 12.136 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_22_s/COUT |
| 12.136 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_23_s/CIN |
| 12.171 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_23_s/COUT |
| 12.171 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_24_s/CIN |
| 12.206 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_24_s/COUT |
| 12.206 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_25_s/CIN |
| 12.242 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_25_s/COUT |
| 12.242 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_26_s/CIN |
| 12.277 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_26_s/COUT |
| 12.277 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_27_s/CIN |
| 12.312 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_27_s/COUT |
| 12.312 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_28_s/CIN |
| 12.347 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_28_s/COUT |
| 12.347 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_29_s/CIN |
| 12.382 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_29_s/COUT |
| 12.382 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s/CIN |
| 12.418 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s/COUT |
| 12.418 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_31_s/CIN |
| 12.453 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_31_s/COUT |
| 12.927 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/alu_cout_ex_Z_s0/I2 |
| 13.380 | 0.453 | tINS | FF | 3 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/alu_cout_ex_Z_s0/F |
| 13.854 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_cin_ex_s2/I2 |
| 14.307 | 0.453 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_cin_ex_s2/F |
| 14.781 | 0.474 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_0_s/CIN |
| 14.816 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_0_s/COUT |
| 14.816 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_1_s/CIN |
| 14.851 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_1_s/COUT |
| 14.851 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_2_s/CIN |
| 15.321 | 0.470 | tINS | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_2_s/SUM |
| 15.795 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s40/I0 |
| 16.312 | 0.517 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s40/F |
| 16.786 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s39/I2 |
| 17.239 | 0.453 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s39/F |
| 17.713 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s37/I2 |
| 18.166 | 0.453 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s37/F |
| 18.640 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s27/I2 |
| 19.093 | 0.453 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s27/F |
| 19.567 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s15/I3 |
| 19.938 | 0.371 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s15/F |
| 20.412 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s7/I2 |
| 20.865 | 0.453 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s7/F |
| 21.339 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s3/I1 |
| 21.894 | 0.555 | tINS | FF | 8 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s3/F |
| 22.368 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_25_s5/I1 |
| 22.923 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_25_s5/F |
| 23.397 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_25_s3/I2 |
| 23.850 | 0.453 | tINS | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_25_s3/F |
| 24.324 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_25_s1/I1 |
| 24.879 | 0.555 | tINS | FF | 7 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_25_s1/F |
| 25.353 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_29_s1/I1 |
| 25.908 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_29_s1/F |
| 26.382 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_29_s0/I1 |
| 26.937 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_29_s0/F |
| 27.411 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_pc_fwd_ex_29_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | HCLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 5294 | HCLK_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_pc_fwd_ex_29_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_pc_fwd_ex_29_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 31 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 14.021, 51.832%; route: 12.798, 47.310%; tC2Q: 0.232, 0.858% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 5
Path Summary:| Slack | -17.086 |
| Data Arrival Time | 27.411 |
| Data Required Time | 10.325 |
| From | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_rd_a_data_ex_2_s0 |
| To | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_pc_fwd_ex_31_s0 |
| Launch Clk | HCLK[R] |
| Latch Clk | HCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 5294 | HCLK_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_rd_a_data_ex_2_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 19 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_rd_a_data_ex_2_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/nxt_div_srt_init_ex_0_s6/I1 |
| 1.621 | 0.555 | tINS | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/nxt_div_srt_init_ex_0_s6/F |
| 2.095 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_25_s7/I0 |
| 2.612 | 0.517 | tINS | FF | 11 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_25_s7/F |
| 3.086 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s22/I1 |
| 3.641 | 0.555 | tINS | FF | 4 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s22/F |
| 4.115 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s11/I0 |
| 4.632 | 0.517 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s11/F |
| 5.106 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s6/I1 |
| 5.661 | 0.555 | tINS | FF | 62 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s6/F |
| 6.135 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_7_s5/I0 |
| 6.652 | 0.517 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_7_s5/F |
| 7.126 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_7_s4/I2 |
| 7.579 | 0.453 | tINS | FF | 4 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_7_s4/F |
| 8.053 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s2/I1 |
| 8.608 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s2/F |
| 9.082 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s1/I1 |
| 9.637 | 0.555 | tINS | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s1/F |
| 10.111 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s15/I2 |
| 10.564 | 0.453 | tINS | FF | 3 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_7_s15/F |
| 11.038 | 0.474 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_7_s/I1 |
| 11.608 | 0.570 | tINS | FR | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_7_s/COUT |
| 11.608 | 0.000 | tNET | RR | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_8_s/CIN |
| 11.643 | 0.035 | tINS | RF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_8_s/COUT |
| 11.643 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_9_s/CIN |
| 11.678 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_9_s/COUT |
| 11.678 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_10_s/CIN |
| 11.714 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_10_s/COUT |
| 11.714 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_11_s/CIN |
| 11.749 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_11_s/COUT |
| 11.749 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_12_s/CIN |
| 11.784 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_12_s/COUT |
| 11.784 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_13_s/CIN |
| 11.819 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_13_s/COUT |
| 11.819 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_14_s/CIN |
| 11.854 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_14_s/COUT |
| 11.854 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_15_s/CIN |
| 11.890 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_15_s/COUT |
| 11.890 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_16_s/CIN |
| 11.925 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_16_s/COUT |
| 11.925 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_17_s/CIN |
| 11.960 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_17_s/COUT |
| 11.960 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_18_s/CIN |
| 11.995 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_18_s/COUT |
| 11.995 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_19_s/CIN |
| 12.030 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_19_s/COUT |
| 12.030 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_20_s/CIN |
| 12.066 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_20_s/COUT |
| 12.066 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_21_s/CIN |
| 12.101 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_21_s/COUT |
| 12.101 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_22_s/CIN |
| 12.136 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_22_s/COUT |
| 12.136 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_23_s/CIN |
| 12.171 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_23_s/COUT |
| 12.171 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_24_s/CIN |
| 12.206 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_24_s/COUT |
| 12.206 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_25_s/CIN |
| 12.242 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_25_s/COUT |
| 12.242 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_26_s/CIN |
| 12.277 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_26_s/COUT |
| 12.277 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_27_s/CIN |
| 12.312 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_27_s/COUT |
| 12.312 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_28_s/CIN |
| 12.347 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_28_s/COUT |
| 12.347 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_29_s/CIN |
| 12.382 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_29_s/COUT |
| 12.382 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s/CIN |
| 12.418 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s/COUT |
| 12.418 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_31_s/CIN |
| 12.453 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_31_s/COUT |
| 12.927 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/alu_cout_ex_Z_s0/I2 |
| 13.380 | 0.453 | tINS | FF | 3 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/alu_cout_ex_Z_s0/F |
| 13.854 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_cin_ex_s2/I2 |
| 14.307 | 0.453 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_cin_ex_s2/F |
| 14.781 | 0.474 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_0_s/CIN |
| 14.816 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_0_s/COUT |
| 14.816 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_1_s/CIN |
| 14.851 | 0.035 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_1_s/COUT |
| 14.851 | 0.000 | tNET | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_2_s/CIN |
| 15.321 | 0.470 | tINS | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_2_s/SUM |
| 15.795 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s40/I0 |
| 16.312 | 0.517 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s40/F |
| 16.786 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s39/I2 |
| 17.239 | 0.453 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s39/F |
| 17.713 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s37/I2 |
| 18.166 | 0.453 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s37/F |
| 18.640 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s27/I2 |
| 19.093 | 0.453 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s27/F |
| 19.567 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s15/I3 |
| 19.938 | 0.371 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s15/F |
| 20.412 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s7/I2 |
| 20.865 | 0.453 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s7/F |
| 21.339 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s3/I1 |
| 21.894 | 0.555 | tINS | FF | 8 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/wr1_data_18_s3/F |
| 22.368 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_25_s5/I1 |
| 22.923 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_25_s5/F |
| 23.397 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_25_s3/I2 |
| 23.850 | 0.453 | tINS | FF | 2 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_25_s3/F |
| 24.324 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_25_s1/I1 |
| 24.879 | 0.555 | tINS | FF | 7 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_25_s1/F |
| 25.353 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_31_s1/I1 |
| 25.908 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_31_s1/F |
| 26.382 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_31_s0/I1 |
| 26.937 | 0.555 | tINS | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_31_s0/F |
| 27.411 | 0.474 | tNET | FF | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_pc_fwd_ex_31_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | HCLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 5294 | HCLK_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_pc_fwd_ex_31_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_pc_fwd_ex_31_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 31 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 14.021, 51.832%; route: 12.798, 47.310%; tC2Q: 0.232, 0.858% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |