Timing Messages

Report Title	Timing Analysis Report
Design File	D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj9k_usb2_loopback_speed\prj9k_usb2_loopback_speed_single_lvds\project\impl\gwsynthesis\gowin_usb_refdesign.vg
Physical Constraints File	D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj9k_usb2_loopback_speed\prj9k_usb2_loopback_speed_single_lvds\project\src\usb_ref.cst
Timing Constraint File	D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj9k_usb2_loopback_speed\prj9k_usb2_loopback_speed_single_lvds\project\src\gowin_usb_refdesign.sdc
Tool Version	V1.9.12 (64-bit)
Part Number	GW1N-LV9LQ144C7/I6
Device	GW1N-9
Device Version	C
Created Time	Wed Nov 5 10:36:12 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C C7/I6
Hold Delay Model	Fast 1.26V 0C C7/I6
Numbers of Paths Analyzed	4681
Numbers of Endpoints Analyzed	4537
Numbers of Falling Endpoints	4
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Fall	Source	Master	Objects
1	clk60	Base	16.667	59.999	8.334			PHY_CLKOUT
2	clk120	Base	8.333	120.005	4.167			u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/sclk
3	CLK_IN	Base	83.333	12.000	41.667			CLK_IN_ibuf/I
4	u_pll/rpll_inst/CLKOUT.default_gen_clk	Generated	2.083	480.000	1.042	CLK_IN_ibuf/I	CLK_IN	u_pll/rpll_inst/CLKOUT
5	u_pll/rpll_inst/CLKOUTP.default_gen_clk	Generated	2.083	480.000	1.042	CLK_IN_ibuf/I	CLK_IN	u_pll/rpll_inst/CLKOUTP
6	u_pll/rpll_inst/CLKOUTD3.default_gen_clk	Generated	6.250	160.000	3.125	CLK_IN_ibuf/I	CLK_IN	u_pll/rpll_inst/CLKOUTD3

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk60	59.999(MHz)	60.138(MHz)	18	TOP
2	clk120	120.005(MHz)	121.684(MHz)	8	TOP

No timing paths to get frequency of CLK_IN!

No timing paths to get frequency of u_pll/rpll_inst/CLKOUT.default_gen_clk!

No timing paths to get frequency of u_pll/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of u_pll/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk60	Setup	0.000	0
clk60	Hold	0.000	0
clk120	Setup	0.000	0
clk120	Hold	0.000	0
CLK_IN	Setup	0.000	0
CLK_IN	Hold	0.000	0
u_pll/rpll_inst/CLKOUT.default_gen_clk	Setup	0.000	0
u_pll/rpll_inst/CLKOUT.default_gen_clk	Hold	0.000	0
u_pll/rpll_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
u_pll/rpll_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
u_pll/rpll_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
u_pll/rpll_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 100 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Data Delay
1	0.039	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s1/D	clk60:[R]	clk60:[R]	16.667	16.332
2	0.074	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_16_s1/D	clk60:[R]	clk60:[R]	16.667	16.297
3	0.113	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Full_s0/D	clk60:[R]	clk60:[R]	16.667	16.257
4	0.115	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/Q4	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1/D	clk120:[R]	clk120:[R]	8.333	7.922
5	0.131	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_empty_s0/D	clk120:[R]	clk120:[R]	8.333	7.905
6	0.168	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_11_s1/D	clk60:[R]	clk60:[R]	16.667	16.203
7	0.177	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_15_s1/D	clk60:[R]	clk60:[R]	16.667	16.193
8	0.181	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/Q5	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s1/D	clk120:[R]	clk120:[R]	8.333	7.856
9	0.194	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DO[1]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_rxgoodpacket_s0/D	clk60:[R]	clk60:[R]	16.667	16.176
10	0.278	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_9_s1/D	clk60:[R]	clk60:[R]	16.667	16.092
11	0.285	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_4_s0/D	clk60:[R]	clk60:[R]	16.667	16.086
12	0.285	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_5_s0/D	clk60:[R]	clk60:[R]	16.667	16.086
13	0.361	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_9_s2/D	clk60:[R]	clk60:[R]	16.667	16.010
14	0.382	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_8_s1/D	clk60:[R]	clk60:[R]	16.667	15.988
15	0.399	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_0_s1/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_1_s1/D	clk120:[R]	clk120:[R]	8.333	7.637
16	0.490	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0/D	clk120:[R]	clk120:[R]	8.333	7.546
17	0.494	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_3_s1/D	clk60:[R]	clk60:[R]	16.667	15.877
18	0.497	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_2_s1/D	clk60:[R]	clk60:[R]	16.667	15.873
19	0.506	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_2_s0/D	clk60:[R]	clk60:[R]	16.667	15.865
20	0.559	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_0_s1/D	clk120:[R]	clk120:[R]	8.333	7.477
21	0.612	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_12_s1/D	clk60:[R]	clk60:[R]	16.667	15.759
22	0.628	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_1_s1/D	clk60:[R]	clk60:[R]	16.667	15.742
23	0.635	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_5_s1/D	clk120:[R]	clk120:[R]	8.333	7.401
24	0.641	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_10_s1/D	clk60:[R]	clk60:[R]	16.667	15.730
25	0.694	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_14_s1/D	clk60:[R]	clk60:[R]	16.667	15.677
26	0.727	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_7_s1/D	clk60:[R]	clk60:[R]	16.667	15.644
27	0.759	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_7_s1/D	clk120:[R]	clk120:[R]	8.333	7.278
28	0.771	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DO[2]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_dataout_6_s0/D	clk60:[R]	clk60:[R]	16.667	15.600
29	0.773	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_8_s4/D	clk60:[R]	clk60:[R]	16.667	15.598
30	0.793	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_3_s0/D	clk60:[R]	clk60:[R]	16.667	15.578
31	0.893	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_7_s0/CE	clk60:[R]	clk60:[R]	16.667	15.742
32	0.960	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/Q5	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/dru_locked_s2/D	clk120:[R]	clk120:[R]	8.333	7.077
33	0.966	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/data_out_en_s0/D	clk120:[R]	clk120:[R]	8.333	7.071
34	0.978	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DO[1]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/crc16_buf_0_s1/D	clk60:[R]	clk60:[R]	16.667	15.392
35	0.978	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DO[1]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/crc16_buf_1_s1/D	clk60:[R]	clk60:[R]	16.667	15.392
36	0.978	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DO[1]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/crc16_buf_15_s1/D	clk60:[R]	clk60:[R]	16.667	15.392
37	0.985	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DO[2]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_6_s0/D	clk60:[R]	clk60:[R]	16.667	15.386
38	0.996	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_4_s1/D	clk60:[R]	clk60:[R]	16.667	15.375
39	1.003	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_TXVALID_s1/CE	clk60:[R]	clk60:[R]	16.667	15.632
40	1.006	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_4_s1/D	clk120:[R]	clk120:[R]	8.333	7.031
41	1.015	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/D	clk60:[R]	clk60:[R]	16.667	15.355
42	1.017	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_13_s1/D	clk60:[R]	clk60:[R]	16.667	15.353
43	1.041	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_6_s1/D	clk60:[R]	clk60:[R]	16.667	15.329
44	1.052	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/Q5	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s1/CE	clk120:[R]	clk120:[R]	8.333	7.249
45	1.075	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DO[1]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_dataout_5_s0/D	clk60:[R]	clk60:[R]	16.667	15.296
46	1.076	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/Q5	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1/CE	clk120:[R]	clk120:[R]	8.333	7.225
47	1.113	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_1_s0/D	clk60:[R]	clk60:[R]	16.667	15.257
48	1.204	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_0_s1/D	clk60:[R]	clk60:[R]	16.667	15.167
49	1.210	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_0_s0/D	clk60:[R]	clk60:[R]	16.667	15.160
50	1.379	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_2_s1/D	clk120:[R]	clk120:[R]	8.333	6.658
51	1.402	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_4_s0/CE	clk60:[R]	clk60:[R]	16.667	15.233
52	1.402	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_6_s0/CE	clk60:[R]	clk60:[R]	16.667	15.233
53	1.405	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_1_s0/CE	clk60:[R]	clk60:[R]	16.667	15.229
54	1.437	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q1	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_1_s0/RESET	clk120:[R]	clk120:[R]	8.333	6.864
55	1.437	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q1	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_9_s0/RESET	clk120:[R]	clk120:[R]	8.333	6.864
56	1.437	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_0_s0/CE	clk60:[R]	clk60:[R]	16.667	15.197
57	1.502	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/descrom_raddr_1_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_dataout_7_s0/D	clk60:[R]	clk60:[R]	16.667	14.868
58	1.533	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_3_s0/CE	clk60:[R]	clk60:[R]	16.667	15.102
59	1.535	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_1_s1/D	clk60:[R]	clk60:[R]	16.667	14.836
60	1.537	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_2_s0/CE	clk60:[R]	clk60:[R]	16.667	15.098
61	1.602	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/descrom_raddr_1_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_7_s0/D	clk60:[R]	clk60:[R]	16.667	14.768
62	1.662	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_val_s1/CE	clk60:[R]	clk60:[R]	16.667	14.973
63	1.690	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_7_s1/D	clk60:[R]	clk60:[R]	16.667	14.680
64	1.697	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_state_0_s1/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_5_s12/CE	clk60:[R]	clk60:[R]	16.667	14.938
65	1.701	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DO[1]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_5_s0/D	clk60:[R]	clk60:[R]	16.667	14.670
66	1.703	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_3_s1/D	clk120:[R]	clk120:[R]	8.333	6.334
67	1.704	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_state_0_s1/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_2_s12/CE	clk60:[R]	clk60:[R]	16.667	14.931
68	1.710	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q1	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_5_s0/RESET	clk120:[R]	clk120:[R]	8.333	6.591
69	1.710	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q1	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_13_s0/RESET	clk120:[R]	clk120:[R]	8.333	6.591
70	1.711	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q1	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_3_s0/RESET	clk120:[R]	clk120:[R]	8.333	6.590
71	1.711	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q1	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_6_s0/RESET	clk120:[R]	clk120:[R]	8.333	6.590
72	1.711	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q1	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_7_s0/RESET	clk120:[R]	clk120:[R]	8.333	6.590
73	1.723	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_6_s1/D	clk120:[R]	clk120:[R]	8.333	6.313
74	1.738	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Full_s0/D	clk120:[R]	clk120:[R]	8.333	6.299
75	1.743	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_6_s1/CE	clk60:[R]	clk60:[R]	16.667	14.892
76	1.743	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_7_s1/CE	clk60:[R]	clk60:[R]	16.667	14.892
77	1.743	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_8_s1/CE	clk60:[R]	clk60:[R]	16.667	14.892
78	1.743	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_9_s1/CE	clk60:[R]	clk60:[R]	16.667	14.892
79	1.779	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_6_s1/D	clk60:[R]	clk60:[R]	16.667	14.592
80	1.819	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_2_s1/CE	clk60:[R]	clk60:[R]	16.667	14.816
81	1.819	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_6_s1/CE	clk60:[R]	clk60:[R]	16.667	14.816
82	1.820	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wptr_3_s0/D	clk60:[R]	clk60:[R]	16.667	14.550
83	1.825	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbin_3_s0/D	clk60:[R]	clk60:[R]	16.667	14.545
84	1.836	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s1/D	clk60:[R]	clk60:[R]	16.667	14.535
85	1.862	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_3_s6/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_0_s0/CE	clk60:[R]	clk60:[R]	16.667	14.773
86	1.870	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DO[2]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/crc16_buf_3_s1/D	clk60:[R]	clk60:[R]	16.667	14.500
87	1.876	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wptr_4_s0/D	clk60:[R]	clk60:[R]	16.667	14.495
88	1.964	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_8_s1/CE	clk60:[R]	clk60:[R]	16.667	14.671
89	1.964	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_13_s1/CE	clk60:[R]	clk60:[R]	16.667	14.671
90	1.971	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_9_s1/CE	clk60:[R]	clk60:[R]	16.667	14.664
91	1.976	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_state_0_s1/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_0_s12/CE	clk60:[R]	clk60:[R]	16.667	14.659
92	1.985	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q1	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_2_s0/RESET	clk120:[R]	clk120:[R]	8.333	6.316
93	1.985	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q1	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_11_s0/RESET	clk120:[R]	clk120:[R]	8.333	6.316
94	2.002	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wptr_0_s0/D	clk60:[R]	clk60:[R]	16.667	14.369
95	2.018	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_10_s1/CE	clk60:[R]	clk60:[R]	16.667	14.616
96	2.018	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_11_s1/CE	clk60:[R]	clk60:[R]	16.667	14.616
97	2.062	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_txready_s0/D	clk60:[R]	clk60:[R]	16.667	14.309
98	2.081	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_5_s0/CE	clk60:[R]	clk60:[R]	16.667	14.553
99	2.095	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_1_s1/CE	clk60:[R]	clk60:[R]	16.667	14.540
100	2.095	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_3_s1/CE	clk60:[R]	clk60:[R]	16.667	14.540

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Data Delay
1	0.305	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_next_8_s0/Q	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/ADB[10]	clk60:[R]	clk60:[R]	0.424
2	0.326	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_next_9_s0/Q	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/ADB[11]	clk60:[R]	clk60:[R]	0.444
3	0.357	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_5_s0/Q	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_1_s/DI[1]	clk60:[R]	clk60:[R]	0.421
4	0.357	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_0_s0/Q	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/DI[0]	clk60:[R]	clk60:[R]	0.421
5	0.380	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_1_s0/Q	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/DI[1]	clk60:[R]	clk60:[R]	0.444
6	0.414	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_pktval_s0/Q	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/pkg_wp_6_s0/CE	clk60:[R]	clk60:[R]	0.423
7	0.414	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_pktval_s0/Q	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/pkg_wp_10_s0/CE	clk60:[R]	clk60:[R]	0.423
8	0.415	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/E4_0_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/DVE_1_s0/RESET	clk120:[R]	clk120:[R]	0.424
9	0.436	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/E4_2_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/DVE_0_s0/RESET	clk120:[R]	clk120:[R]	0.445
10	0.524	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_q_s4/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_q_s4/D	clk60:[R]	clk60:[R]	0.524
11	0.524	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/ones_count_q_0_s1/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/ones_count_q_0_s1/D	clk60:[R]	clk60:[R]	0.524
12	0.524	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/ones_count_q_1_s1/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/ones_count_q_1_s1/D	clk60:[R]	clk60:[R]	0.524
13	0.524	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/sample_cnt_q_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/sample_cnt_q_1_s0/D	clk60:[R]	clk60:[R]	0.524
14	0.524	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/sample_cnt_q_5_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/sample_cnt_q_5_s0/D	clk60:[R]	clk60:[R]	0.524
15	0.524	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_3_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_3_s0/D	clk60:[R]	clk60:[R]	0.524
16	0.524	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_9_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_9_s0/D	clk60:[R]	clk60:[R]	0.524
17	0.524	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/rx_en_s2/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/rx_en_s2/D	clk120:[R]	clk120:[R]	0.524
18	0.524	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/q_tx_cnt_7_s1/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/q_tx_cnt_7_s1/D	clk60:[R]	clk60:[R]	0.524
19	0.524	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/se0_det_counter_11_s3/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/se0_det_counter_11_s3/D	clk60:[R]	clk60:[R]	0.524
20	0.524	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/se0_det_counter_2_s1/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/se0_det_counter_2_s1/D	clk60:[R]	clk60:[R]	0.524
21	0.524	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_interface_set_s6/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_interface_set_s6/D	clk60:[R]	clk60:[R]	0.524
22	0.524	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_1_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_1_s0/D	clk60:[R]	clk60:[R]	0.524
23	0.524	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_4_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_4_s0/D	clk60:[R]	clk60:[R]	0.524
24	0.524	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_6_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_6_s0/D	clk60:[R]	clk60:[R]	0.524
25	0.524	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0/D	clk60:[R]	clk60:[R]	0.524

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.384	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/RESETB	clk120:[F]	clk120:[R]	4.166	0.011	3.618
2	0.490	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_2_s0/CLEAR	clk120:[F]	clk120:[R]	4.166	0.011	3.633
3	0.490	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_3_s0/CLEAR	clk120:[F]	clk120:[R]	4.166	0.011	3.633
4	0.490	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_4_s0/CLEAR	clk120:[F]	clk120:[R]	4.166	0.011	3.633
5	0.490	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_1_s0/CLEAR	clk120:[F]	clk120:[R]	4.166	0.011	3.633
6	0.490	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_2_s0/CLEAR	clk120:[F]	clk120:[R]	4.166	0.011	3.633
7	0.497	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0/PRESET	clk120:[F]	clk120:[R]	4.166	0.011	3.626
8	0.497	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_3_s0/CLEAR	clk120:[F]	clk120:[R]	4.166	0.011	3.626
9	0.497	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_0_s0/CLEAR	clk120:[F]	clk120:[R]	4.166	0.011	3.626
10	0.497	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_1_s0/CLEAR	clk120:[F]	clk120:[R]	4.166	0.011	3.626
11	0.497	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_5_s0/CLEAR	clk120:[F]	clk120:[R]	4.166	0.011	3.626
12	0.497	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Full_s0/CLEAR	clk120:[F]	clk120:[R]	4.166	0.011	3.626
13	0.497	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_0_s0/CLEAR	clk120:[F]	clk120:[R]	4.166	0.011	3.626
14	0.497	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_1_s0/CLEAR	clk120:[F]	clk120:[R]	4.166	0.011	3.626
15	0.497	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_2_s0/CLEAR	clk120:[F]	clk120:[R]	4.166	0.011	3.626
16	0.497	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_0_s0/CLEAR	clk120:[F]	clk120:[R]	4.166	0.011	3.626
17	0.497	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_4_s0/CLEAR	clk120:[F]	clk120:[R]	4.166	0.011	3.626
18	0.497	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_5_s0/CLEAR	clk120:[F]	clk120:[R]	4.166	0.011	3.626
19	0.497	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_1_s0/CLEAR	clk120:[F]	clk120:[R]	4.166	0.011	3.626
20	0.497	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_5_s0/CLEAR	clk120:[F]	clk120:[R]	4.166	0.011	3.626
21	0.497	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_0_s0/CLEAR	clk120:[F]	clk120:[R]	4.166	0.011	3.626
22	0.497	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_3_s0/CLEAR	clk120:[F]	clk120:[R]	4.166	0.011	3.626
23	0.497	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_4_s0/CLEAR	clk120:[F]	clk120:[R]	4.166	0.011	3.626
24	0.504	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_0_s0/CLEAR	clk120:[F]	clk120:[R]	4.166	0.011	3.618
25	0.504	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_1_s0/CLEAR	clk120:[F]	clk120:[R]	4.166	0.011	3.618

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Data Delay
1	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/Empty_s0/PRESET	clk60:[R]	clk60:[R]	1.353
2	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/AlmostFull_s0/CLEAR	clk60:[R]	clk60:[R]	1.353
3	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/Full_s0/CLEAR	clk60:[R]	clk60:[R]	1.353
4	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_0_s0/CLEAR	clk60:[R]	clk60:[R]	1.353
5	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_1_s0/CLEAR	clk60:[R]	clk60:[R]	1.353
6	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_2_s0/CLEAR	clk60:[R]	clk60:[R]	1.353
7	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_3_s0/CLEAR	clk60:[R]	clk60:[R]	1.353
8	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_4_s0/CLEAR	clk60:[R]	clk60:[R]	1.353
9	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_5_s0/CLEAR	clk60:[R]	clk60:[R]	1.353
10	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_0_s0/CLEAR	clk60:[R]	clk60:[R]	1.353
11	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_1_s0/CLEAR	clk60:[R]	clk60:[R]	1.353
12	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_2_s0/CLEAR	clk60:[R]	clk60:[R]	1.353
13	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_3_s0/CLEAR	clk60:[R]	clk60:[R]	1.353
14	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_4_s0/CLEAR	clk60:[R]	clk60:[R]	1.353
15	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_5_s0/CLEAR	clk60:[R]	clk60:[R]	1.353
16	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_6_s0/CLEAR	clk60:[R]	clk60:[R]	1.353
17	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_0_s0/CLEAR	clk60:[R]	clk60:[R]	1.353
18	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_1_s0/CLEAR	clk60:[R]	clk60:[R]	1.353
19	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_2_s0/CLEAR	clk60:[R]	clk60:[R]	1.353
20	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_3_s0/CLEAR	clk60:[R]	clk60:[R]	1.353
21	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_4_s0/CLEAR	clk60:[R]	clk60:[R]	1.353
22	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_5_s0/CLEAR	clk60:[R]	clk60:[R]	1.353
23	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_0_s0/CLEAR	clk60:[R]	clk60:[R]	1.353
24	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_1_s0/CLEAR	clk60:[R]	clk60:[R]	1.353
25	1.344	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_2_s0/CLEAR	clk60:[R]	clk60:[R]	1.353

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.185	4.111	0.926	Low Pulse Width	clk120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_2_s0
2	3.185	4.111	0.926	Low Pulse Width	clk120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/data_out_0_s0
3	3.185	4.111	0.926	Low Pulse Width	clk120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_3_s0
4	3.185	4.111	0.926	Low Pulse Width	clk120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_2_s0
5	3.185	4.111	0.926	Low Pulse Width	clk120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_1_s0
6	3.185	4.111	0.926	Low Pulse Width	clk120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_0_s0
7	3.185	4.111	0.926	Low Pulse Width	clk120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_1_s0
8	3.185	4.111	0.926	Low Pulse Width	clk120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_2_s0
9	3.185	4.111	0.926	Low Pulse Width	clk120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s
10	3.185	4.111	0.926	Low Pulse Width	clk120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_0_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 100 -max_common_paths 1

Path1

Path Summary:

Slack	0.039
Data Arrival Time	16.513
Data Required Time	16.551
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/CLK
0.520	0.340	tC2Q	RF	77	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q
1.860	1.340	tNET	FF	1	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I1
2.469	0.609	tINS	FF	5	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
2.481	0.012	tNET	FF	1	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
3.268	0.786	tINS	FR	7	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
3.581	0.313	tNET	RR	1	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
4.045	0.464	tINS	RF	4	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
4.057	0.012	tNET	FF	1	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
4.871	0.814	tINS	FF	5	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
5.238	0.366	tNET	FF	1	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
5.832	0.594	tINS	FR	2	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
6.145	0.313	tNET	RR	1	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
6.609	0.464	tINS	RF	10	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
7.229	0.620	tNET	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
7.693	0.464	tINS	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
8.302	0.608	tNET	FF	2	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
8.709	0.408	tINS	FR	1	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
8.709	0.000	tNET	RR	2	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
8.751	0.042	tINS	RF	1	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
8.751	0.000	tNET	FF	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
9.143	0.391	tINS	FR	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/SUM
9.454	0.312	tNET	RR	1	R13C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s9/I1
9.918	0.464	tINS	RF	6	R13C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s9/F
10.522	0.603	tNET	FF	1	R14C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s6/I3
10.986	0.464	tINS	FF	4	R14C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s6/F
11.602	0.617	tNET	FF	1	R13C11[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n925_s2/I1
12.066	0.464	tINS	FF	18	R13C11[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n925_s2/F
12.678	0.612	tNET	FF	1	R15C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1112_s8/I2
13.142	0.464	tINS	FF	1	R15C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1112_s8/F
13.146	0.004	tNET	FF	1	R15C10[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1112_s6/I2
13.960	0.814	tINS	FF	1	R15C10[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1112_s6/F
14.209	0.249	tNET	FF	1	R15C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1112_s4/I1
14.974	0.765	tINS	FF	1	R15C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1112_s4/F
14.978	0.004	tNET	FF	1	R15C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1112_s2/I0
15.738	0.760	tINS	FR	1	R15C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1112_s2/F
16.049	0.310	tNET	RR	1	R16C10[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1112_s1/I1
16.513	0.464	tINS	RF	1	R16C10[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1112_s1/F
16.513	0.000	tNET	FF	1	R16C10[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R16C10[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s1/CLK
16.551	-0.296	tSu		1	R16C10[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	18
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 9.695, 59.364%; route: 6.297, 38.557%; tC2Q: 0.340, 2.080%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path2

Path Summary:

Slack	0.074
Data Arrival Time	16.478
Data Required Time	16.551
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_16_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/CLK
0.520	0.340	tC2Q	RF	77	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q
1.860	1.340	tNET	FF	1	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I1
2.469	0.609	tINS	FF	5	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
2.481	0.012	tNET	FF	1	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
3.268	0.786	tINS	FR	7	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
3.581	0.313	tNET	RR	1	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
4.045	0.464	tINS	RF	4	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
4.057	0.012	tNET	FF	1	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
4.871	0.814	tINS	FF	5	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
5.238	0.366	tNET	FF	1	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
5.832	0.594	tINS	FR	2	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
6.145	0.313	tNET	RR	1	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
6.609	0.464	tINS	RF	10	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
7.229	0.620	tNET	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
7.693	0.464	tINS	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
8.302	0.608	tNET	FF	2	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
8.709	0.408	tINS	FR	1	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
8.709	0.000	tNET	RR	2	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
8.751	0.042	tINS	RF	1	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
8.751	0.000	tNET	FF	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
8.794	0.042	tINS	FF	1	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
8.794	0.000	tNET	FF	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
9.185	0.391	tINS	FR	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
9.498	0.313	tNET	RR	1	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
10.313	0.814	tINS	RF	9	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
10.691	0.379	tNET	FF	1	R13C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/I0
11.506	0.814	tINS	FF	22	R13C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/F
13.712	2.207	tNET	FF	1	R15C10[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1113_s3/I2
14.321	0.609	tINS	FF	1	R15C10[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1113_s3/F
14.917	0.596	tNET	FF	1	R15C12[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1113_s2/I0
15.704	0.786	tINS	FR	1	R15C12[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1113_s2/F
16.014	0.310	tNET	RR	1	R16C12[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1113_s1/I0
16.478	0.464	tINS	RF	1	R16C12[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1113_s1/F
16.478	0.000	tNET	FF	1	R16C12[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_16_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R16C12[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_16_s1/CLK
16.551	-0.296	tSu		1	R16C12[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_16_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	15
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 8.567, 52.566%; route: 7.391, 45.350%; tC2Q: 0.340, 2.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path3

Path Summary:

Slack	0.113
Data Arrival Time	16.438
Data Required Time	16.551
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Full_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.914	0.983	tNET	FF	1	R7C15[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_opmode_o_d_1_s/I2
6.728	0.814	tINS	FF	12	R7C15[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_opmode_o_d_1_s/F
8.783	2.055	tNET	FF	1	R4C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/fifo_wr_data_7_s1/I1
9.247	0.464	tINS	FF	17	R4C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/fifo_wr_data_7_s1/F
10.972	1.726	tNET	FF	1	R7C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n24_s1/I3
11.581	0.609	tINS	FF	7	R7C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n24_s1/F
12.210	0.629	tNET	FF	1	R8C6[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbinnext_3_s4/I3
12.820	0.609	tINS	FF	3	R8C6[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbinnext_3_s4/F
13.189	0.370	tNET	FF	1	R8C4[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbinnext_4_s2/I1
13.950	0.760	tINS	FR	3	R8C4[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbinnext_4_s2/F
14.263	0.313	tNET	RR	1	R8C5[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/wfull_val_s1/I3
15.028	0.765	tINS	RF	1	R8C5[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/wfull_val_s1/F
15.624	0.596	tNET	FF	1	R7C4[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/wfull_val_s0/I0
16.438	0.814	tINS	FF	1	R7C4[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/wfull_val_s0/F
16.438	0.000	tNET	FF	1	R7C4[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Full_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R7C4[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Full_s0/CLK
16.551	-0.296	tSu		1	R7C4[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Full_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	11
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 7.180, 44.162%; route: 8.738, 53.749%; tC2Q: 0.340, 2.089%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path4

Path Summary:

Slack	0.115
Data Arrival Time	8.101
Data Required Time	8.216
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	8	IOB15[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/PCLK
0.650	0.471	tC2Q	RF	5	IOB15[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/Q4
2.945	2.295	tNET	FF	1	R24C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s26/I2
3.409	0.464	tINS	FF	1	R24C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s26/F
3.413	0.004	tNET	FF	1	R24C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s20/I0
4.022	0.609	tINS	FF	1	R24C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s20/F
4.026	0.004	tNET	FF	1	R24C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s11/I2
4.791	0.765	tINS	FF	1	R24C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s11/F
4.795	0.004	tNET	FF	1	R24C10[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s4/I0
5.581	0.786	tINS	FR	6	R24C10[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s4/F
5.905	0.324	tNET	RR	1	R23C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s11/I1
6.719	0.814	tINS	RF	1	R23C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s11/F
6.723	0.004	tNET	FF	1	R23C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s10/I2
7.488	0.765	tINS	FF	1	R23C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s10/F
7.492	0.004	tNET	FF	1	R23C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s9/I0
8.101	0.609	tINS	FF	1	R23C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s9/F
8.101	0.000	tNET	FF	1	R23C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R23C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1/CLK
8.216	-0.296	tSu		1	R23C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 4.812, 60.746%; route: 2.639, 33.314%; tC2Q: 0.471, 5.940%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path5

Path Summary:

Slack	0.131
Data Arrival Time	8.085
Data Required Time	8.216
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_empty_s0
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	1	R9C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/CLK
0.519	0.340	tC2Q	RR	5	R9C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/Q
0.836	0.317	tNET	RR	1	R9C6[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_2_s5/I2
1.622	0.786	tINS	RR	7	R9C6[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_2_s5/F
1.941	0.319	tNET	RR	1	R8C6[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_2_s3/I1
2.756	0.814	tINS	RF	2	R8C6[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_2_s3/F
2.764	0.008	tNET	FF	1	R8C6[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rgraynext_1_s1/I0
3.373	0.609	tINS	FF	2	R8C6[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rgraynext_1_s1/F
4.573	1.200	tNET	FF	2	R7C5[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n162_s0/I0
5.283	0.710	tINS	FF	1	R7C5[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n162_s0/COUT
5.283	0.000	tNET	FF	2	R7C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n163_s0/CIN
5.325	0.042	tINS	FF	1	R7C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n163_s0/COUT
5.325	0.000	tNET	FF	2	R7C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n164_s0/CIN
5.368	0.042	tINS	FF	1	R7C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n164_s0/COUT
5.368	0.000	tNET	FF	2	R7C5[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n165_s0/CIN
5.410	0.042	tINS	FF	2	R7C5[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n165_s0/COUT
6.194	0.784	tNET	FF	1	R9C5[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/w_empty_s0/I0
7.008	0.814	tINS	FF	2	R9C5[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/w_empty_s0/F
8.085	1.076	tNET	FF	1	R9C7[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_empty_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R9C7[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_empty_s0/CLK
8.216	-0.296	tSu		1	R9C7[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_empty_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 3.861, 48.835%; route: 3.705, 46.868%; tC2Q: 0.340, 4.296%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path6

Path Summary:

Slack	0.168
Data Arrival Time	16.384
Data Required Time	16.551
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_11_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/CLK
0.520	0.340	tC2Q	RF	77	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q
1.860	1.340	tNET	FF	1	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I1
2.469	0.609	tINS	FF	5	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
2.481	0.012	tNET	FF	1	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
3.268	0.786	tINS	FR	7	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
3.581	0.313	tNET	RR	1	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
4.045	0.464	tINS	RF	4	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
4.057	0.012	tNET	FF	1	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
4.871	0.814	tINS	FF	5	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
5.238	0.366	tNET	FF	1	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
5.832	0.594	tINS	FR	2	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
6.145	0.313	tNET	RR	1	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
6.609	0.464	tINS	RF	10	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
7.229	0.620	tNET	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
7.693	0.464	tINS	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
8.302	0.608	tNET	FF	2	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
8.709	0.408	tINS	FR	1	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
8.709	0.000	tNET	RR	2	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
8.751	0.042	tINS	RF	1	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
8.751	0.000	tNET	FF	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
8.794	0.042	tINS	FF	1	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
8.794	0.000	tNET	FF	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
9.185	0.391	tINS	FR	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
9.498	0.313	tNET	RR	1	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
10.313	0.814	tINS	RF	9	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
10.691	0.379	tNET	FF	1	R13C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/I0
11.506	0.814	tINS	FF	22	R13C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/F
12.126	0.620	tNET	FF	1	R14C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/I3
12.891	0.765	tINS	FF	15	R14C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/F
14.345	1.454	tNET	FF	1	R18C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1042_s13/I2
14.939	0.594	tINS	FR	1	R18C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1042_s13/F
14.939	0.000	tNET	RR	1	R18C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1042_s9/I0
15.051	0.111	tINS	RR	1	R18C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1042_s9/O
15.051	0.000	tNET	RR	1	R18C11[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1042_s5/I0
15.182	0.131	tINS	RR	1	R18C11[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1042_s5/O
15.497	0.316	tNET	RR	1	R18C11[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1118_s7/I0
16.262	0.765	tINS	RF	1	R18C11[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1118_s7/F
16.262	0.000	tNET	FF	1	R18C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1118_s4/I1
16.372	0.110	tINS	FF	1	R18C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1118_s4/O
16.384	0.011	tNET	FF	1	R18C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_11_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R18C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_11_s1/CLK
16.551	-0.296	tSu		1	R18C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_11_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 9.184, 56.681%; route: 6.679, 41.223%; tC2Q: 0.340, 2.096%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path7

Path Summary:

Slack	0.177
Data Arrival Time	16.374
Data Required Time	16.551
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_15_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/CLK
0.520	0.340	tC2Q	RF	77	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q
1.860	1.340	tNET	FF	1	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I1
2.469	0.609	tINS	FF	5	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
2.481	0.012	tNET	FF	1	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
3.268	0.786	tINS	FR	7	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
3.581	0.313	tNET	RR	1	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
4.045	0.464	tINS	RF	4	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
4.057	0.012	tNET	FF	1	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
4.871	0.814	tINS	FF	5	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
5.238	0.366	tNET	FF	1	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
5.832	0.594	tINS	FR	2	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
6.145	0.313	tNET	RR	1	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
6.609	0.464	tINS	RF	10	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
7.229	0.620	tNET	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
7.693	0.464	tINS	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
8.302	0.608	tNET	FF	2	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
8.709	0.408	tINS	FR	1	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
8.709	0.000	tNET	RR	2	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
8.751	0.042	tINS	RF	1	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
8.751	0.000	tNET	FF	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
9.143	0.391	tINS	FR	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/SUM
9.454	0.312	tNET	RR	1	R13C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s9/I1
9.918	0.464	tINS	RF	6	R13C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s9/F
10.522	0.603	tNET	FF	1	R14C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s6/I3
10.986	0.464	tINS	FF	4	R14C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s6/F
11.602	0.617	tNET	FF	1	R13C11[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n925_s2/I1
12.066	0.464	tINS	FF	18	R13C11[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n925_s2/F
12.940	0.873	tNET	FF	1	R14C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1114_s6/I2
13.754	0.814	tINS	FF	1	R14C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1114_s6/F
13.758	0.004	tNET	FF	1	R14C12[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1114_s5/I2
14.519	0.760	tINS	FR	1	R14C12[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1114_s5/F
14.829	0.310	tNET	RR	1	R15C12[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1114_s4/I0
15.293	0.464	tINS	RF	1	R15C12[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1114_s4/F
15.297	0.004	tNET	FF	1	R15C12[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1114_s2/I1
15.761	0.464	tINS	FF	1	R15C12[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1114_s2/F
15.765	0.004	tNET	FF	1	R15C12[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1114_s1/I0
16.374	0.609	tINS	FF	1	R15C12[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1114_s1/F
16.374	0.000	tNET	FF	1	R15C12[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_15_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R15C12[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_15_s1/CLK
16.551	-0.296	tSu		1	R15C12[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_15_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	18
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 9.540, 58.912%; route: 6.314, 38.991%; tC2Q: 0.340, 2.097%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path8

Path Summary:

Slack	0.181
Data Arrival Time	8.035
Data Required Time	8.216
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s1
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	8	IOB15[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/PCLK
0.579	0.400	tC2Q	RF	5	IOB15[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/Q5
2.035	1.455	tNET	FF	1	R25C11[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s29/I3
2.795	0.760	tINS	FR	1	R25C11[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s29/F
3.105	0.310	tNET	RR	1	R25C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s23/I0
3.870	0.765	tINS	RF	1	R25C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s23/F
3.874	0.004	tNET	FF	1	R25C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s14/I2
4.639	0.765	tINS	FF	1	R25C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s14/F
4.643	0.004	tNET	FF	1	R25C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s5/I1
5.252	0.609	tINS	FF	5	R25C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s5/F
5.984	0.732	tNET	FF	1	R23C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s11/I1
6.799	0.814	tINS	FF	1	R23C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s11/F
6.803	0.004	tNET	FF	1	R23C9[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s10/I2
7.266	0.464	tINS	FF	1	R23C9[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s10/F
7.270	0.004	tNET	FF	1	R23C9[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s9/I0
8.035	0.765	tINS	FF	1	R23C9[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s9/F
8.035	0.000	tNET	FF	1	R23C9[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R23C9[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s1/CLK
8.216	-0.296	tSu		1	R23C9[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 4.942, 62.905%; route: 2.514, 32.002%; tC2Q: 0.400, 5.094%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path9

Path Summary:

Slack	0.194
Data Arrival Time	16.357
Data Required Time	16.551
From	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_rxgoodpacket_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	4	BSRAM_R28[14]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKB
2.745	2.564	tC2Q	RF	1	BSRAM_R28[14]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DO[1]
4.783	2.038	tNET	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s21/I1
5.597	0.814	tINS	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s21/F
5.597	0.000	tNET	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s20/I0
5.707	0.110	tINS	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s20/O
7.510	1.802	tNET	FF	1	R6C32[3][A]	usb_txdat_5_s3/I0
7.973	0.464	tINS	FF	2	R6C32[3][A]	usb_txdat_5_s3/F
9.055	1.081	tNET	FF	1	R5C23[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s10/I1
9.518	0.463	tINS	FR	1	R5C23[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s10/F
9.828	0.310	tNET	RR	1	R5C22[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s9/I0
10.642	0.814	tINS	RF	1	R5C22[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s9/F
10.647	0.004	tNET	FF	1	R5C22[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s6/I2
11.256	0.609	tINS	FF	1	R5C22[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s6/F
11.852	0.596	tNET	FF	1	R4C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s4/I1
12.638	0.786	tINS	FR	2	R4C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s4/F
12.951	0.313	tNET	RR	1	R5C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s3/I1
13.545	0.594	tINS	RR	4	R5C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s3/F
13.859	0.313	tNET	RR	1	R5C20[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n912_s11/I1
14.468	0.609	tINS	RF	1	R5C20[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n912_s11/F
14.472	0.004	tNET	FF	1	R5C20[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n912_s3/I3
15.232	0.760	tINS	FR	1	R5C20[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n912_s3/F
15.543	0.310	tNET	RR	1	R6C20[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n912_s0/I2
16.357	0.814	tINS	RF	1	R6C20[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n912_s0/F
16.357	0.000	tNET	FF	1	R6C20[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_rxgoodpacket_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R6C20[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_rxgoodpacket_s0/CLK
16.551	-0.296	tSu		1	R6C20[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_rxgoodpacket_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	11
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 6.839, 42.281%; route: 6.773, 41.869%; tC2Q: 2.564, 15.850%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path10

Path Summary:

Slack	0.278
Data Arrival Time	16.273
Data Required Time	16.551
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_9_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/CLK
0.520	0.340	tC2Q	RF	77	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q
1.860	1.340	tNET	FF	1	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I1
2.469	0.609	tINS	FF	5	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
2.481	0.012	tNET	FF	1	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
3.268	0.786	tINS	FR	7	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
3.581	0.313	tNET	RR	1	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
4.045	0.464	tINS	RF	4	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
4.057	0.012	tNET	FF	1	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
4.871	0.814	tINS	FF	5	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
5.238	0.366	tNET	FF	1	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
5.832	0.594	tINS	FR	2	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
6.145	0.313	tNET	RR	1	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
6.609	0.464	tINS	RF	10	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
7.229	0.620	tNET	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
7.693	0.464	tINS	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
8.302	0.608	tNET	FF	2	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
8.709	0.408	tINS	FR	1	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
8.709	0.000	tNET	RR	2	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
8.751	0.042	tINS	RF	1	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
8.751	0.000	tNET	FF	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
8.794	0.042	tINS	FF	1	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
8.794	0.000	tNET	FF	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
9.185	0.391	tINS	FR	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
9.498	0.313	tNET	RR	1	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
10.313	0.814	tINS	RF	9	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
10.691	0.379	tNET	FF	1	R13C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/I0
11.506	0.814	tINS	FF	22	R13C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/F
12.126	0.620	tNET	FF	1	R14C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/I3
12.891	0.765	tINS	FF	15	R14C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/F
14.235	1.344	tNET	FF	1	R17C9[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1044_s13/I2
14.829	0.594	tINS	FR	1	R17C9[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1044_s13/F
14.829	0.000	tNET	RR	1	R17C9[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1044_s9/I0
14.940	0.111	tINS	RR	1	R17C9[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1044_s9/O
14.940	0.000	tNET	RR	1	R17C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1044_s5/I0
15.071	0.131	tINS	RR	1	R17C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1044_s5/O
15.387	0.316	tNET	RR	1	R17C9[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1120_s7/I0
16.152	0.765	tINS	RF	1	R17C9[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1120_s7/F
16.152	0.000	tNET	FF	1	R17C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1120_s4/I1
16.262	0.110	tINS	FF	1	R17C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1120_s4/O
16.273	0.011	tNET	FF	1	R17C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R17C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_9_s1/CLK
16.551	-0.296	tSu		1	R17C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_9_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 9.184, 57.070%; route: 6.569, 40.819%; tC2Q: 0.340, 2.110%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path11

Path Summary:

Slack	0.285
Data Arrival Time	16.267
Data Required Time	16.551
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_4_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R18C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/CLK
0.520	0.340	tC2Q	RR	1	R18C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/Q
0.769	0.249	tNET	RR	1	R18C20[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_15_s10/I3
1.584	0.814	tINS	RF	34	R18C20[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_15_s10/F
4.628	3.044	tNET	FF	1	R25C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/n2208_s3/I1
5.092	0.464	tINS	FF	17	R25C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/n2208_s3/F
5.960	0.868	tNET	FF	1	R25C25[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s15/I0
6.725	0.765	tINS	FF	1	R25C25[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s15/F
6.729	0.004	tNET	FF	1	R25C25[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s11/I0
7.494	0.765	tINS	FF	1	R25C25[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s11/F
7.498	0.004	tNET	FF	1	R25C25[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s8/I2
7.961	0.464	tINS	FF	2	R25C25[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s8/F
10.720	2.759	tNET	FF	2	R20C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1411_s0/I1
11.494	0.774	tINS	FF	1	R20C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1411_s0/COUT
11.494	0.000	tNET	FF	2	R20C15[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1412_s0/CIN
11.537	0.042	tINS	FF	1	R20C15[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1412_s0/COUT
11.537	0.000	tNET	FF	2	R20C15[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1413_s0/CIN
11.579	0.042	tINS	FF	1	R20C15[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1413_s0/COUT
11.579	0.000	tNET	FF	2	R20C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1414_s0/CIN
11.621	0.042	tINS	FF	1	R20C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1414_s0/COUT
11.621	0.000	tNET	FF	2	R20C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1415_s0/CIN
11.663	0.042	tINS	FF	1	R20C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1415_s0/COUT
11.663	0.000	tNET	FF	2	R20C16[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1416_s0/CIN
11.706	0.042	tINS	FF	1	R20C16[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1416_s0/COUT
11.706	0.000	tNET	FF	2	R20C16[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1417_s0/CIN
11.748	0.042	tINS	FF	1	R20C16[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1417_s0/COUT
11.748	0.000	tNET	FF	2	R20C16[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1418_s0/CIN
11.790	0.042	tINS	FF	1	R20C16[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1418_s0/COUT
11.790	0.000	tNET	FF	2	R20C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1419_s0/CIN
11.832	0.042	tINS	FF	1	R20C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1419_s0/COUT
11.832	0.000	tNET	FF	2	R20C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1420_s0/CIN
11.875	0.042	tINS	FF	1	R20C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1420_s0/COUT
11.875	0.000	tNET	FF	2	R20C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1421_s0/CIN
11.917	0.042	tINS	FF	1	R20C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1421_s0/COUT
11.917	0.000	tNET	FF	2	R20C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1422_s0/CIN
11.959	0.042	tINS	FF	1	R20C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1422_s0/COUT
11.959	0.000	tNET	FF	2	R20C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1423_s0/CIN
12.001	0.042	tINS	FF	1	R20C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1423_s0/COUT
12.001	0.000	tNET	FF	2	R20C17[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1424_s0/CIN
12.044	0.042	tINS	FF	3	R20C17[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1424_s0/COUT
12.827	0.784	tNET	FF	1	R20C19[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1688_s39/I2
13.592	0.765	tINS	FF	3	R20C19[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1688_s39/F
13.959	0.367	tNET	FF	1	R20C21[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1678_s14/I1
14.719	0.760	tINS	FR	3	R20C21[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1678_s14/F
15.034	0.315	tNET	RR	1	R20C20[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1666_s12/I1
15.498	0.464	tINS	RF	1	R20C20[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1666_s12/F
15.502	0.004	tNET	FF	1	R20C20[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1666_s11/I0
16.267	0.765	tINS	FF	1	R20C20[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1666_s11/F
16.267	0.000	tNET	FF	1	R20C20[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R20C20[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_4_s0/CLK
16.551	-0.296	tSu		1	R20C20[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	13
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 7.348, 45.682%; route: 8.398, 52.206%; tC2Q: 0.340, 2.111%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path12

Path Summary:

Slack	0.285
Data Arrival Time	16.267
Data Required Time	16.551
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_5_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R18C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/CLK
0.520	0.340	tC2Q	RR	1	R18C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/Q
0.769	0.249	tNET	RR	1	R18C20[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_15_s10/I3
1.584	0.814	tINS	RF	34	R18C20[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_15_s10/F
4.628	3.044	tNET	FF	1	R25C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/n2208_s3/I1
5.092	0.464	tINS	FF	17	R25C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/n2208_s3/F
5.960	0.868	tNET	FF	1	R25C25[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s15/I0
6.725	0.765	tINS	FF	1	R25C25[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s15/F
6.729	0.004	tNET	FF	1	R25C25[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s11/I0
7.494	0.765	tINS	FF	1	R25C25[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s11/F
7.498	0.004	tNET	FF	1	R25C25[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s8/I2
7.961	0.464	tINS	FF	2	R25C25[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s8/F
10.720	2.759	tNET	FF	2	R20C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1411_s0/I1
11.494	0.774	tINS	FF	1	R20C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1411_s0/COUT
11.494	0.000	tNET	FF	2	R20C15[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1412_s0/CIN
11.537	0.042	tINS	FF	1	R20C15[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1412_s0/COUT
11.537	0.000	tNET	FF	2	R20C15[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1413_s0/CIN
11.579	0.042	tINS	FF	1	R20C15[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1413_s0/COUT
11.579	0.000	tNET	FF	2	R20C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1414_s0/CIN
11.621	0.042	tINS	FF	1	R20C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1414_s0/COUT
11.621	0.000	tNET	FF	2	R20C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1415_s0/CIN
11.663	0.042	tINS	FF	1	R20C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1415_s0/COUT
11.663	0.000	tNET	FF	2	R20C16[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1416_s0/CIN
11.706	0.042	tINS	FF	1	R20C16[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1416_s0/COUT
11.706	0.000	tNET	FF	2	R20C16[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1417_s0/CIN
11.748	0.042	tINS	FF	1	R20C16[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1417_s0/COUT
11.748	0.000	tNET	FF	2	R20C16[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1418_s0/CIN
11.790	0.042	tINS	FF	1	R20C16[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1418_s0/COUT
11.790	0.000	tNET	FF	2	R20C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1419_s0/CIN
11.832	0.042	tINS	FF	1	R20C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1419_s0/COUT
11.832	0.000	tNET	FF	2	R20C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1420_s0/CIN
11.875	0.042	tINS	FF	1	R20C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1420_s0/COUT
11.875	0.000	tNET	FF	2	R20C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1421_s0/CIN
11.917	0.042	tINS	FF	1	R20C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1421_s0/COUT
11.917	0.000	tNET	FF	2	R20C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1422_s0/CIN
11.959	0.042	tINS	FF	1	R20C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1422_s0/COUT
11.959	0.000	tNET	FF	2	R20C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1423_s0/CIN
12.001	0.042	tINS	FF	1	R20C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1423_s0/COUT
12.001	0.000	tNET	FF	2	R20C17[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1424_s0/CIN
12.044	0.042	tINS	FF	3	R20C17[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1424_s0/COUT
12.827	0.784	tNET	FF	1	R20C19[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1688_s39/I2
13.592	0.765	tINS	FF	3	R20C19[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1688_s39/F
13.959	0.367	tNET	FF	1	R20C21[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1678_s14/I1
14.719	0.760	tINS	FR	3	R20C21[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1678_s14/F
15.034	0.315	tNET	RR	1	R20C20[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1663_s12/I1
15.498	0.464	tINS	RF	1	R20C20[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1663_s12/F
15.502	0.004	tNET	FF	1	R20C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1663_s11/I0
16.267	0.765	tINS	FF	1	R20C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1663_s11/F
16.267	0.000	tNET	FF	1	R20C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R20C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_5_s0/CLK
16.551	-0.296	tSu		1	R20C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	13
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 7.348, 45.682%; route: 8.398, 52.206%; tC2Q: 0.340, 2.111%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path13

Path Summary:

Slack	0.361
Data Arrival Time	16.191
Data Required Time	16.551
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_9_s2
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R18C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/CLK
0.520	0.340	tC2Q	RR	1	R18C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/Q
0.769	0.249	tNET	RR	1	R18C20[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_15_s10/I3
1.584	0.814	tINS	RF	34	R18C20[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_15_s10/F
4.628	3.044	tNET	FF	1	R25C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/n2208_s3/I1
5.092	0.464	tINS	FF	17	R25C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/n2208_s3/F
5.960	0.868	tNET	FF	1	R25C25[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s15/I0
6.725	0.765	tINS	FF	1	R25C25[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s15/F
6.729	0.004	tNET	FF	1	R25C25[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s11/I0
7.494	0.765	tINS	FF	1	R25C25[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s11/F
7.498	0.004	tNET	FF	1	R25C25[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s8/I2
7.961	0.464	tINS	FF	2	R25C25[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s8/F
10.720	2.759	tNET	FF	2	R20C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1411_s0/I1
11.494	0.774	tINS	FF	1	R20C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1411_s0/COUT
11.494	0.000	tNET	FF	2	R20C15[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1412_s0/CIN
11.537	0.042	tINS	FF	1	R20C15[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1412_s0/COUT
11.537	0.000	tNET	FF	2	R20C15[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1413_s0/CIN
11.579	0.042	tINS	FF	1	R20C15[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1413_s0/COUT
11.579	0.000	tNET	FF	2	R20C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1414_s0/CIN
11.621	0.042	tINS	FF	1	R20C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1414_s0/COUT
11.621	0.000	tNET	FF	2	R20C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1415_s0/CIN
11.663	0.042	tINS	FF	1	R20C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1415_s0/COUT
11.663	0.000	tNET	FF	2	R20C16[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1416_s0/CIN
11.706	0.042	tINS	FF	1	R20C16[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1416_s0/COUT
11.706	0.000	tNET	FF	2	R20C16[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1417_s0/CIN
11.748	0.042	tINS	FF	1	R20C16[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1417_s0/COUT
11.748	0.000	tNET	FF	2	R20C16[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1418_s0/CIN
11.790	0.042	tINS	FF	1	R20C16[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1418_s0/COUT
11.790	0.000	tNET	FF	2	R20C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1419_s0/CIN
11.832	0.042	tINS	FF	1	R20C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1419_s0/COUT
11.832	0.000	tNET	FF	2	R20C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1420_s0/CIN
11.875	0.042	tINS	FF	1	R20C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1420_s0/COUT
11.875	0.000	tNET	FF	2	R20C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1421_s0/CIN
11.917	0.042	tINS	FF	1	R20C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1421_s0/COUT
11.917	0.000	tNET	FF	2	R20C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1422_s0/CIN
11.959	0.042	tINS	FF	1	R20C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1422_s0/COUT
11.959	0.000	tNET	FF	2	R20C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1423_s0/CIN
12.001	0.042	tINS	FF	1	R20C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1423_s0/COUT
12.001	0.000	tNET	FF	2	R20C17[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1424_s0/CIN
12.044	0.042	tINS	FF	3	R20C17[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1424_s0/COUT
12.827	0.784	tNET	FF	1	R20C19[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1688_s39/I2
13.592	0.765	tINS	FF	3	R20C19[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1688_s39/F
14.441	0.849	tNET	FF	1	R18C18[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1686_s44/I0
14.904	0.464	tINS	FF	1	R18C18[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1686_s44/F
14.908	0.004	tNET	FF	1	R18C18[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1686_s40/I0
15.372	0.464	tINS	FF	1	R18C18[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1686_s40/F
15.376	0.004	tNET	FF	1	R18C18[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1686_s37/I2
16.191	0.814	tINS	FF	1	R18C18[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1686_s37/F
16.191	0.000	tNET	FF	1	R18C18[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_9_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R18C18[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_9_s2/CLK
16.551	-0.296	tSu		1	R18C18[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_9_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	13
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 7.102, 44.358%; route: 8.569, 53.521%; tC2Q: 0.340, 2.121%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path14

Path Summary:

Slack	0.382
Data Arrival Time	16.169
Data Required Time	16.551
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_8_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/CLK
0.520	0.340	tC2Q	RF	77	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q
1.860	1.340	tNET	FF	1	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I1
2.469	0.609	tINS	FF	5	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
2.481	0.012	tNET	FF	1	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
3.268	0.786	tINS	FR	7	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
3.581	0.313	tNET	RR	1	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
4.045	0.464	tINS	RF	4	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
4.057	0.012	tNET	FF	1	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
4.871	0.814	tINS	FF	5	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
5.238	0.366	tNET	FF	1	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
5.832	0.594	tINS	FR	2	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
6.145	0.313	tNET	RR	1	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
6.609	0.464	tINS	RF	10	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
7.229	0.620	tNET	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
7.693	0.464	tINS	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
8.302	0.608	tNET	FF	2	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
8.709	0.408	tINS	FR	1	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
8.709	0.000	tNET	RR	2	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
8.751	0.042	tINS	RF	1	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
8.751	0.000	tNET	FF	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
8.794	0.042	tINS	FF	1	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
8.794	0.000	tNET	FF	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
9.185	0.391	tINS	FR	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
9.498	0.313	tNET	RR	1	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
10.313	0.814	tINS	RF	9	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
10.691	0.379	tNET	FF	1	R13C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s6/I0
11.506	0.814	tINS	FF	19	R13C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s6/F
12.126	0.621	tNET	FF	1	R14C10[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s10/I3
12.590	0.464	tINS	FF	18	R14C10[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s10/F
13.939	1.349	tNET	FF	1	R17C11[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1045_s11/I2
14.725	0.786	tINS	FR	1	R17C11[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1045_s11/F
14.725	0.000	tNET	RR	1	R17C11[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1045_s10/I0
14.836	0.111	tINS	RR	1	R17C11[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1045_s10/O
14.836	0.000	tNET	RR	1	R17C11[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1045_s5/I1
14.967	0.131	tINS	RR	1	R17C11[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1045_s5/O
15.283	0.316	tNET	RR	1	R17C11[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1121_s7/I0
16.048	0.765	tINS	RF	1	R17C11[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1121_s7/F
16.048	0.000	tNET	FF	1	R17C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1121_s4/I1
16.158	0.110	tINS	FF	1	R17C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1121_s4/O
16.169	0.011	tNET	FF	1	R17C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R17C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_8_s1/CLK
16.551	-0.296	tSu		1	R17C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_8_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 9.075, 56.760%; route: 6.574, 41.116%; tC2Q: 0.340, 2.124%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path15

Path Summary:

Slack	0.399
Data Arrival Time	7.816
Data Required Time	8.216
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_0_s1
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_1_s1
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	1	R20C13[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_0_s1/CLK
0.519	0.340	tC2Q	RF	21	R20C13[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_0_s1/Q
1.126	0.607	tNET	FF	1	R21C12[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n79_s4/I2
1.735	0.609	tINS	FF	9	R21C12[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n79_s4/F
2.960	1.225	tNET	FF	1	R20C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n120_s8/I2
3.569	0.609	tINS	FF	1	R20C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n120_s8/F
3.932	0.363	tNET	FF	1	R20C11[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n120_s5/I2
4.541	0.609	tINS	FF	2	R20C11[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n120_s5/F
4.550	0.008	tNET	FF	1	R20C11[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n120_s6/I3
5.314	0.765	tINS	FF	1	R20C11[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n120_s6/F
5.318	0.004	tNET	FF	1	R20C11[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n120_s3/I0
5.927	0.609	tINS	FF	1	R20C11[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n120_s3/F
5.931	0.004	tNET	FF	1	R20C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n120_s1/I1
6.692	0.760	tINS	FR	1	R20C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n120_s1/F
7.002	0.310	tNET	RR	1	R20C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n120_s0/I0
7.816	0.814	tINS	RF	1	R20C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n120_s0/F
7.816	0.000	tNET	FF	1	R20C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R20C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_1_s1/CLK
8.216	-0.296	tSu		1	R20C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 4.776, 62.533%; route: 2.522, 33.020%; tC2Q: 0.340, 4.447%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path16

Path Summary:

Slack	0.490
Data Arrival Time	7.726
Data Required Time	8.216
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	1	R9C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/CLK
0.519	0.340	tC2Q	RR	5	R9C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/Q
0.836	0.317	tNET	RR	1	R9C6[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_2_s5/I2
1.622	0.786	tINS	RR	7	R9C6[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_2_s5/F
1.941	0.319	tNET	RR	1	R8C6[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_2_s3/I1
2.756	0.814	tINS	RF	2	R8C6[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_2_s3/F
2.764	0.008	tNET	FF	1	R8C6[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rgraynext_1_s1/I0
3.373	0.609	tINS	FF	2	R8C6[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rgraynext_1_s1/F
4.573	1.200	tNET	FF	2	R7C5[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n162_s0/I0
5.283	0.710	tINS	FF	1	R7C5[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n162_s0/COUT
5.283	0.000	tNET	FF	2	R7C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n163_s0/CIN
5.325	0.042	tINS	FF	1	R7C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n163_s0/COUT
5.325	0.000	tNET	FF	2	R7C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n164_s0/CIN
5.368	0.042	tINS	FF	1	R7C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n164_s0/COUT
5.368	0.000	tNET	FF	2	R7C5[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n165_s0/CIN
5.410	0.042	tINS	FF	2	R7C5[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n165_s0/COUT
6.194	0.784	tNET	FF	1	R9C5[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/w_empty_s0/I0
7.008	0.814	tINS	FF	2	R9C5[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/w_empty_s0/F
7.726	0.717	tNET	FF	1	R9C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R9C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0/CLK
8.216	-0.296	tSu		1	R9C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 3.861, 51.159%; route: 3.346, 44.340%; tC2Q: 0.340, 4.501%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path17

Path Summary:

Slack	0.494
Data Arrival Time	16.058
Data Required Time	16.551
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_3_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/CLK
0.520	0.340	tC2Q	RF	77	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q
1.860	1.340	tNET	FF	1	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I1
2.469	0.609	tINS	FF	5	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
2.481	0.012	tNET	FF	1	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
3.268	0.786	tINS	FR	7	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
3.581	0.313	tNET	RR	1	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
4.045	0.464	tINS	RF	4	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
4.057	0.012	tNET	FF	1	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
4.871	0.814	tINS	FF	5	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
5.238	0.366	tNET	FF	1	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
5.832	0.594	tINS	FR	2	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
6.145	0.313	tNET	RR	1	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
6.609	0.464	tINS	RF	10	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
7.229	0.620	tNET	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
7.693	0.464	tINS	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
8.302	0.608	tNET	FF	2	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
8.709	0.408	tINS	FR	1	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
8.709	0.000	tNET	RR	2	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
8.751	0.042	tINS	RF	1	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
8.751	0.000	tNET	FF	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
8.794	0.042	tINS	FF	1	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
8.794	0.000	tNET	FF	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
9.185	0.391	tINS	FR	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
9.498	0.313	tNET	RR	1	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
10.313	0.814	tINS	RF	9	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
10.691	0.379	tNET	FF	1	R13C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/I0
11.506	0.814	tINS	FF	22	R13C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/F
12.126	0.620	tNET	FF	1	R14C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/I3
12.891	0.765	tINS	FF	15	R14C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/F
13.983	1.092	tNET	FF	1	R14C8[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1050_s13/I2
14.769	0.786	tINS	FR	1	R14C8[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1050_s13/F
14.769	0.000	tNET	RR	1	R14C8[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1050_s9/I0
14.880	0.111	tINS	RR	1	R14C8[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1050_s9/O
14.880	0.000	tNET	RR	1	R14C8[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1050_s5/I0
15.011	0.131	tINS	RR	1	R14C8[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1050_s5/O
15.327	0.316	tNET	RR	1	R14C9[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1126_s7/I0
15.936	0.609	tINS	RF	1	R14C9[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1126_s7/F
15.936	0.000	tNET	FF	1	R14C9[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1126_s4/I1
16.046	0.110	tINS	FF	1	R14C9[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1126_s4/O
16.058	0.011	tNET	FF	1	R14C9[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R14C9[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_3_s1/CLK
16.551	-0.296	tSu		1	R14C9[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 9.220, 58.074%; route: 6.317, 39.787%; tC2Q: 0.340, 2.139%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path18

Path Summary:

Slack	0.497
Data Arrival Time	16.054
Data Required Time	16.551
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_2_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/CLK
0.520	0.340	tC2Q	RF	77	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q
1.860	1.340	tNET	FF	1	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I1
2.469	0.609	tINS	FF	5	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
2.481	0.012	tNET	FF	1	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
3.268	0.786	tINS	FR	7	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
3.581	0.313	tNET	RR	1	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
4.045	0.464	tINS	RF	4	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
4.057	0.012	tNET	FF	1	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
4.871	0.814	tINS	FF	5	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
5.238	0.366	tNET	FF	1	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
5.832	0.594	tINS	FR	2	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
6.145	0.313	tNET	RR	1	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
6.609	0.464	tINS	RF	10	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
7.229	0.620	tNET	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
7.693	0.464	tINS	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
8.302	0.608	tNET	FF	2	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
8.709	0.408	tINS	FR	1	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
8.709	0.000	tNET	RR	2	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
8.751	0.042	tINS	RF	1	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
8.751	0.000	tNET	FF	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
8.794	0.042	tINS	FF	1	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
8.794	0.000	tNET	FF	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
9.185	0.391	tINS	FR	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
9.498	0.313	tNET	RR	1	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
10.313	0.814	tINS	RF	9	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
10.691	0.379	tNET	FF	1	R13C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/I0
11.506	0.814	tINS	FF	22	R13C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/F
12.126	0.620	tNET	FF	1	R14C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/I3
12.891	0.765	tINS	FF	15	R14C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/F
13.979	1.089	tNET	FF	1	R15C8[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1051_s13/I2
14.766	0.786	tINS	FR	1	R15C8[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1051_s13/F
14.766	0.000	tNET	RR	1	R15C8[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1051_s9/I0
14.877	0.111	tINS	RR	1	R15C8[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1051_s9/O
14.877	0.000	tNET	RR	1	R15C8[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1051_s5/I0
15.008	0.131	tINS	RR	1	R15C8[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1051_s5/O
15.323	0.316	tNET	RR	1	R15C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1127_s7/I0
15.933	0.609	tINS	RF	1	R15C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1127_s7/F
15.933	0.000	tNET	FF	1	R15C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1127_s4/I1
16.043	0.110	tINS	FF	1	R15C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1127_s4/O
16.054	0.011	tNET	FF	1	R15C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R15C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_2_s1/CLK
16.551	-0.296	tSu		1	R15C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 9.220, 58.086%; route: 6.314, 39.774%; tC2Q: 0.340, 2.140%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path19

Path Summary:

Slack	0.506
Data Arrival Time	16.046
Data Required Time	16.551
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_2_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R18C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/CLK
0.520	0.340	tC2Q	RR	1	R18C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/Q
0.769	0.249	tNET	RR	1	R18C20[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_15_s10/I3
1.584	0.814	tINS	RF	34	R18C20[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_15_s10/F
4.628	3.044	tNET	FF	1	R25C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/n2208_s3/I1
5.092	0.464	tINS	FF	17	R25C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/n2208_s3/F
5.960	0.868	tNET	FF	1	R25C25[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s15/I0
6.725	0.765	tINS	FF	1	R25C25[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s15/F
6.729	0.004	tNET	FF	1	R25C25[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s11/I0
7.494	0.765	tINS	FF	1	R25C25[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s11/F
7.498	0.004	tNET	FF	1	R25C25[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s8/I2
7.961	0.464	tINS	FF	2	R25C25[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s8/F
10.720	2.759	tNET	FF	2	R20C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1411_s0/I1
11.494	0.774	tINS	FF	1	R20C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1411_s0/COUT
11.494	0.000	tNET	FF	2	R20C15[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1412_s0/CIN
11.537	0.042	tINS	FF	1	R20C15[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1412_s0/COUT
11.537	0.000	tNET	FF	2	R20C15[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1413_s0/CIN
11.579	0.042	tINS	FF	1	R20C15[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1413_s0/COUT
11.579	0.000	tNET	FF	2	R20C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1414_s0/CIN
11.621	0.042	tINS	FF	1	R20C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1414_s0/COUT
11.621	0.000	tNET	FF	2	R20C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1415_s0/CIN
11.663	0.042	tINS	FF	1	R20C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1415_s0/COUT
11.663	0.000	tNET	FF	2	R20C16[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1416_s0/CIN
11.706	0.042	tINS	FF	1	R20C16[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1416_s0/COUT
11.706	0.000	tNET	FF	2	R20C16[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1417_s0/CIN
11.748	0.042	tINS	FF	1	R20C16[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1417_s0/COUT
11.748	0.000	tNET	FF	2	R20C16[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1418_s0/CIN
11.790	0.042	tINS	FF	1	R20C16[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1418_s0/COUT
11.790	0.000	tNET	FF	2	R20C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1419_s0/CIN
11.832	0.042	tINS	FF	1	R20C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1419_s0/COUT
11.832	0.000	tNET	FF	2	R20C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1420_s0/CIN
11.875	0.042	tINS	FF	1	R20C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1420_s0/COUT
11.875	0.000	tNET	FF	2	R20C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1421_s0/CIN
11.917	0.042	tINS	FF	1	R20C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1421_s0/COUT
11.917	0.000	tNET	FF	2	R20C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1422_s0/CIN
11.959	0.042	tINS	FF	1	R20C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1422_s0/COUT
11.959	0.000	tNET	FF	2	R20C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1423_s0/CIN
12.001	0.042	tINS	FF	1	R20C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1423_s0/COUT
12.001	0.000	tNET	FF	2	R20C17[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1424_s0/CIN
12.044	0.042	tINS	FF	3	R20C17[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1424_s0/COUT
12.824	0.780	tNET	FF	1	R20C18[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1686_s38/I0
13.584	0.760	tINS	FR	3	R20C18[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1686_s38/F
13.896	0.312	tNET	RR	1	R20C19[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1669_s12/I0
14.710	0.814	tINS	RF	2	R20C19[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1669_s12/F
15.437	0.726	tNET	FF	1	R20C21[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1672_s11/I2
16.046	0.609	tINS	FF	1	R20C21[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1672_s11/F
16.046	0.000	tNET	FF	1	R20C21[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R20C21[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_2_s0/CLK
16.551	-0.296	tSu		1	R20C21[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	12
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 6.779, 42.727%; route: 8.747, 55.132%; tC2Q: 0.340, 2.141%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path20

Path Summary:

Slack	0.559
Data Arrival Time	7.657
Data Required Time	8.216
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_0_s1
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	1	R20C12[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3/CLK
0.519	0.340	tC2Q	RF	10	R20C12[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3/Q
1.623	1.104	tNET	FF	1	R20C7[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n321_s16/I3
2.437	0.814	tINS	FF	11	R20C7[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n321_s16/F
3.061	0.624	tNET	FF	1	R21C8[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n321_s12/I3
3.875	0.814	tINS	FF	3	R21C8[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n321_s12/F
4.479	0.604	tNET	FF	1	R20C7[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n321_s13/I2
5.293	0.814	tINS	FF	2	R20C7[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n321_s13/F
5.302	0.008	tNET	FF	1	R20C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n119_s3/I3
5.765	0.464	tINS	FF	3	R20C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n119_s3/F
6.842	1.077	tNET	FF	1	R21C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n121_s0/I2
7.657	0.814	tINS	FF	1	R21C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n121_s0/F
7.657	0.000	tNET	FF	1	R21C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R21C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_0_s1/CLK
8.216	-0.296	tSu		1	R21C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 3.721, 49.767%; route: 3.417, 45.691%; tC2Q: 0.340, 4.542%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path21

Path Summary:

Slack	0.612
Data Arrival Time	15.940
Data Required Time	16.551
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_12_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/CLK
0.520	0.340	tC2Q	RF	77	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q
1.860	1.340	tNET	FF	1	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I1
2.469	0.609	tINS	FF	5	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
2.481	0.012	tNET	FF	1	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
3.268	0.786	tINS	FR	7	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
3.581	0.313	tNET	RR	1	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
4.045	0.464	tINS	RF	4	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
4.057	0.012	tNET	FF	1	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
4.871	0.814	tINS	FF	5	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
5.238	0.366	tNET	FF	1	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
5.832	0.594	tINS	FR	2	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
6.145	0.313	tNET	RR	1	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
6.609	0.464	tINS	RF	10	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
7.229	0.620	tNET	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
7.693	0.464	tINS	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
8.302	0.608	tNET	FF	2	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
8.709	0.408	tINS	FR	1	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
8.709	0.000	tNET	RR	2	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
8.751	0.042	tINS	RF	1	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
8.751	0.000	tNET	FF	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
9.143	0.391	tINS	FR	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/SUM
9.454	0.312	tNET	RR	1	R13C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s9/I1
9.918	0.464	tINS	RF	6	R13C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s9/F
10.522	0.603	tNET	FF	1	R14C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s6/I3
10.986	0.464	tINS	FF	4	R14C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s6/F
11.602	0.617	tNET	FF	1	R13C11[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n925_s2/I1
12.066	0.464	tINS	FF	18	R13C11[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n925_s2/F
14.010	1.944	tNET	FF	1	R18C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1041_s12/I2
14.796	0.786	tINS	FR	1	R18C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1041_s12/F
14.796	0.000	tNET	RR	1	R18C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1041_s10/I1
14.907	0.111	tINS	RR	1	R18C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1041_s10/O
14.907	0.000	tNET	RR	1	R18C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1041_s5/I1
15.038	0.131	tINS	RR	1	R18C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1041_s5/O
15.354	0.316	tNET	RR	1	R18C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1117_s7/I0
15.818	0.464	tINS	RF	1	R18C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1117_s7/F
15.818	0.000	tNET	FF	1	R18C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1117_s4/I1
15.928	0.110	tINS	FF	1	R18C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1117_s4/O
15.940	0.011	tNET	FF	1	R18C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_12_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R18C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_12_s1/CLK
16.551	-0.296	tSu		1	R18C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_12_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 8.031, 50.962%; route: 7.388, 46.883%; tC2Q: 0.340, 2.155%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path22

Path Summary:

Slack	0.628
Data Arrival Time	15.923
Data Required Time	16.551
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_1_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/CLK
0.520	0.340	tC2Q	RF	77	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q
1.860	1.340	tNET	FF	1	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I1
2.469	0.609	tINS	FF	5	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
2.481	0.012	tNET	FF	1	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
3.268	0.786	tINS	FR	7	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
3.581	0.313	tNET	RR	1	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
4.045	0.464	tINS	RF	4	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
4.057	0.012	tNET	FF	1	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
4.871	0.814	tINS	FF	5	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
5.238	0.366	tNET	FF	1	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
5.832	0.594	tINS	FR	2	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
6.145	0.313	tNET	RR	1	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
6.609	0.464	tINS	RF	10	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
7.229	0.620	tNET	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
7.693	0.464	tINS	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
8.302	0.608	tNET	FF	2	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
8.709	0.408	tINS	FR	1	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
8.709	0.000	tNET	RR	2	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
8.751	0.042	tINS	RF	1	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
8.751	0.000	tNET	FF	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
8.794	0.042	tINS	FF	1	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
8.794	0.000	tNET	FF	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
9.185	0.391	tINS	FR	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
9.498	0.313	tNET	RR	1	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
10.313	0.814	tINS	RF	9	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
10.691	0.379	tNET	FF	1	R13C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s6/I0
11.506	0.814	tINS	FF	19	R13C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s6/F
12.126	0.621	tNET	FF	1	R14C10[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s10/I3
12.590	0.464	tINS	FF	18	R14C10[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s10/F
14.171	1.581	tNET	FF	1	R16C8[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1052_s11/I2
14.634	0.463	tINS	FR	1	R16C8[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1052_s11/F
14.634	0.000	tNET	RR	1	R16C8[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1052_s10/I0
14.746	0.111	tINS	RR	1	R16C8[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1052_s10/O
14.746	0.000	tNET	RR	1	R16C8[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1052_s5/I1
14.877	0.131	tINS	RR	1	R16C8[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1052_s5/O
15.192	0.316	tNET	RR	1	R16C9[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1128_s7/I0
15.801	0.609	tINS	RF	1	R16C9[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1128_s7/F
15.801	0.000	tNET	FF	1	R16C9[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1128_s4/I1
15.912	0.110	tINS	FF	1	R16C9[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1128_s4/O
15.923	0.011	tNET	FF	1	R16C9[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R16C9[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_1_s1/CLK
16.551	-0.296	tSu		1	R16C9[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 8.596, 54.607%; route: 6.806, 43.236%; tC2Q: 0.340, 2.157%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path23

Path Summary:

Slack	0.635
Data Arrival Time	7.581
Data Required Time	8.216
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_5_s1
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	1	R20C12[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3/CLK
0.519	0.340	tC2Q	RF	10	R20C12[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3/Q
1.623	1.104	tNET	FF	1	R20C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n105_s6/I2
2.437	0.814	tINS	FF	17	R20C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n105_s6/F
3.443	1.006	tNET	FF	1	R22C8[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n319_s11/I3
4.257	0.814	tINS	FF	1	R22C8[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n319_s11/F
4.261	0.004	tNET	FF	1	R22C8[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n319_s9/I1
5.022	0.760	tINS	FR	2	R22C8[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n319_s9/F
5.335	0.313	tNET	RR	1	R22C7[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n319_s8/I0
6.149	0.814	tINS	RF	1	R22C7[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n319_s8/F
6.153	0.004	tNET	FF	1	R22C7[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n319_s6/I1
6.968	0.814	tINS	FF	1	R22C7[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n319_s6/F
6.972	0.004	tNET	FF	1	R22C7[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n319_s5/I0
7.581	0.609	tINS	FF	1	R22C7[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n319_s5/F
7.581	0.000	tNET	FF	1	R22C7[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R22C7[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_5_s1/CLK
8.216	-0.296	tSu		1	R22C7[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_5_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 4.627, 62.512%; route: 2.435, 32.900%; tC2Q: 0.340, 4.589%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path24

Path Summary:

Slack	0.641
Data Arrival Time	15.910
Data Required Time	16.551
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_10_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/CLK
0.520	0.340	tC2Q	RF	77	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q
1.860	1.340	tNET	FF	1	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I1
2.469	0.609	tINS	FF	5	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
2.481	0.012	tNET	FF	1	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
3.268	0.786	tINS	FR	7	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
3.581	0.313	tNET	RR	1	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
4.045	0.464	tINS	RF	4	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
4.057	0.012	tNET	FF	1	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
4.871	0.814	tINS	FF	5	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
5.238	0.366	tNET	FF	1	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
5.832	0.594	tINS	FR	2	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
6.145	0.313	tNET	RR	1	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
6.609	0.464	tINS	RF	10	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
7.229	0.620	tNET	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
7.693	0.464	tINS	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
8.302	0.608	tNET	FF	2	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
8.709	0.408	tINS	FR	1	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
8.709	0.000	tNET	RR	2	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
8.751	0.042	tINS	RF	1	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
8.751	0.000	tNET	FF	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
8.794	0.042	tINS	FF	1	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
8.794	0.000	tNET	FF	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
9.185	0.391	tINS	FR	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
9.498	0.313	tNET	RR	1	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
10.313	0.814	tINS	RF	9	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
10.691	0.379	tNET	FF	1	R13C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/I0
11.506	0.814	tINS	FF	22	R13C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/F
12.126	0.620	tNET	FF	1	R14C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/I3
12.891	0.765	tINS	FF	15	R14C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/F
13.630	0.740	tNET	FF	1	R17C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1043_s13/I2
14.417	0.786	tINS	FR	1	R17C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1043_s13/F
14.417	0.000	tNET	RR	1	R17C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1043_s9/I0
14.528	0.111	tINS	RR	1	R17C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1043_s9/O
14.528	0.000	tNET	RR	1	R17C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1043_s5/I0
14.659	0.131	tINS	RR	1	R17C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1043_s5/O
14.975	0.316	tNET	RR	1	R16C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1119_s7/I0
15.789	0.814	tINS	RF	1	R16C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1119_s7/F
15.789	0.000	tNET	FF	1	R16C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1119_s4/I1
15.899	0.110	tINS	FF	1	R16C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1119_s4/O
15.910	0.011	tNET	FF	1	R16C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_10_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R16C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_10_s1/CLK
16.551	-0.296	tSu		1	R16C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_10_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 9.426, 59.922%; route: 5.965, 37.919%; tC2Q: 0.340, 2.159%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path25

Path Summary:

Slack	0.694
Data Arrival Time	15.857
Data Required Time	16.551
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_14_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/CLK
0.520	0.340	tC2Q	RF	77	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q
1.860	1.340	tNET	FF	1	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I1
2.469	0.609	tINS	FF	5	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
2.481	0.012	tNET	FF	1	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
3.268	0.786	tINS	FR	7	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
3.581	0.313	tNET	RR	1	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
4.045	0.464	tINS	RF	4	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
4.057	0.012	tNET	FF	1	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
4.871	0.814	tINS	FF	5	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
5.238	0.366	tNET	FF	1	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
5.832	0.594	tINS	FR	2	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
6.145	0.313	tNET	RR	1	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
6.609	0.464	tINS	RF	10	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
7.229	0.620	tNET	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
7.693	0.464	tINS	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
8.302	0.608	tNET	FF	2	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
8.709	0.408	tINS	FR	1	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
8.709	0.000	tNET	RR	2	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
8.751	0.042	tINS	RF	1	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
8.751	0.000	tNET	FF	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
8.794	0.042	tINS	FF	1	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
8.794	0.000	tNET	FF	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
9.185	0.391	tINS	FR	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
9.498	0.313	tNET	RR	1	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
10.313	0.814	tINS	RF	9	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
10.691	0.379	tNET	FF	1	R13C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/I0
11.506	0.814	tINS	FF	22	R13C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/F
12.126	0.620	tNET	FF	1	R14C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/I3
12.891	0.765	tINS	FF	15	R14C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/F
13.627	0.736	tNET	FF	1	R18C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s18/I2
14.413	0.786	tINS	FR	1	R18C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s18/F
14.413	0.000	tNET	RR	1	R18C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s14/I0
14.524	0.111	tINS	RR	1	R18C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s14/O
14.524	0.000	tNET	RR	1	R18C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s5/I0
14.656	0.131	tINS	RR	1	R18C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s5/O
14.971	0.316	tNET	RR	1	R18C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1115_s10/I0
15.736	0.765	tINS	RF	1	R18C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1115_s10/F
15.736	0.000	tNET	FF	1	R18C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1115_s4/I1
15.846	0.110	tINS	FF	1	R18C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1115_s4/O
15.857	0.011	tNET	FF	1	R18C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_14_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R18C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_14_s1/CLK
16.551	-0.296	tSu		1	R18C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_14_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 9.376, 59.808%; route: 5.961, 38.026%; tC2Q: 0.340, 2.166%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path26

Path Summary:

Slack	0.727
Data Arrival Time	15.825
Data Required Time	16.551
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_7_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/CLK
0.520	0.340	tC2Q	RF	77	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q
1.860	1.340	tNET	FF	1	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I1
2.469	0.609	tINS	FF	5	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
2.481	0.012	tNET	FF	1	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
3.268	0.786	tINS	FR	7	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
3.581	0.313	tNET	RR	1	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
4.045	0.464	tINS	RF	4	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
4.057	0.012	tNET	FF	1	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
4.871	0.814	tINS	FF	5	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
5.238	0.366	tNET	FF	1	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
5.832	0.594	tINS	FR	2	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
6.145	0.313	tNET	RR	1	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
6.609	0.464	tINS	RF	10	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
7.229	0.620	tNET	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
7.693	0.464	tINS	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
8.302	0.608	tNET	FF	2	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
8.709	0.408	tINS	FR	1	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
8.709	0.000	tNET	RR	2	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
8.751	0.042	tINS	RF	1	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
8.751	0.000	tNET	FF	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
8.794	0.042	tINS	FF	1	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
8.794	0.000	tNET	FF	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
9.185	0.391	tINS	FR	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
9.498	0.313	tNET	RR	1	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
10.313	0.814	tINS	RF	9	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
10.691	0.379	tNET	FF	1	R13C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/I0
11.506	0.814	tINS	FF	22	R13C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/F
12.126	0.620	tNET	FF	1	R14C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/I3
12.891	0.765	tINS	FF	15	R14C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/F
13.620	0.730	tNET	FF	1	R15C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1046_s13/I2
14.381	0.760	tINS	FR	1	R15C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1046_s13/F
14.381	0.000	tNET	RR	1	R15C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1046_s9/I0
14.492	0.111	tINS	RR	1	R15C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1046_s9/O
14.492	0.000	tNET	RR	1	R15C11[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1046_s5/I0
14.623	0.131	tINS	RR	1	R15C11[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1046_s5/O
14.938	0.316	tNET	RR	1	R15C11[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1122_s7/I0
15.703	0.765	tINS	RF	1	R15C11[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1122_s7/F
15.703	0.000	tNET	FF	1	R15C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1122_s4/I1
15.814	0.110	tINS	FF	1	R15C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1122_s4/O
15.825	0.011	tNET	FF	1	R15C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R15C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_7_s1/CLK
16.551	-0.296	tSu		1	R15C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_7_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 9.350, 59.767%; route: 5.954, 38.062%; tC2Q: 0.340, 2.171%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path27

Path Summary:

Slack	0.759
Data Arrival Time	7.457
Data Required Time	8.216
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_7_s1
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	1	R20C12[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3/CLK
0.519	0.340	tC2Q	RF	10	R20C12[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3/Q
1.623	1.104	tNET	FF	1	R20C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n105_s6/I2
2.437	0.814	tINS	FF	17	R20C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n105_s6/F
3.077	0.640	tNET	FF	1	R21C8[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n317_s11/I3
3.837	0.760	tINS	FR	1	R21C8[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n317_s11/F
4.148	0.310	tNET	RR	1	R22C8[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n317_s9/I1
4.962	0.814	tINS	RF	2	R22C8[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n317_s9/F
5.561	0.599	tNET	FF	1	R21C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n317_s8/I0
6.171	0.609	tINS	FF	1	R21C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n317_s8/F
6.175	0.004	tNET	FF	1	R21C7[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n317_s6/I1
6.638	0.464	tINS	FF	1	R21C7[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n317_s6/F
6.643	0.004	tNET	FF	1	R21C7[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n317_s5/I0
7.457	0.814	tINS	FF	1	R21C7[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n317_s5/F
7.457	0.000	tNET	FF	1	R21C7[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R21C7[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_7_s1/CLK
8.216	-0.296	tSu		1	R21C7[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_7_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 4.276, 58.760%; route: 2.662, 36.573%; tC2Q: 0.340, 4.667%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path28

Path Summary:

Slack	0.771
Data Arrival Time	15.780
Data Required Time	16.551
From	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_dataout_6_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	4	BSRAM_R28[14]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKB
2.745	2.564	tC2Q	RF	1	BSRAM_R28[14]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DO[2]
4.783	2.038	tNET	FF	1	R11C38[3][A]	usb_fifo/o_usb_txdat_6_s21/I1
5.246	0.464	tINS	FF	1	R11C38[3][A]	usb_fifo/o_usb_txdat_6_s21/F
5.246	0.000	tNET	FF	1	R11C38[3][A]	usb_fifo/o_usb_txdat_6_s20/I0
5.357	0.110	tINS	FF	1	R11C38[3][A]	usb_fifo/o_usb_txdat_6_s20/O
7.048	1.691	tNET	FF	1	R7C26[2][A]	usb_txdat_6_s3/I0
7.657	0.609	tINS	FF	2	R7C26[2][A]	usb_txdat_6_s3/F
8.383	0.726	tNET	FF	1	R5C24[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s22/I1
8.992	0.609	tINS	FF	1	R5C24[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s22/F
8.996	0.004	tNET	FF	1	R5C24[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s21/I0
9.810	0.814	tINS	FF	1	R5C24[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s21/F
10.173	0.363	tNET	FF	1	R5C22[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s17/I3
10.938	0.765	tINS	FF	1	R5C22[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s17/F
11.546	0.608	tNET	FF	1	R5C24[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s15/I1
12.156	0.609	tINS	FF	2	R5C24[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s15/F
12.756	0.600	tNET	FF	1	R4C22[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s14/I1
13.516	0.760	tINS	FR	1	R4C22[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s14/F
13.826	0.310	tNET	RR	1	R5C22[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s12/I3
14.591	0.765	tINS	RF	2	R5C22[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s12/F
15.780	1.189	tNET	FF	1	R7C22[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_dataout_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R7C22[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_dataout_6_s0/CLK
16.551	-0.296	tSu		1	R7C22[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_dataout_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.506, 35.293%; route: 7.530, 48.271%; tC2Q: 2.564, 16.435%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path29

Path Summary:

Slack	0.773
Data Arrival Time	15.779
Data Required Time	16.551
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_8_s4
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R18C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/CLK
0.520	0.340	tC2Q	RR	1	R18C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/Q
0.769	0.249	tNET	RR	1	R18C20[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_15_s10/I3
1.584	0.814	tINS	RF	34	R18C20[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_15_s10/F
4.628	3.044	tNET	FF	1	R25C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/n2208_s3/I1
5.092	0.464	tINS	FF	17	R25C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/n2208_s3/F
5.960	0.868	tNET	FF	1	R25C25[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s15/I0
6.725	0.765	tINS	FF	1	R25C25[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s15/F
6.729	0.004	tNET	FF	1	R25C25[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s11/I0
7.494	0.765	tINS	FF	1	R25C25[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s11/F
7.498	0.004	tNET	FF	1	R25C25[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s8/I2
7.961	0.464	tINS	FF	2	R25C25[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s8/F
10.720	2.759	tNET	FF	2	R20C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1411_s0/I1
11.494	0.774	tINS	FF	1	R20C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1411_s0/COUT
11.494	0.000	tNET	FF	2	R20C15[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1412_s0/CIN
11.537	0.042	tINS	FF	1	R20C15[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1412_s0/COUT
11.537	0.000	tNET	FF	2	R20C15[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1413_s0/CIN
11.579	0.042	tINS	FF	1	R20C15[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1413_s0/COUT
11.579	0.000	tNET	FF	2	R20C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1414_s0/CIN
11.621	0.042	tINS	FF	1	R20C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1414_s0/COUT
11.621	0.000	tNET	FF	2	R20C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1415_s0/CIN
11.663	0.042	tINS	FF	1	R20C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1415_s0/COUT
11.663	0.000	tNET	FF	2	R20C16[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1416_s0/CIN
11.706	0.042	tINS	FF	1	R20C16[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1416_s0/COUT
11.706	0.000	tNET	FF	2	R20C16[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1417_s0/CIN
11.748	0.042	tINS	FF	1	R20C16[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1417_s0/COUT
11.748	0.000	tNET	FF	2	R20C16[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1418_s0/CIN
11.790	0.042	tINS	FF	1	R20C16[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1418_s0/COUT
11.790	0.000	tNET	FF	2	R20C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1419_s0/CIN
11.832	0.042	tINS	FF	1	R20C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1419_s0/COUT
11.832	0.000	tNET	FF	2	R20C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1420_s0/CIN
11.875	0.042	tINS	FF	1	R20C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1420_s0/COUT
11.875	0.000	tNET	FF	2	R20C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1421_s0/CIN
11.917	0.042	tINS	FF	1	R20C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1421_s0/COUT
11.917	0.000	tNET	FF	2	R20C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1422_s0/CIN
11.959	0.042	tINS	FF	1	R20C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1422_s0/COUT
11.959	0.000	tNET	FF	2	R20C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1423_s0/CIN
12.001	0.042	tINS	FF	1	R20C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1423_s0/COUT
12.001	0.000	tNET	FF	2	R20C17[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1424_s0/CIN
12.044	0.042	tINS	FF	3	R20C17[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1424_s0/COUT
12.827	0.784	tNET	FF	1	R20C19[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1688_s39/I2
13.592	0.765	tINS	FF	3	R20C19[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1688_s39/F
14.195	0.603	tNET	FF	1	R18C18[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1688_s36/I0
15.010	0.814	tINS	FF	1	R18C18[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1688_s36/F
15.014	0.004	tNET	FF	1	R18C18[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1688_s35/I2
15.779	0.765	tINS	FF	1	R18C18[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1688_s35/F
15.779	0.000	tNET	FF	1	R18C18[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_8_s4/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R18C18[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_8_s4/CLK
16.551	-0.296	tSu		1	R18C18[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_8_s4

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	12
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 6.939, 44.485%; route: 8.319, 53.337%; tC2Q: 0.340, 2.177%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path30

Path Summary:

Slack	0.793
Data Arrival Time	15.759
Data Required Time	16.551
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_3_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R18C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/CLK
0.520	0.340	tC2Q	RR	1	R18C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/Q
0.769	0.249	tNET	RR	1	R18C20[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_15_s10/I3
1.584	0.814	tINS	RF	34	R18C20[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_15_s10/F
4.628	3.044	tNET	FF	1	R25C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/n2208_s3/I1
5.092	0.464	tINS	FF	17	R25C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/n2208_s3/F
5.960	0.868	tNET	FF	1	R25C25[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s15/I0
6.725	0.765	tINS	FF	1	R25C25[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s15/F
6.729	0.004	tNET	FF	1	R25C25[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s11/I0
7.494	0.765	tINS	FF	1	R25C25[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s11/F
7.498	0.004	tNET	FF	1	R25C25[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s8/I2
7.961	0.464	tINS	FF	2	R25C25[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s8/F
10.720	2.759	tNET	FF	2	R20C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1411_s0/I1
11.494	0.774	tINS	FF	1	R20C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1411_s0/COUT
11.494	0.000	tNET	FF	2	R20C15[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1412_s0/CIN
11.537	0.042	tINS	FF	1	R20C15[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1412_s0/COUT
11.537	0.000	tNET	FF	2	R20C15[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1413_s0/CIN
11.579	0.042	tINS	FF	1	R20C15[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1413_s0/COUT
11.579	0.000	tNET	FF	2	R20C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1414_s0/CIN
11.621	0.042	tINS	FF	1	R20C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1414_s0/COUT
11.621	0.000	tNET	FF	2	R20C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1415_s0/CIN
11.663	0.042	tINS	FF	1	R20C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1415_s0/COUT
11.663	0.000	tNET	FF	2	R20C16[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1416_s0/CIN
11.706	0.042	tINS	FF	1	R20C16[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1416_s0/COUT
11.706	0.000	tNET	FF	2	R20C16[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1417_s0/CIN
11.748	0.042	tINS	FF	1	R20C16[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1417_s0/COUT
11.748	0.000	tNET	FF	2	R20C16[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1418_s0/CIN
11.790	0.042	tINS	FF	1	R20C16[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1418_s0/COUT
11.790	0.000	tNET	FF	2	R20C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1419_s0/CIN
11.832	0.042	tINS	FF	1	R20C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1419_s0/COUT
11.832	0.000	tNET	FF	2	R20C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1420_s0/CIN
11.875	0.042	tINS	FF	1	R20C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1420_s0/COUT
11.875	0.000	tNET	FF	2	R20C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1421_s0/CIN
11.917	0.042	tINS	FF	1	R20C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1421_s0/COUT
11.917	0.000	tNET	FF	2	R20C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1422_s0/CIN
11.959	0.042	tINS	FF	1	R20C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1422_s0/COUT
11.959	0.000	tNET	FF	2	R20C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1423_s0/CIN
12.001	0.042	tINS	FF	1	R20C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1423_s0/COUT
12.001	0.000	tNET	FF	2	R20C17[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1424_s0/CIN
12.044	0.042	tINS	FF	3	R20C17[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1424_s0/COUT
12.824	0.780	tNET	FF	1	R20C18[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1686_s38/I0
13.584	0.760	tINS	FR	3	R20C18[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1686_s38/F
13.896	0.312	tNET	RR	1	R20C19[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1669_s12/I0
14.682	0.786	tINS	RR	2	R20C19[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1669_s12/F
14.994	0.312	tNET	RR	1	R20C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1669_s11/I1
15.759	0.765	tINS	RF	1	R20C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1669_s11/F
15.759	0.000	tNET	FF	1	R20C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R20C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_3_s0/CLK
16.551	-0.296	tSu		1	R20C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	12
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 6.906, 44.333%; route: 8.332, 53.487%; tC2Q: 0.340, 2.180%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path31

Path Summary:

Slack	0.893
Data Arrival Time	15.923
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_7_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.422	1.098	tNET	FF	1	R5C19[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s8/I3
14.208	0.786	tINS	FR	9	R5C19[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s8/F
15.923	1.715	tNET	RR	1	R6C18[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_7_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R6C18[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_7_s0/CLK
16.816	-0.032	tSu		1	R6C18[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.782, 36.730%; route: 9.621, 61.113%; tC2Q: 0.340, 2.157%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path32

Path Summary:

Slack	0.960
Data Arrival Time	7.256
Data Required Time	8.216
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/dru_locked_s2
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	8	IOB15[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/PCLK
0.579	0.400	tC2Q	RF	5	IOB15[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/Q5
2.035	1.455	tNET	FF	1	R25C11[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s29/I3
2.795	0.760	tINS	FR	1	R25C11[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s29/F
3.105	0.310	tNET	RR	1	R25C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s23/I0
3.870	0.765	tINS	RF	1	R25C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s23/F
3.874	0.004	tNET	FF	1	R25C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s14/I2
4.639	0.765	tINS	FF	1	R25C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s14/F
4.643	0.004	tNET	FF	1	R25C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s5/I1
5.252	0.609	tINS	FF	5	R25C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s5/F
5.974	0.722	tNET	FF	1	R24C9[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s1/I3
6.788	0.814	tINS	FF	1	R24C9[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s1/F
6.792	0.004	tNET	FF	1	R24C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n352_s3/I0
7.256	0.464	tINS	FF	1	R24C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n352_s3/F
7.256	0.000	tNET	FF	1	R24C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/dru_locked_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R24C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/dru_locked_s2/CLK
8.216	-0.296	tSu		1	R24C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/dru_locked_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 4.177, 59.023%; route: 2.500, 35.323%; tC2Q: 0.400, 5.654%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path33

Path Summary:

Slack	0.966
Data Arrival Time	7.250
Data Required Time	8.216
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/data_out_en_s0
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	1	R9C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/CLK
0.519	0.340	tC2Q	RR	5	R9C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/Q
0.836	0.317	tNET	RR	1	R9C6[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_2_s5/I2
1.622	0.786	tINS	RR	7	R9C6[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_2_s5/F
1.941	0.319	tNET	RR	1	R8C6[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_2_s3/I1
2.756	0.814	tINS	RF	2	R8C6[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_2_s3/F
2.764	0.008	tNET	FF	1	R8C6[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rgraynext_1_s1/I0
3.373	0.609	tINS	FF	2	R8C6[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rgraynext_1_s1/F
4.573	1.200	tNET	FF	2	R7C5[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n162_s0/I0
5.283	0.710	tINS	FF	1	R7C5[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n162_s0/COUT
5.283	0.000	tNET	FF	2	R7C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n163_s0/CIN
5.325	0.042	tINS	FF	1	R7C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n163_s0/COUT
5.325	0.000	tNET	FF	2	R7C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n164_s0/CIN
5.368	0.042	tINS	FF	1	R7C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n164_s0/COUT
5.368	0.000	tNET	FF	2	R7C5[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n165_s0/CIN
5.410	0.042	tINS	FF	2	R7C5[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n165_s0/COUT
6.786	1.376	tNET	FF	1	R9C7[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n648_s0/I2
7.250	0.464	tINS	FF	1	R9C7[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n648_s0/F
7.250	0.000	tNET	FF	1	R9C7[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/data_out_en_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R9C7[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/data_out_en_s0/CLK
8.216	-0.296	tSu		1	R9C7[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/data_out_en_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 3.510, 49.644%; route: 3.221, 45.553%; tC2Q: 0.340, 4.803%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path34

Path Summary:

Slack	0.978
Data Arrival Time	15.573
Data Required Time	16.551
From	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/crc16_buf_0_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	4	BSRAM_R28[14]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKB
2.745	2.564	tC2Q	RF	1	BSRAM_R28[14]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DO[1]
4.783	2.038	tNET	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s21/I1
5.597	0.814	tINS	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s21/F
5.597	0.000	tNET	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s20/I0
5.707	0.110	tINS	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s20/O
7.510	1.802	tNET	FF	1	R6C32[3][A]	usb_txdat_5_s3/I0
7.973	0.464	tINS	FF	2	R6C32[3][A]	usb_txdat_5_s3/F
9.055	1.081	tNET	FF	1	R5C23[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s10/I1
9.518	0.463	tINS	FR	1	R5C23[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s10/F
9.828	0.310	tNET	RR	1	R5C22[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s9/I0
10.642	0.814	tINS	RF	1	R5C22[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s9/F
10.647	0.004	tNET	FF	1	R5C22[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s6/I2
11.256	0.609	tINS	FF	1	R5C22[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s6/F
11.852	0.596	tNET	FF	1	R4C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s4/I1
12.638	0.786	tINS	FR	2	R4C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s4/F
12.951	0.313	tNET	RR	1	R5C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s3/I1
13.545	0.594	tINS	RR	4	R5C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s3/F
13.862	0.316	tNET	RR	1	R5C20[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n776_s5/I2
14.648	0.786	tINS	RR	3	R5C20[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n776_s5/F
14.964	0.316	tNET	RR	1	R4C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n776_s2/I2
15.573	0.609	tINS	RF	1	R4C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n776_s2/F
15.573	0.000	tNET	FF	1	R4C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/crc16_buf_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R4C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/crc16_buf_0_s1/CLK
16.551	-0.296	tSu		1	R4C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/crc16_buf_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 6.051, 39.311%; route: 6.778, 44.032%; tC2Q: 2.564, 16.657%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path35

Path Summary:

Slack	0.978
Data Arrival Time	15.573
Data Required Time	16.551
From	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/crc16_buf_1_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	4	BSRAM_R28[14]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKB
2.745	2.564	tC2Q	RF	1	BSRAM_R28[14]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DO[1]
4.783	2.038	tNET	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s21/I1
5.597	0.814	tINS	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s21/F
5.597	0.000	tNET	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s20/I0
5.707	0.110	tINS	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s20/O
7.510	1.802	tNET	FF	1	R6C32[3][A]	usb_txdat_5_s3/I0
7.973	0.464	tINS	FF	2	R6C32[3][A]	usb_txdat_5_s3/F
9.055	1.081	tNET	FF	1	R5C23[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s10/I1
9.518	0.463	tINS	FR	1	R5C23[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s10/F
9.828	0.310	tNET	RR	1	R5C22[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s9/I0
10.642	0.814	tINS	RF	1	R5C22[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s9/F
10.647	0.004	tNET	FF	1	R5C22[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s6/I2
11.256	0.609	tINS	FF	1	R5C22[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s6/F
11.852	0.596	tNET	FF	1	R4C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s4/I1
12.638	0.786	tINS	FR	2	R4C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s4/F
12.951	0.313	tNET	RR	1	R5C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s3/I1
13.545	0.594	tINS	RR	4	R5C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s3/F
13.862	0.316	tNET	RR	1	R5C20[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n776_s5/I2
14.648	0.786	tINS	RR	3	R5C20[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n776_s5/F
14.964	0.316	tNET	RR	1	R4C20[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n775_s3/I1
15.573	0.609	tINS	RF	1	R4C20[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n775_s3/F
15.573	0.000	tNET	FF	1	R4C20[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/crc16_buf_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R4C20[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/crc16_buf_1_s1/CLK
16.551	-0.296	tSu		1	R4C20[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/crc16_buf_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 6.051, 39.311%; route: 6.778, 44.032%; tC2Q: 2.564, 16.657%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path36

Path Summary:

Slack	0.978
Data Arrival Time	15.573
Data Required Time	16.551
From	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/crc16_buf_15_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	4	BSRAM_R28[14]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKB
2.745	2.564	tC2Q	RF	1	BSRAM_R28[14]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DO[1]
4.783	2.038	tNET	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s21/I1
5.597	0.814	tINS	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s21/F
5.597	0.000	tNET	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s20/I0
5.707	0.110	tINS	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s20/O
7.510	1.802	tNET	FF	1	R6C32[3][A]	usb_txdat_5_s3/I0
7.973	0.464	tINS	FF	2	R6C32[3][A]	usb_txdat_5_s3/F
9.055	1.081	tNET	FF	1	R5C23[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s10/I1
9.518	0.463	tINS	FR	1	R5C23[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s10/F
9.828	0.310	tNET	RR	1	R5C22[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s9/I0
10.642	0.814	tINS	RF	1	R5C22[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s9/F
10.647	0.004	tNET	FF	1	R5C22[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s6/I2
11.256	0.609	tINS	FF	1	R5C22[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s6/F
11.852	0.596	tNET	FF	1	R4C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s4/I1
12.638	0.786	tINS	FR	2	R4C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s4/F
12.951	0.313	tNET	RR	1	R5C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s3/I1
13.545	0.594	tINS	RR	4	R5C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s3/F
13.862	0.316	tNET	RR	1	R5C20[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n776_s5/I2
14.648	0.786	tINS	RR	3	R5C20[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n776_s5/F
14.964	0.316	tNET	RR	1	R4C20[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n761_s2/I1
15.573	0.609	tINS	RF	1	R4C20[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n761_s2/F
15.573	0.000	tNET	FF	1	R4C20[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/crc16_buf_15_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R4C20[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/crc16_buf_15_s1/CLK
16.551	-0.296	tSu		1	R4C20[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/crc16_buf_15_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 6.051, 39.311%; route: 6.778, 44.032%; tC2Q: 2.564, 16.657%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path37

Path Summary:

Slack	0.985
Data Arrival Time	15.567
Data Required Time	16.551
From	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_6_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	4	BSRAM_R28[14]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKB
2.745	2.564	tC2Q	RF	1	BSRAM_R28[14]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DO[2]
4.783	2.038	tNET	FF	1	R11C38[3][A]	usb_fifo/o_usb_txdat_6_s21/I1
5.246	0.464	tINS	FF	1	R11C38[3][A]	usb_fifo/o_usb_txdat_6_s21/F
5.246	0.000	tNET	FF	1	R11C38[3][A]	usb_fifo/o_usb_txdat_6_s20/I0
5.357	0.110	tINS	FF	1	R11C38[3][A]	usb_fifo/o_usb_txdat_6_s20/O
7.048	1.691	tNET	FF	1	R7C26[2][A]	usb_txdat_6_s3/I0
7.657	0.609	tINS	FF	2	R7C26[2][A]	usb_txdat_6_s3/F
8.383	0.726	tNET	FF	1	R5C24[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s22/I1
8.992	0.609	tINS	FF	1	R5C24[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s22/F
8.996	0.004	tNET	FF	1	R5C24[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s21/I0
9.810	0.814	tINS	FF	1	R5C24[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s21/F
10.173	0.363	tNET	FF	1	R5C22[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s17/I3
10.938	0.765	tINS	FF	1	R5C22[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s17/F
11.546	0.608	tNET	FF	1	R5C24[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s15/I1
12.156	0.609	tINS	FF	2	R5C24[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s15/F
12.756	0.600	tNET	FF	1	R4C22[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s14/I1
13.516	0.760	tINS	FR	1	R4C22[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s14/F
13.826	0.310	tNET	RR	1	R5C22[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s12/I3
14.591	0.765	tINS	RF	2	R5C22[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s12/F
14.957	0.366	tNET	FF	1	R7C22[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n779_s0/I0
15.567	0.609	tINS	FF	1	R7C22[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n779_s0/F
15.567	0.000	tNET	FF	1	R7C22[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R7C22[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_6_s0/CLK
16.551	-0.296	tSu		1	R7C22[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 6.115, 39.743%; route: 6.707, 43.594%; tC2Q: 2.564, 16.664%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path38

Path Summary:

Slack	0.996
Data Arrival Time	15.555
Data Required Time	16.551
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_4_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/CLK
0.520	0.340	tC2Q	RF	77	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q
1.860	1.340	tNET	FF	1	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I1
2.469	0.609	tINS	FF	5	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
2.481	0.012	tNET	FF	1	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
3.268	0.786	tINS	FR	7	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
3.581	0.313	tNET	RR	1	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
4.045	0.464	tINS	RF	4	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
4.057	0.012	tNET	FF	1	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
4.871	0.814	tINS	FF	5	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
5.238	0.366	tNET	FF	1	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
5.832	0.594	tINS	FR	2	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
6.145	0.313	tNET	RR	1	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
6.609	0.464	tINS	RF	10	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
7.229	0.620	tNET	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
7.693	0.464	tINS	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
8.302	0.608	tNET	FF	2	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
8.709	0.408	tINS	FR	1	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
8.709	0.000	tNET	RR	2	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
8.751	0.042	tINS	RF	1	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
8.751	0.000	tNET	FF	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
9.143	0.391	tINS	FR	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/SUM
9.454	0.312	tNET	RR	1	R13C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s9/I1
9.918	0.464	tINS	RF	6	R13C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s9/F
10.522	0.603	tNET	FF	1	R14C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s6/I3
10.986	0.464	tINS	FF	4	R14C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s6/F
11.602	0.617	tNET	FF	1	R13C11[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n925_s2/I1
12.066	0.464	tINS	FF	18	R13C11[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n925_s2/F
13.652	1.585	tNET	FF	1	R16C8[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1049_s12/I2
14.412	0.760	tINS	FR	1	R16C8[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1049_s12/F
14.412	0.000	tNET	RR	1	R16C8[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1049_s10/I1
14.523	0.111	tINS	RR	1	R16C8[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1049_s10/O
14.523	0.000	tNET	RR	1	R16C8[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1049_s5/I1
14.654	0.131	tINS	RR	1	R16C8[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1049_s5/O
14.970	0.316	tNET	RR	1	R16C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1125_s7/I0
15.434	0.464	tINS	RF	1	R16C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1125_s7/F
15.434	0.000	tNET	FF	1	R16C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1125_s4/I1
15.544	0.110	tINS	FF	1	R16C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1125_s4/O
15.555	0.011	tNET	FF	1	R16C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R16C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_4_s1/CLK
16.551	-0.296	tSu		1	R16C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_4_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 8.005, 52.066%; route: 7.030, 45.725%; tC2Q: 0.340, 2.209%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path39

Path Summary:

Slack	1.003
Data Arrival Time	15.812
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_TXVALID_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.422	1.098	tNET	FF	1	R5C19[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s8/I3
14.236	0.814	tINS	FF	9	R5C19[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s8/F
14.969	0.733	tNET	FF	1	R6C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_TXVALID_s4/I3
15.563	0.594	tINS	FR	1	R6C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_TXVALID_s4/F
15.812	0.249	tNET	RR	1	R6C21[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_TXVALID_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R6C21[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_TXVALID_s1/CLK
16.816	-0.032	tSu		1	R6C21[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_TXVALID_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 6.404, 40.971%; route: 8.888, 56.856%; tC2Q: 0.340, 2.173%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path40

Path Summary:

Slack	1.006
Data Arrival Time	7.210
Data Required Time	8.216
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_4_s1
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	1	R20C12[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3/CLK
0.519	0.340	tC2Q	RF	10	R20C12[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3/Q
1.623	1.104	tNET	FF	1	R20C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n105_s6/I2
2.437	0.814	tINS	FF	17	R20C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n105_s6/F
3.688	1.251	tNET	FF	1	R22C8[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n320_s11/I3
4.453	0.765	tINS	FF	1	R22C8[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n320_s11/F
4.457	0.004	tNET	FF	1	R22C8[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n320_s9/I1
5.051	0.594	tINS	FR	2	R22C8[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n320_s9/F
5.364	0.313	tNET	RR	1	R22C7[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n320_s8/I0
5.828	0.464	tINS	RF	1	R22C7[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n320_s8/F
5.832	0.004	tNET	FF	1	R22C7[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n320_s6/I1
6.597	0.765	tINS	FF	1	R22C7[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n320_s6/F
6.601	0.004	tNET	FF	1	R22C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n320_s5/I0
7.210	0.609	tINS	FF	1	R22C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n320_s5/F
7.210	0.000	tNET	FF	1	R22C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R22C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_4_s1/CLK
8.216	-0.296	tSu		1	R22C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_4_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 4.011, 57.049%; route: 2.680, 38.120%; tC2Q: 0.340, 4.831%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path41

Path Summary:

Slack	1.015
Data Arrival Time	15.536
Data Required Time	16.551
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/CLK
0.520	0.340	tC2Q	RF	77	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q
1.860	1.340	tNET	FF	1	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I1
2.469	0.609	tINS	FF	5	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
2.481	0.012	tNET	FF	1	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
3.268	0.786	tINS	FR	7	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
3.581	0.313	tNET	RR	1	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
4.045	0.464	tINS	RF	4	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
4.057	0.012	tNET	FF	1	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
4.871	0.814	tINS	FF	5	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
5.238	0.366	tNET	FF	1	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
5.832	0.594	tINS	FR	2	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
6.145	0.313	tNET	RR	1	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
6.609	0.464	tINS	RF	10	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
7.229	0.620	tNET	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
7.693	0.464	tINS	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
8.302	0.608	tNET	FF	2	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
8.709	0.408	tINS	FR	1	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
8.709	0.000	tNET	RR	2	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
8.751	0.042	tINS	RF	1	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
8.751	0.000	tNET	FF	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
8.794	0.042	tINS	FF	1	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
8.794	0.000	tNET	FF	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
9.185	0.391	tINS	FR	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
9.498	0.313	tNET	RR	1	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
10.313	0.814	tINS	RF	9	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
10.941	0.628	tNET	FF	1	R14C10[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1001_s6/I1
11.550	0.609	tINS	FF	15	R14C10[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1001_s6/F
13.497	1.947	tNET	FF	1	R15C9[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1048_s14/I2
14.092	0.594	tINS	FR	1	R15C9[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1048_s14/F
14.092	0.000	tNET	RR	1	R15C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1048_s9/I1
14.203	0.111	tINS	RR	1	R15C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1048_s9/O
14.203	0.000	tNET	RR	1	R15C9[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1048_s5/I0
14.334	0.131	tINS	RR	1	R15C9[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1048_s5/O
14.650	0.316	tNET	RR	1	R15C9[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1124_s7/I0
15.414	0.765	tINS	RF	1	R15C9[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1124_s7/F
15.414	0.000	tNET	FF	1	R15C9[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1124_s4/I1
15.525	0.110	tINS	FF	1	R15C9[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1124_s4/O
15.536	0.011	tNET	FF	1	R15C9[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R15C9[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/CLK
16.551	-0.296	tSu		1	R15C9[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	15
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 8.214, 53.493%; route: 6.802, 44.295%; tC2Q: 0.340, 2.212%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path42

Path Summary:

Slack	1.017
Data Arrival Time	15.534
Data Required Time	16.551
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_13_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/CLK
0.520	0.340	tC2Q	RF	77	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q
1.860	1.340	tNET	FF	1	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I1
2.469	0.609	tINS	FF	5	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
2.481	0.012	tNET	FF	1	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
3.268	0.786	tINS	FR	7	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
3.581	0.313	tNET	RR	1	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
4.045	0.464	tINS	RF	4	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
4.057	0.012	tNET	FF	1	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
4.871	0.814	tINS	FF	5	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
5.238	0.366	tNET	FF	1	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
5.832	0.594	tINS	FR	2	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
6.145	0.313	tNET	RR	1	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
6.609	0.464	tINS	RF	10	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
7.229	0.620	tNET	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
7.693	0.464	tINS	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
8.302	0.608	tNET	FF	2	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
8.709	0.408	tINS	FR	1	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
8.709	0.000	tNET	RR	2	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
8.751	0.042	tINS	RF	1	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
8.751	0.000	tNET	FF	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
8.794	0.042	tINS	FF	1	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
8.794	0.000	tNET	FF	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
9.185	0.391	tINS	FR	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
9.498	0.313	tNET	RR	1	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
10.313	0.814	tINS	RF	9	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
10.691	0.379	tNET	FF	1	R13C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/I0
11.506	0.814	tINS	FF	22	R13C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/F
12.126	0.620	tNET	FF	1	R14C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/I3
12.891	0.765	tINS	FF	15	R14C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/F
13.630	0.740	tNET	FF	1	R17C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1040_s13/I2
14.391	0.760	tINS	FR	1	R17C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1040_s13/F
14.391	0.000	tNET	RR	1	R17C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1040_s9/I0
14.502	0.111	tINS	RR	1	R17C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1040_s9/O
14.502	0.000	tNET	RR	1	R17C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1040_s5/I0
14.633	0.131	tINS	RR	1	R17C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1040_s5/O
14.949	0.316	tNET	RR	1	R17C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1116_s7/I0
15.412	0.464	tINS	RF	1	R17C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1116_s7/F
15.412	0.000	tNET	FF	1	R17C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1116_s4/I1
15.523	0.110	tINS	FF	1	R17C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1116_s4/O
15.534	0.011	tNET	FF	1	R17C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_13_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R17C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_13_s1/CLK
16.551	-0.296	tSu		1	R17C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_13_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 9.049, 58.939%; route: 5.965, 38.849%; tC2Q: 0.340, 2.212%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path43

Path Summary:

Slack	1.041
Data Arrival Time	15.510
Data Required Time	16.551
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_6_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/CLK
0.520	0.340	tC2Q	RF	77	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q
1.860	1.340	tNET	FF	1	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I1
2.469	0.609	tINS	FF	5	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
2.481	0.012	tNET	FF	1	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
3.268	0.786	tINS	FR	7	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
3.581	0.313	tNET	RR	1	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
4.045	0.464	tINS	RF	4	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
4.057	0.012	tNET	FF	1	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
4.871	0.814	tINS	FF	5	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
5.238	0.366	tNET	FF	1	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
5.832	0.594	tINS	FR	2	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
6.145	0.313	tNET	RR	1	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
6.609	0.464	tINS	RF	10	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
7.229	0.620	tNET	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
7.693	0.464	tINS	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
8.302	0.608	tNET	FF	2	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
8.709	0.408	tINS	FR	1	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
8.709	0.000	tNET	RR	2	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
8.751	0.042	tINS	RF	1	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
8.751	0.000	tNET	FF	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
9.143	0.391	tINS	FR	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/SUM
9.454	0.312	tNET	RR	1	R13C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s9/I1
9.918	0.464	tINS	RF	6	R13C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s9/F
10.522	0.603	tNET	FF	1	R14C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s6/I3
10.986	0.464	tINS	FF	4	R14C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s6/F
11.602	0.617	tNET	FF	1	R13C11[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n925_s2/I1
12.066	0.464	tINS	FF	18	R13C11[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n925_s2/F
13.758	1.692	tNET	FF	1	R16C9[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1047_s12/I2
14.222	0.463	tINS	FR	1	R16C9[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1047_s12/F
14.222	0.000	tNET	RR	1	R16C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1047_s10/I1
14.333	0.111	tINS	RR	1	R16C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1047_s10/O
14.333	0.000	tNET	RR	1	R16C9[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1047_s5/I1
14.464	0.131	tINS	RR	1	R16C9[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1047_s5/O
14.779	0.316	tNET	RR	1	R16C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1123_s7/I0
15.389	0.609	tINS	RF	1	R16C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1123_s7/F
15.389	0.000	tNET	FF	1	R16C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1123_s4/I1
15.499	0.110	tINS	FF	1	R16C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1123_s4/O
15.510	0.011	tNET	FF	1	R16C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R16C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_6_s1/CLK
16.551	-0.296	tSu		1	R16C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_6_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 7.853, 51.229%; route: 7.137, 46.556%; tC2Q: 0.340, 2.216%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path44

Path Summary:

Slack	1.052
Data Arrival Time	7.429
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s1
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	8	IOB15[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/PCLK
0.579	0.400	tC2Q	RF	5	IOB15[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/Q5
2.035	1.455	tNET	FF	1	R25C11[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s29/I3
2.795	0.760	tINS	FR	1	R25C11[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s29/F
3.105	0.310	tNET	RR	1	R25C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s23/I0
3.870	0.765	tINS	RF	1	R25C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s23/F
3.874	0.004	tNET	FF	1	R25C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s14/I2
4.639	0.765	tINS	FF	1	R25C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s14/F
4.643	0.004	tNET	FF	1	R25C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s5/I1
5.252	0.609	tINS	FF	5	R25C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s5/F
5.622	0.370	tNET	FF	1	R23C10[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s9/I1
6.386	0.765	tINS	FF	2	R23C10[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s9/F
6.395	0.008	tNET	FF	1	R23C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s13/I2
7.155	0.760	tINS	FR	1	R23C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s13/F
7.429	0.274	tNET	RR	1	R23C9[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R23C9[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s1/CLK
8.480	-0.032	tSu		1	R23C9[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 4.424, 61.023%; route: 2.425, 33.457%; tC2Q: 0.400, 5.520%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path45

Path Summary:

Slack	1.075
Data Arrival Time	15.477
Data Required Time	16.551
From	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_dataout_5_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	4	BSRAM_R28[14]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKB
2.745	2.564	tC2Q	RF	1	BSRAM_R28[14]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DO[1]
4.783	2.038	tNET	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s21/I1
5.597	0.814	tINS	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s21/F
5.597	0.000	tNET	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s20/I0
5.707	0.110	tINS	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s20/O
7.510	1.802	tNET	FF	1	R6C32[3][A]	usb_txdat_5_s3/I0
7.973	0.464	tINS	FF	2	R6C32[3][A]	usb_txdat_5_s3/F
9.055	1.081	tNET	FF	1	R5C23[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s10/I1
9.518	0.463	tINS	FR	1	R5C23[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s10/F
9.828	0.310	tNET	RR	1	R5C22[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s9/I0
10.642	0.814	tINS	RF	1	R5C22[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s9/F
10.647	0.004	tNET	FF	1	R5C22[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s6/I2
11.256	0.609	tINS	FF	1	R5C22[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s6/F
11.852	0.596	tNET	FF	1	R4C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s4/I1
12.638	0.786	tINS	FR	2	R4C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s4/F
12.951	0.313	tNET	RR	1	R5C21[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n780_s3/I1
13.560	0.609	tINS	RF	1	R5C21[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n780_s3/F
13.564	0.004	tNET	FF	1	R5C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n780_s1/I2
14.351	0.786	tINS	FR	2	R5C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n780_s1/F
14.662	0.312	tNET	RR	1	R5C22[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n644_s12/I2
15.477	0.814	tINS	RF	1	R5C22[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n644_s12/F
15.477	0.000	tNET	FF	1	R5C22[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_dataout_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R5C22[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_dataout_5_s0/CLK
16.551	-0.296	tSu		1	R5C22[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_dataout_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 6.271, 40.998%; route: 6.461, 42.240%; tC2Q: 2.564, 16.762%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path46

Path Summary:

Slack	1.076
Data Arrival Time	7.404
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	8	IOB15[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/PCLK
0.579	0.400	tC2Q	RF	5	IOB15[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/Q5
2.035	1.455	tNET	FF	1	R25C11[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s29/I3
2.795	0.760	tINS	FR	1	R25C11[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s29/F
3.105	0.310	tNET	RR	1	R25C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s23/I0
3.870	0.765	tINS	RF	1	R25C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s23/F
3.874	0.004	tNET	FF	1	R25C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s14/I2
4.639	0.765	tINS	FF	1	R25C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s14/F
4.643	0.004	tNET	FF	1	R25C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s5/I1
5.252	0.609	tINS	FF	5	R25C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s5/F
5.622	0.370	tNET	FF	1	R23C10[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s9/I1
6.386	0.765	tINS	FF	2	R23C10[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s9/F
6.395	0.008	tNET	FF	1	R23C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s10/I2
7.155	0.760	tINS	FR	1	R23C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s10/F
7.404	0.249	tNET	RR	1	R23C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R23C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1/CLK
8.480	-0.032	tSu		1	R23C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 4.424, 61.231%; route: 2.401, 33.230%; tC2Q: 0.400, 5.539%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path47

Path Summary:

Slack	1.113
Data Arrival Time	15.438
Data Required Time	16.551
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_1_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R18C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/CLK
0.520	0.340	tC2Q	RR	1	R18C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/Q
0.769	0.249	tNET	RR	1	R18C20[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_15_s10/I3
1.584	0.814	tINS	RF	34	R18C20[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_15_s10/F
4.628	3.044	tNET	FF	1	R25C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/n2208_s3/I1
5.092	0.464	tINS	FF	17	R25C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/n2208_s3/F
5.960	0.868	tNET	FF	1	R25C25[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s15/I0
6.725	0.765	tINS	FF	1	R25C25[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s15/F
6.729	0.004	tNET	FF	1	R25C25[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s11/I0
7.494	0.765	tINS	FF	1	R25C25[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s11/F
7.498	0.004	tNET	FF	1	R25C25[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s8/I2
7.961	0.464	tINS	FF	2	R25C25[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s8/F
10.720	2.759	tNET	FF	2	R20C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1411_s0/I1
11.494	0.774	tINS	FF	1	R20C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1411_s0/COUT
11.494	0.000	tNET	FF	2	R20C15[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1412_s0/CIN
11.537	0.042	tINS	FF	1	R20C15[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1412_s0/COUT
11.537	0.000	tNET	FF	2	R20C15[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1413_s0/CIN
11.579	0.042	tINS	FF	1	R20C15[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1413_s0/COUT
11.579	0.000	tNET	FF	2	R20C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1414_s0/CIN
11.621	0.042	tINS	FF	1	R20C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1414_s0/COUT
11.621	0.000	tNET	FF	2	R20C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1415_s0/CIN
11.663	0.042	tINS	FF	1	R20C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1415_s0/COUT
11.663	0.000	tNET	FF	2	R20C16[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1416_s0/CIN
11.706	0.042	tINS	FF	1	R20C16[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1416_s0/COUT
11.706	0.000	tNET	FF	2	R20C16[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1417_s0/CIN
11.748	0.042	tINS	FF	1	R20C16[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1417_s0/COUT
11.748	0.000	tNET	FF	2	R20C16[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1418_s0/CIN
11.790	0.042	tINS	FF	1	R20C16[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1418_s0/COUT
11.790	0.000	tNET	FF	2	R20C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1419_s0/CIN
11.832	0.042	tINS	FF	1	R20C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1419_s0/COUT
11.832	0.000	tNET	FF	2	R20C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1420_s0/CIN
11.875	0.042	tINS	FF	1	R20C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1420_s0/COUT
11.875	0.000	tNET	FF	2	R20C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1421_s0/CIN
11.917	0.042	tINS	FF	1	R20C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1421_s0/COUT
11.917	0.000	tNET	FF	2	R20C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1422_s0/CIN
11.959	0.042	tINS	FF	1	R20C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1422_s0/COUT
11.959	0.000	tNET	FF	2	R20C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1423_s0/CIN
12.001	0.042	tINS	FF	1	R20C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1423_s0/COUT
12.001	0.000	tNET	FF	2	R20C17[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1424_s0/CIN
12.044	0.042	tINS	FF	3	R20C17[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1424_s0/COUT
13.186	1.143	tNET	FF	1	R20C20[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1675_s17/I2
13.947	0.760	tINS	FR	1	R20C20[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1675_s17/F
14.257	0.310	tNET	RR	1	R20C21[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1675_s11/I1
14.721	0.464	tINS	RF	2	R20C21[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1675_s11/F
15.438	0.717	tNET	FF	1	R20C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R20C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_1_s0/CLK
16.551	-0.296	tSu		1	R20C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	11
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.819, 38.140%; route: 9.099, 59.634%; tC2Q: 0.340, 2.226%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path48

Path Summary:

Slack	1.204
Data Arrival Time	15.348
Data Required Time	16.551
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_0_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/CLK
0.520	0.340	tC2Q	RF	77	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q
1.860	1.340	tNET	FF	1	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I1
2.469	0.609	tINS	FF	5	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
2.481	0.012	tNET	FF	1	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
3.268	0.786	tINS	FR	7	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
3.581	0.313	tNET	RR	1	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
4.045	0.464	tINS	RF	4	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
4.057	0.012	tNET	FF	1	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
4.871	0.814	tINS	FF	5	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
5.238	0.366	tNET	FF	1	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
5.832	0.594	tINS	FR	2	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
6.145	0.313	tNET	RR	1	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
6.609	0.464	tINS	RF	10	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
7.229	0.620	tNET	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
7.693	0.464	tINS	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
8.302	0.608	tNET	FF	2	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
8.709	0.408	tINS	FR	1	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
8.709	0.000	tNET	RR	2	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
8.751	0.042	tINS	RF	1	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
8.751	0.000	tNET	FF	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
8.794	0.042	tINS	FF	1	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
8.794	0.000	tNET	FF	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
9.185	0.391	tINS	FR	2	R13C10[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
9.498	0.313	tNET	RR	1	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
10.313	0.814	tINS	RF	9	R13C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
10.691	0.379	tNET	FF	1	R13C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/I0
11.506	0.814	tINS	FF	22	R13C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/F
12.126	0.620	tNET	FF	1	R14C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/I3
12.886	0.760	tINS	FR	15	R14C10[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/F
13.201	0.315	tNET	RR	1	R14C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1053_s14/I2
13.810	0.609	tINS	RF	1	R14C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1053_s14/F
13.810	0.000	tNET	FF	1	R14C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1053_s10/I0
13.921	0.110	tINS	FF	1	R14C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1053_s10/O
13.921	0.000	tNET	FF	1	R14C9[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1053_s5/I0
14.041	0.121	tINS	FF	1	R14C9[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1053_s5/O
14.412	0.370	tNET	FF	1	R14C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1129_s7/I0
15.226	0.814	tINS	FF	1	R14C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1129_s7/F
15.226	0.000	tNET	FF	1	R14C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1129_s4/I1
15.336	0.110	tINS	FF	1	R14C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1129_s4/O
15.348	0.011	tNET	FF	1	R14C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R14C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_0_s1/CLK
16.551	-0.296	tSu		1	R14C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 9.233, 60.876%; route: 5.594, 36.885%; tC2Q: 0.340, 2.239%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path49

Path Summary:

Slack	1.210
Data Arrival Time	15.341
Data Required Time	16.551
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_0_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R18C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/CLK
0.520	0.340	tC2Q	RR	1	R18C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_7_s0/Q
0.769	0.249	tNET	RR	1	R18C20[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_15_s10/I3
1.584	0.814	tINS	RF	34	R18C20[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_15_s10/F
4.628	3.044	tNET	FF	1	R25C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/n2208_s3/I1
5.092	0.464	tINS	FF	17	R25C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/n2208_s3/F
5.960	0.868	tNET	FF	1	R25C25[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s15/I0
6.725	0.765	tINS	FF	1	R25C25[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s15/F
6.729	0.004	tNET	FF	1	R25C25[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s11/I0
7.494	0.765	tINS	FF	1	R25C25[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s11/F
7.498	0.004	tNET	FF	1	R25C25[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s8/I2
7.961	0.464	tINS	FF	2	R25C25[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_2_s8/F
10.720	2.759	tNET	FF	2	R20C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1411_s0/I1
11.494	0.774	tINS	FF	1	R20C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1411_s0/COUT
11.494	0.000	tNET	FF	2	R20C15[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1412_s0/CIN
11.537	0.042	tINS	FF	1	R20C15[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1412_s0/COUT
11.537	0.000	tNET	FF	2	R20C15[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1413_s0/CIN
11.579	0.042	tINS	FF	1	R20C15[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1413_s0/COUT
11.579	0.000	tNET	FF	2	R20C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1414_s0/CIN
11.621	0.042	tINS	FF	1	R20C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1414_s0/COUT
11.621	0.000	tNET	FF	2	R20C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1415_s0/CIN
11.663	0.042	tINS	FF	1	R20C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1415_s0/COUT
11.663	0.000	tNET	FF	2	R20C16[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1416_s0/CIN
11.706	0.042	tINS	FF	1	R20C16[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1416_s0/COUT
11.706	0.000	tNET	FF	2	R20C16[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1417_s0/CIN
11.748	0.042	tINS	FF	1	R20C16[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1417_s0/COUT
11.748	0.000	tNET	FF	2	R20C16[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1418_s0/CIN
11.790	0.042	tINS	FF	1	R20C16[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1418_s0/COUT
11.790	0.000	tNET	FF	2	R20C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1419_s0/CIN
11.832	0.042	tINS	FF	1	R20C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1419_s0/COUT
11.832	0.000	tNET	FF	2	R20C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1420_s0/CIN
11.875	0.042	tINS	FF	1	R20C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1420_s0/COUT
11.875	0.000	tNET	FF	2	R20C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1421_s0/CIN
11.917	0.042	tINS	FF	1	R20C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1421_s0/COUT
11.917	0.000	tNET	FF	2	R20C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1422_s0/CIN
11.959	0.042	tINS	FF	1	R20C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1422_s0/COUT
11.959	0.000	tNET	FF	2	R20C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1423_s0/CIN
12.001	0.042	tINS	FF	1	R20C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1423_s0/COUT
12.001	0.000	tNET	FF	2	R20C17[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1424_s0/CIN
12.044	0.042	tINS	FF	3	R20C17[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1424_s0/COUT
12.827	0.784	tNET	FF	1	R20C19[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1688_s39/I2
13.592	0.765	tINS	FF	3	R20C19[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1688_s39/F
13.959	0.367	tNET	FF	1	R20C21[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1678_s14/I1
14.724	0.765	tINS	FF	3	R20C21[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1678_s14/F
14.732	0.008	tNET	FF	1	R20C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1678_s12/I1
15.341	0.609	tINS	FF	1	R20C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1678_s12/F
15.341	0.000	tNET	FF	1	R20C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R20C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_0_s0/CLK
16.551	-0.296	tSu		1	R20C21[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	12
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 6.733, 44.415%; route: 8.087, 53.345%; tC2Q: 0.340, 2.240%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path50

Path Summary:

Slack	1.379
Data Arrival Time	6.837
Data Required Time	8.216
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_2_s1
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	1	R20C12[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3/CLK
0.519	0.340	tC2Q	RF	10	R20C12[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3/Q
1.623	1.104	tNET	FF	1	R20C7[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n321_s16/I3
2.437	0.814	tINS	FF	11	R20C7[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n321_s16/F
3.061	0.624	tNET	FF	1	R21C8[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n321_s12/I3
3.875	0.814	tINS	FF	3	R21C8[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n321_s12/F
4.479	0.604	tNET	FF	1	R20C7[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n321_s13/I2
5.293	0.814	tINS	FF	2	R20C7[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n321_s13/F
5.302	0.008	tNET	FF	1	R20C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n119_s3/I3
5.765	0.464	tINS	FF	3	R20C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n119_s3/F
6.373	0.608	tNET	FF	1	R20C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n119_s0/I3
6.837	0.464	tINS	FF	1	R20C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n119_s0/F
6.837	0.000	tNET	FF	1	R20C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R20C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_2_s1/CLK
8.216	-0.296	tSu		1	R20C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 3.371, 50.630%; route: 2.947, 44.269%; tC2Q: 0.340, 5.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path51

Path Summary:

Slack	1.402
Data Arrival Time	15.414
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_4_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.422	1.098	tNET	FF	1	R5C19[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s8/I3
14.208	0.786	tINS	FR	9	R5C19[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s8/F
15.414	1.206	tNET	RR	1	R7C22[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_4_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R7C22[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_4_s0/CLK
16.816	-0.032	tSu		1	R7C22[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.782, 37.958%; route: 9.111, 59.813%; tC2Q: 0.340, 2.230%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path52

Path Summary:

Slack	1.402
Data Arrival Time	15.414
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_6_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.422	1.098	tNET	FF	1	R5C19[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s8/I3
14.208	0.786	tINS	FR	9	R5C19[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s8/F
15.414	1.206	tNET	RR	1	R7C22[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R7C22[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_6_s0/CLK
16.816	-0.032	tSu		1	R7C22[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.782, 37.958%; route: 9.111, 59.813%; tC2Q: 0.340, 2.230%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path53

Path Summary:

Slack	1.405
Data Arrival Time	15.410
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_1_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.422	1.098	tNET	FF	1	R5C19[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s8/I3
14.208	0.786	tINS	FR	9	R5C19[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s8/F
15.410	1.202	tNET	RR	1	R8C22[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R8C22[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_1_s0/CLK
16.816	-0.032	tSu		1	R8C22[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.782, 37.966%; route: 9.108, 59.804%; tC2Q: 0.340, 2.230%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path54

Path Summary:

Slack	1.437
Data Arrival Time	7.043
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_1_s0
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	8	IOB17[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK
0.579	0.400	tC2Q	RF	1	IOB17[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q1
1.301	0.721	tNET	FF	1	R27C17[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I2
2.065	0.765	tINS	FF	1	R27C17[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F
2.909	0.844	tNET	FF	1	R27C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3
3.724	0.814	tINS	FF	11	R27C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F
4.934	1.211	tNET	FF	1	R26C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1
5.695	0.760	tINS	FR	16	R26C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F
7.043	1.348	tNET	RR	1	R25C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_1_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R25C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_1_s0/CLK
8.480	-0.032	tSu		1	R25C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.339, 34.083%; route: 4.124, 60.088%; tC2Q: 0.400, 5.830%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path55

Path Summary:

Slack	1.437
Data Arrival Time	7.043
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_9_s0
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	8	IOB17[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK
0.579	0.400	tC2Q	RF	1	IOB17[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q1
1.301	0.721	tNET	FF	1	R27C17[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I2
2.065	0.765	tINS	FF	1	R27C17[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F
2.909	0.844	tNET	FF	1	R27C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3
3.724	0.814	tINS	FF	11	R27C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F
4.934	1.211	tNET	FF	1	R26C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1
5.695	0.760	tINS	FR	16	R26C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F
7.043	1.348	tNET	RR	1	R25C12[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_9_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R25C12[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_9_s0/CLK
8.480	-0.032	tSu		1	R25C12[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.339, 34.083%; route: 4.124, 60.088%; tC2Q: 0.400, 5.830%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path56

Path Summary:

Slack	1.437
Data Arrival Time	15.378
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_0_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.422	1.098	tNET	FF	1	R5C19[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s8/I3
14.208	0.786	tINS	FR	9	R5C19[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s8/F
15.378	1.170	tNET	RR	1	R8C19[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R8C19[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_0_s0/CLK
16.816	-0.032	tSu		1	R8C19[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.782, 38.046%; route: 9.076, 59.719%; tC2Q: 0.340, 2.235%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path57

Path Summary:

Slack	1.502
Data Arrival Time	15.049
Data Required Time	16.551
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/descrom_raddr_1_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_dataout_7_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R24C20[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/descrom_raddr_1_s0/CLK
0.520	0.340	tC2Q	RF	42	R24C20[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/descrom_raddr_1_s0/Q
2.273	1.753	tNET	FF	1	R26C17[3][B]	u_usb_desc/DESCROM_RDAT_7_s5/I3
3.087	0.814	tINS	FF	1	R26C17[3][B]	u_usb_desc/DESCROM_RDAT_7_s5/F
3.092	0.004	tNET	FF	1	R26C17[0][A]	u_usb_desc/DESCROM_RDAT_7_s4/I1
3.856	0.765	tINS	FF	1	R26C17[0][A]	u_usb_desc/DESCROM_RDAT_7_s4/F
4.105	0.249	tNET	FF	1	R26C17[0][B]	u_usb_desc/DESCROM_RDAT_7_s1/I3
4.866	0.760	tINS	FR	1	R26C17[0][B]	u_usb_desc/DESCROM_RDAT_7_s1/F
5.176	0.310	tNET	RR	1	R26C18[1][A]	u_usb_desc/DESCROM_RDAT_7_s/I1
5.941	0.765	tINS	RF	2	R26C18[1][A]	u_usb_desc/DESCROM_RDAT_7_s/F
8.714	2.773	tNET	FF	1	R7C24[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n640_s19/I0
9.177	0.464	tINS	FF	1	R7C24[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n640_s19/F
9.427	0.249	tNET	FF	1	R7C24[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n640_s17/I3
10.241	0.814	tINS	FF	1	R7C24[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n640_s17/F
10.245	0.004	tNET	FF	1	R7C24[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n640_s15/I1
10.709	0.464	tINS	FF	2	R7C24[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n640_s15/F
11.790	1.081	tNET	FF	1	R4C20[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n640_s14/I0
12.254	0.464	tINS	FF	1	R4C20[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n640_s14/F
12.850	0.596	tNET	FF	1	R5C19[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n640_s12/I3
13.615	0.765	tINS	FF	2	R5C19[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n640_s12/F
15.049	1.435	tNET	FF	1	R6C18[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_dataout_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R6C18[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_dataout_7_s0/CLK
16.551	-0.296	tSu		1	R6C18[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_dataout_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 6.075, 40.857%; route: 8.454, 56.859%; tC2Q: 0.340, 2.284%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path58

Path Summary:

Slack	1.533
Data Arrival Time	15.282
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_3_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.422	1.098	tNET	FF	1	R5C19[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s8/I3
14.208	0.786	tINS	FR	9	R5C19[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s8/F
15.282	1.075	tNET	RR	1	R6C19[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_3_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R6C19[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_3_s0/CLK
16.816	-0.032	tSu		1	R6C19[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.782, 38.287%; route: 8.980, 59.464%; tC2Q: 0.340, 2.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path59

Path Summary:

Slack	1.535
Data Arrival Time	15.017
Data Required Time	16.551
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_1_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.177	0.853	tNET	FF	1	R4C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n317_s7/I0
13.937	0.760	tINS	FR	4	R4C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n317_s7/F
14.252	0.315	tNET	RR	1	R4C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n317_s4/I3
15.017	0.765	tINS	RF	1	R4C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n317_s4/F
15.017	0.000	tNET	FF	1	R4C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R4C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_1_s1/CLK
16.551	-0.296	tSu		1	R4C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 6.521, 43.953%; route: 7.975, 53.758%; tC2Q: 0.340, 2.289%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path60

Path Summary:

Slack	1.537
Data Arrival Time	15.279
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_2_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.422	1.098	tNET	FF	1	R5C19[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s8/I3
14.208	0.786	tINS	FR	9	R5C19[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s8/F
15.279	1.071	tNET	RR	1	R8C21[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R8C21[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_2_s0/CLK
16.816	-0.032	tSu		1	R8C21[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.782, 38.296%; route: 8.977, 59.455%; tC2Q: 0.340, 2.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path61

Path Summary:

Slack	1.602
Data Arrival Time	14.949
Data Required Time	16.551
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/descrom_raddr_1_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_7_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R24C20[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/descrom_raddr_1_s0/CLK
0.520	0.340	tC2Q	RF	42	R24C20[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/descrom_raddr_1_s0/Q
2.273	1.753	tNET	FF	1	R26C17[3][B]	u_usb_desc/DESCROM_RDAT_7_s5/I3
3.087	0.814	tINS	FF	1	R26C17[3][B]	u_usb_desc/DESCROM_RDAT_7_s5/F
3.092	0.004	tNET	FF	1	R26C17[0][A]	u_usb_desc/DESCROM_RDAT_7_s4/I1
3.856	0.765	tINS	FF	1	R26C17[0][A]	u_usb_desc/DESCROM_RDAT_7_s4/F
4.105	0.249	tNET	FF	1	R26C17[0][B]	u_usb_desc/DESCROM_RDAT_7_s1/I3
4.866	0.760	tINS	FR	1	R26C17[0][B]	u_usb_desc/DESCROM_RDAT_7_s1/F
5.176	0.310	tNET	RR	1	R26C18[1][A]	u_usb_desc/DESCROM_RDAT_7_s/I1
5.941	0.765	tINS	RF	2	R26C18[1][A]	u_usb_desc/DESCROM_RDAT_7_s/F
8.714	2.773	tNET	FF	1	R7C24[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n640_s19/I0
9.177	0.464	tINS	FF	1	R7C24[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n640_s19/F
9.427	0.249	tNET	FF	1	R7C24[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n640_s17/I3
10.241	0.814	tINS	FF	1	R7C24[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n640_s17/F
10.245	0.004	tNET	FF	1	R7C24[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n640_s15/I1
10.709	0.464	tINS	FF	2	R7C24[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n640_s15/F
11.790	1.081	tNET	FF	1	R4C20[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n640_s14/I0
12.254	0.464	tINS	FF	1	R4C20[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n640_s14/F
12.850	0.596	tNET	FF	1	R5C19[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n640_s12/I3
13.615	0.765	tINS	FF	2	R5C19[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n640_s12/F
14.340	0.726	tNET	FF	1	R6C18[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n778_s0/I0
14.949	0.609	tINS	FF	1	R6C18[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n778_s0/F
14.949	0.000	tNET	FF	1	R6C18[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R6C18[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_7_s0/CLK
16.551	-0.296	tSu		1	R6C18[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	11
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 6.684, 45.257%; route: 7.745, 52.443%; tC2Q: 0.340, 2.300%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path62

Path Summary:

Slack	1.662
Data Arrival Time	15.154
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_val_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.051	0.727	tNET	FF	1	R5C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s7/I0
13.660	0.609	tINS	FF	1	R5C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s7/F
13.664	0.004	tNET	FF	1	R5C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s3/I3
14.128	0.464	tINS	FF	9	R5C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s3/F
14.144	0.016	tNET	FF	1	R5C17[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_val_s3/I3
14.904	0.760	tINS	FR	1	R5C17[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_val_s3/F
15.154	0.249	tNET	RR	1	R5C17[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_val_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R5C17[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_val_s1/CLK
16.816	-0.032	tSu		1	R5C17[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_val_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	11
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 6.829, 45.610%; route: 7.804, 52.122%; tC2Q: 0.340, 2.268%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path63

Path Summary:

Slack	1.690
Data Arrival Time	14.861
Data Required Time	16.551
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_7_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.177	0.853	tNET	FF	1	R4C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n317_s7/I0
13.937	0.760	tINS	FR	4	R4C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n317_s7/F
14.252	0.315	tNET	RR	1	R5C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n311_s7/I3
14.861	0.609	tINS	RF	1	R5C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n311_s7/F
14.861	0.000	tNET	FF	1	R5C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R5C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_7_s1/CLK
16.551	-0.296	tSu		1	R5C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_7_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 6.365, 43.359%; route: 7.975, 54.328%; tC2Q: 0.340, 2.313%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path64

Path Summary:

Slack	1.697
Data Arrival Time	15.119
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_state_0_s1
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_5_s12
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R4C26[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_state_0_s1/CLK
0.520	0.340	tC2Q	RF	7	R4C26[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_state_0_s1/Q
1.857	1.337	tNET	FF	1	R3C29[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/n1075_s12/I0
2.622	0.765	tINS	FF	8	R3C29[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/n1075_s12/F
3.849	1.228	tNET	FF	1	R5C30[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/n1150_s20/I1
4.313	0.464	tINS	FF	6	R5C30[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/n1150_s20/F
6.010	1.697	tNET	FF	1	R6C26[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s3/I3
6.824	0.814	tINS	FF	12	R6C26[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s3/F
8.391	1.566	tNET	FF	1	R8C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s1/I1
9.000	0.609	tINS	FF	5	R8C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s1/F
10.215	1.215	tNET	FF	1	R6C19[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s24/I2
10.979	0.765	tINS	FF	1	R6C19[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s24/F
11.575	0.596	tNET	FF	1	R6C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s21/I0
12.340	0.765	tINS	FF	1	R6C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s21/F
12.344	0.004	tNET	FF	1	R6C21[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s18/I2
12.807	0.463	tINS	FR	1	R6C21[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s18/F
13.118	0.310	tNET	RR	1	R5C21[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s16/I3
13.712	0.594	tINS	RR	7	R5C21[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s16/F
15.119	1.407	tNET	RR	1	R6C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_5_s12/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R6C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_5_s12/CLK
16.816	-0.032	tSu		1	R6C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_5_s12

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.239, 35.071%; route: 9.359, 62.656%; tC2Q: 0.340, 2.274%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path65

Path Summary:

Slack	1.701
Data Arrival Time	14.851
Data Required Time	16.551
From	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_5_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	4	BSRAM_R28[14]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKB
2.745	2.564	tC2Q	RF	1	BSRAM_R28[14]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DO[1]
4.783	2.038	tNET	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s21/I1
5.597	0.814	tINS	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s21/F
5.597	0.000	tNET	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s20/I0
5.707	0.110	tINS	FF	1	R11C38[2][A]	usb_fifo/o_usb_txdat_5_s20/O
7.510	1.802	tNET	FF	1	R6C32[3][A]	usb_txdat_5_s3/I0
7.973	0.464	tINS	FF	2	R6C32[3][A]	usb_txdat_5_s3/F
9.055	1.081	tNET	FF	1	R5C23[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s10/I1
9.518	0.463	tINS	FR	1	R5C23[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s10/F
9.828	0.310	tNET	RR	1	R5C22[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s9/I0
10.642	0.814	tINS	RF	1	R5C22[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s9/F
10.647	0.004	tNET	FF	1	R5C22[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s6/I2
11.256	0.609	tINS	FF	1	R5C22[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s6/F
11.852	0.596	tNET	FF	1	R4C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s4/I1
12.638	0.786	tINS	FR	2	R4C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s4/F
12.951	0.313	tNET	RR	1	R5C21[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n780_s3/I1
13.560	0.609	tINS	RF	1	R5C21[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n780_s3/F
13.564	0.004	tNET	FF	1	R5C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n780_s1/I2
14.379	0.814	tINS	FF	2	R5C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n780_s1/F
14.387	0.008	tNET	FF	1	R5C21[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n780_s0/I0
14.851	0.464	tINS	FF	1	R5C21[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n780_s0/F
14.851	0.000	tNET	FF	1	R5C21[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R5C21[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_5_s0/CLK
16.551	-0.296	tSu		1	R5C21[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.949, 40.551%; route: 6.157, 41.972%; tC2Q: 2.564, 17.477%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path66

Path Summary:

Slack	1.703
Data Arrival Time	6.513
Data Required Time	8.216
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_3_s1
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	1	R20C12[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3/CLK
0.519	0.340	tC2Q	RF	10	R20C12[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3/Q
1.623	1.104	tNET	FF	1	R20C7[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n321_s16/I3
2.437	0.814	tINS	FF	11	R20C7[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n321_s16/F
3.061	0.624	tNET	FF	1	R21C8[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n321_s12/I3
3.875	0.814	tINS	FF	3	R21C8[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n321_s12/F
4.479	0.604	tNET	FF	1	R20C7[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n321_s13/I2
5.265	0.786	tINS	FR	2	R20C7[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n321_s13/F
5.577	0.312	tNET	RR	1	R21C7[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n321_s17/I2
6.391	0.814	tINS	RF	1	R21C7[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n321_s17/F
6.391	0.000	tNET	FF	1	R21C7[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n321_s10/I0
6.502	0.110	tINS	FF	1	R21C7[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n321_s10/O
6.513	0.011	tNET	FF	1	R21C7[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R21C7[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_3_s1/CLK
8.216	-0.296	tSu		1	R21C7[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 3.340, 52.729%; route: 2.654, 41.909%; tC2Q: 0.340, 5.362%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path67

Path Summary:

Slack	1.704
Data Arrival Time	15.112
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_state_0_s1
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_2_s12
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R4C26[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_state_0_s1/CLK
0.520	0.340	tC2Q	RF	7	R4C26[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_state_0_s1/Q
1.857	1.337	tNET	FF	1	R3C29[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/n1075_s12/I0
2.622	0.765	tINS	FF	8	R3C29[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/n1075_s12/F
3.849	1.228	tNET	FF	1	R5C30[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/n1150_s20/I1
4.313	0.464	tINS	FF	6	R5C30[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/n1150_s20/F
6.010	1.697	tNET	FF	1	R6C26[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s3/I3
6.824	0.814	tINS	FF	12	R6C26[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s3/F
8.391	1.566	tNET	FF	1	R8C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s1/I1
9.000	0.609	tINS	FF	5	R8C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s1/F
10.215	1.215	tNET	FF	1	R6C19[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s24/I2
10.979	0.765	tINS	FF	1	R6C19[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s24/F
11.575	0.596	tNET	FF	1	R6C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s21/I0
12.340	0.765	tINS	FF	1	R6C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s21/F
12.344	0.004	tNET	FF	1	R6C21[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s18/I2
12.807	0.463	tINS	FR	1	R6C21[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s18/F
13.118	0.310	tNET	RR	1	R5C21[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s16/I3
13.712	0.594	tINS	RR	7	R5C21[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s16/F
15.112	1.400	tNET	RR	1	R8C19[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_2_s12/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R8C19[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_2_s12/CLK
16.816	-0.032	tSu		1	R8C19[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_2_s12

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.239, 35.087%; route: 9.353, 62.639%; tC2Q: 0.340, 2.275%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path68

Path Summary:

Slack	1.710
Data Arrival Time	6.771
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_5_s0
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	8	IOB17[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK
0.579	0.400	tC2Q	RF	1	IOB17[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q1
1.301	0.721	tNET	FF	1	R27C17[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I2
2.065	0.765	tINS	FF	1	R27C17[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F
2.909	0.844	tNET	FF	1	R27C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3
3.724	0.814	tINS	FF	11	R27C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F
4.934	1.211	tNET	FF	1	R26C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1
5.695	0.760	tINS	FR	16	R26C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F
6.771	1.076	tNET	RR	1	R25C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_5_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R25C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_5_s0/CLK
8.480	-0.032	tSu		1	R25C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.339, 35.491%; route: 3.852, 58.438%; tC2Q: 0.400, 6.071%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path69

Path Summary:

Slack	1.710
Data Arrival Time	6.771
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_13_s0
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	8	IOB17[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK
0.579	0.400	tC2Q	RF	1	IOB17[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q1
1.301	0.721	tNET	FF	1	R27C17[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I2
2.065	0.765	tINS	FF	1	R27C17[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F
2.909	0.844	tNET	FF	1	R27C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3
3.724	0.814	tINS	FF	11	R27C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F
4.934	1.211	tNET	FF	1	R26C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1
5.695	0.760	tINS	FR	16	R26C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F
6.771	1.076	tNET	RR	1	R25C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_13_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R25C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_13_s0/CLK
8.480	-0.032	tSu		1	R25C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_13_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.339, 35.491%; route: 3.852, 58.438%; tC2Q: 0.400, 6.071%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path70

Path Summary:

Slack	1.711
Data Arrival Time	6.769
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_3_s0
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	8	IOB17[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK
0.579	0.400	tC2Q	RF	1	IOB17[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q1
1.301	0.721	tNET	FF	1	R27C17[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I2
2.065	0.765	tINS	FF	1	R27C17[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F
2.909	0.844	tNET	FF	1	R27C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3
3.724	0.814	tINS	FF	11	R27C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F
4.934	1.211	tNET	FF	1	R26C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1
5.695	0.760	tINS	FR	16	R26C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F
6.769	1.075	tNET	RR	1	R24C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_3_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R24C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_3_s0/CLK
8.480	-0.032	tSu		1	R24C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.339, 35.498%; route: 3.851, 58.430%; tC2Q: 0.400, 6.072%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path71

Path Summary:

Slack	1.711
Data Arrival Time	6.769
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_6_s0
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	8	IOB17[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK
0.579	0.400	tC2Q	RF	1	IOB17[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q1
1.301	0.721	tNET	FF	1	R27C17[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I2
2.065	0.765	tINS	FF	1	R27C17[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F
2.909	0.844	tNET	FF	1	R27C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3
3.724	0.814	tINS	FF	11	R27C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F
4.934	1.211	tNET	FF	1	R26C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1
5.695	0.760	tINS	FR	16	R26C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F
6.769	1.075	tNET	RR	1	R24C13[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_6_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R24C13[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_6_s0/CLK
8.480	-0.032	tSu		1	R24C13[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.339, 35.498%; route: 3.851, 58.430%; tC2Q: 0.400, 6.072%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path72

Path Summary:

Slack	1.711
Data Arrival Time	6.769
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_7_s0
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	8	IOB17[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK
0.579	0.400	tC2Q	RF	1	IOB17[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q1
1.301	0.721	tNET	FF	1	R27C17[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I2
2.065	0.765	tINS	FF	1	R27C17[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F
2.909	0.844	tNET	FF	1	R27C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3
3.724	0.814	tINS	FF	11	R27C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F
4.934	1.211	tNET	FF	1	R26C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1
5.695	0.760	tINS	FR	16	R26C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F
6.769	1.075	tNET	RR	1	R24C13[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_7_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R24C13[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_7_s0/CLK
8.480	-0.032	tSu		1	R24C13[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.339, 35.498%; route: 3.851, 58.430%; tC2Q: 0.400, 6.072%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path73

Path Summary:

Slack	1.723
Data Arrival Time	6.492
Data Required Time	8.216
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_6_s1
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	1	R20C12[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3/CLK
0.519	0.340	tC2Q	RF	10	R20C12[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_2_s3/Q
1.623	1.104	tNET	FF	1	R20C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n105_s6/I2
2.437	0.814	tINS	FF	17	R20C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n105_s6/F
3.077	0.640	tNET	FF	1	R21C8[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n318_s10/I2
3.842	0.765	tINS	FF	1	R21C8[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n318_s10/F
3.846	0.004	tNET	FF	1	R21C8[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n318_s8/I1
4.660	0.814	tINS	FF	1	R21C8[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n318_s8/F
4.909	0.249	tNET	FF	1	R21C8[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n318_s7/I1
5.724	0.814	tINS	FF	1	R21C8[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n318_s7/F
5.728	0.004	tNET	FF	1	R21C8[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n318_s5/I3
6.492	0.765	tINS	FF	1	R21C8[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n318_s5/F
6.492	0.000	tNET	FF	1	R21C8[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R21C8[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_6_s1/CLK
8.216	-0.296	tSu		1	R21C8[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_6_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 3.973, 62.924%; route: 2.001, 31.696%; tC2Q: 0.340, 5.380%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path74

Path Summary:

Slack	1.738
Data Arrival Time	6.478
Data Required Time	8.216
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Full_s0
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	1	R20C7[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_s0/CLK
0.519	0.340	tC2Q	RF	2	R20C7[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_s0/Q
1.598	1.079	tNET	FF	1	R23C5[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/n24_s1/I2
2.061	0.463	tINS	FR	6	R23C5[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/n24_s1/F
2.381	0.319	tNET	RR	1	R22C5[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wgraynext_3_s1/I2
3.195	0.814	tINS	RF	5	R22C5[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wgraynext_3_s1/F
3.215	0.020	tNET	FF	1	R22C5[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbinnext_5_s3/I3
3.975	0.760	tINS	FR	2	R22C5[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbinnext_5_s3/F
4.287	0.312	tNET	RR	1	R21C5[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbinnext_5_s2/I0
5.102	0.814	tINS	RF	2	R21C5[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbinnext_5_s2/F
5.110	0.008	tNET	FF	1	R21C5[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/wfull_val_s1/I3
5.704	0.594	tINS	FR	1	R21C5[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/wfull_val_s1/F
6.014	0.310	tNET	RR	1	R21C4[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/wfull_val_s0/I0
6.478	0.464	tINS	RF	1	R21C4[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/wfull_val_s0/F
6.478	0.000	tNET	FF	1	R21C4[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Full_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R21C4[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Full_s0/CLK
8.216	-0.296	tSu		1	R21C4[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Full_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 3.910, 62.077%; route: 2.049, 32.531%; tC2Q: 0.340, 5.392%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path75

Path Summary:

Slack	1.743
Data Arrival Time	15.073
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_6_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.177	0.853	tNET	FF	1	R6C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_11_s3/I0
13.937	0.760	tINS	FR	12	R6C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_11_s3/F
15.073	1.136	tNET	RR	1	R8C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_6_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R8C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_6_s1/CLK
16.816	-0.032	tSu		1	R8C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_6_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.756, 38.652%; route: 8.797, 59.068%; tC2Q: 0.340, 2.281%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path76

Path Summary:

Slack	1.743
Data Arrival Time	15.073
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_7_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.177	0.853	tNET	FF	1	R6C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_11_s3/I0
13.937	0.760	tINS	FR	12	R6C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_11_s3/F
15.073	1.136	tNET	RR	1	R8C16[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_7_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R8C16[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_7_s1/CLK
16.816	-0.032	tSu		1	R8C16[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_7_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.756, 38.652%; route: 8.797, 59.068%; tC2Q: 0.340, 2.281%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path77

Path Summary:

Slack	1.743
Data Arrival Time	15.073
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_8_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.177	0.853	tNET	FF	1	R6C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_11_s3/I0
13.937	0.760	tINS	FR	12	R6C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_11_s3/F
15.073	1.136	tNET	RR	1	R8C16[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_8_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R8C16[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_8_s1/CLK
16.816	-0.032	tSu		1	R8C16[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_8_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.756, 38.652%; route: 8.797, 59.068%; tC2Q: 0.340, 2.281%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path78

Path Summary:

Slack	1.743
Data Arrival Time	15.073
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_9_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.177	0.853	tNET	FF	1	R6C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_11_s3/I0
13.937	0.760	tINS	FR	12	R6C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_11_s3/F
15.073	1.136	tNET	RR	1	R8C16[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_9_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R8C16[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_9_s1/CLK
16.816	-0.032	tSu		1	R8C16[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_9_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.756, 38.652%; route: 8.797, 59.068%; tC2Q: 0.340, 2.281%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path79

Path Summary:

Slack	1.779
Data Arrival Time	14.772
Data Required Time	16.551
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_6_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.177	0.853	tNET	FF	1	R4C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n317_s7/I0
13.942	0.765	tINS	FF	4	R4C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n317_s7/F
13.958	0.016	tNET	FF	1	R4C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n312_s5/I3
14.772	0.814	tINS	FF	1	R4C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n312_s5/F
14.772	0.000	tNET	FF	1	R4C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R4C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_6_s1/CLK
16.551	-0.296	tSu		1	R4C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_6_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 6.575, 45.060%; route: 7.677, 52.613%; tC2Q: 0.340, 2.328%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path80

Path Summary:

Slack	1.819
Data Arrival Time	14.997
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_2_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.051	0.727	tNET	FF	1	R5C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s7/I0
13.660	0.609	tINS	FF	1	R5C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s7/F
13.664	0.004	tNET	FF	1	R5C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s3/I3
14.127	0.463	tINS	FR	9	R5C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s3/F
14.997	0.870	tNET	RR	1	R4C17[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_2_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R4C17[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_2_s1/CLK
16.816	-0.032	tSu		1	R4C17[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 6.068, 40.956%; route: 8.408, 56.752%; tC2Q: 0.340, 2.292%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path81

Path Summary:

Slack	1.819
Data Arrival Time	14.997
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_6_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.051	0.727	tNET	FF	1	R5C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s7/I0
13.660	0.609	tINS	FF	1	R5C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s7/F
13.664	0.004	tNET	FF	1	R5C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s3/I3
14.127	0.463	tINS	FR	9	R5C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s3/F
14.997	0.870	tNET	RR	1	R4C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_6_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R4C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_6_s1/CLK
16.816	-0.032	tSu		1	R4C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_6_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 6.068, 40.956%; route: 8.408, 56.752%; tC2Q: 0.340, 2.292%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path82

Path Summary:

Slack	1.820
Data Arrival Time	14.731
Data Required Time	16.551
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wptr_3_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.914	0.983	tNET	FF	1	R7C15[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_opmode_o_d_1_s/I2
6.728	0.814	tINS	FF	12	R7C15[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_opmode_o_d_1_s/F
8.783	2.055	tNET	FF	1	R4C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/fifo_wr_data_7_s1/I1
9.247	0.464	tINS	FF	17	R4C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/fifo_wr_data_7_s1/F
10.972	1.726	tNET	FF	1	R7C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n24_s1/I3
11.581	0.609	tINS	FF	7	R7C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n24_s1/F
12.210	0.629	tNET	FF	1	R8C6[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbinnext_3_s4/I3
12.820	0.609	tINS	FF	3	R8C6[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbinnext_3_s4/F
13.189	0.370	tNET	FF	1	R8C4[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbinnext_4_s2/I1
13.954	0.765	tINS	FF	3	R8C4[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbinnext_4_s2/F
13.966	0.012	tNET	FF	1	R8C4[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wgraynext_3_s1/I2
14.731	0.765	tINS	FF	1	R8C4[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wgraynext_3_s1/F
14.731	0.000	tNET	FF	1	R8C4[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wptr_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R8C4[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wptr_3_s0/CLK
16.551	-0.296	tSu		1	R8C4[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wptr_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 6.370, 43.777%; route: 7.841, 53.889%; tC2Q: 0.340, 2.334%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path83

Path Summary:

Slack	1.825
Data Arrival Time	14.726
Data Required Time	16.551
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbin_3_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.914	0.983	tNET	FF	1	R7C15[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_opmode_o_d_1_s/I2
6.728	0.814	tINS	FF	12	R7C15[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_opmode_o_d_1_s/F
8.783	2.055	tNET	FF	1	R4C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/fifo_wr_data_7_s1/I1
9.247	0.464	tINS	FF	17	R4C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/fifo_wr_data_7_s1/F
10.972	1.726	tNET	FF	1	R7C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n24_s1/I3
11.581	0.609	tINS	FF	7	R7C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n24_s1/F
12.210	0.629	tNET	FF	1	R8C6[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbinnext_3_s4/I3
12.820	0.609	tINS	FF	3	R8C6[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbinnext_3_s4/F
13.189	0.370	tNET	FF	1	R8C4[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbinnext_3_s3/I1
13.950	0.760	tINS	FR	2	R8C4[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbinnext_3_s3/F
14.726	0.776	tNET	RR	1	R8C5[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbin_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R8C5[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbin_3_s0/CLK
16.551	-0.296	tSu		1	R8C5[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbin_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.600, 38.503%; route: 8.605, 59.162%; tC2Q: 0.340, 2.335%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path84

Path Summary:

Slack	1.836
Data Arrival Time	14.716
Data Required Time	16.551
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.177	0.853	tNET	FF	1	R4C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n317_s7/I0
13.937	0.760	tINS	FR	4	R4C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n317_s7/F
14.252	0.315	tNET	RR	1	R5C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n309_s2/I3
14.716	0.464	tINS	RF	1	R5C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n309_s2/F
14.716	0.000	tNET	FF	1	R5C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R5C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s1/CLK
16.551	-0.296	tSu		1	R5C17[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 6.220, 42.793%; route: 7.975, 54.871%; tC2Q: 0.340, 2.337%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path85

Path Summary:

Slack	1.862
Data Arrival Time	14.953
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_3_s6
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_0_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R16C18[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_3_s6/CLK
0.520	0.340	tC2Q	RF	5	R16C18[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_3_s6/Q
1.128	0.608	tNET	FF	1	R16C19[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_7_s10/I3
1.893	0.765	tINS	FF	7	R16C19[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_7_s10/F
2.767	0.874	tNET	FF	1	R18C19[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1669_s15/I2
3.531	0.765	tINS	FF	3	R18C19[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1669_s15/F
5.345	1.814	tNET	FF	1	R6C26[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s3/I2
5.954	0.609	tINS	FF	2	R6C26[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s3/F
5.962	0.008	tNET	FF	1	R6C26[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s/I1
6.776	0.814	tINS	FF	17	R6C26[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s/F
10.281	3.504	tNET	FF	1	R15C20[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_7_s12/I3
11.095	0.814	tINS	FF	7	R15C20[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_7_s12/F
11.704	0.608	tNET	FF	1	R16C21[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_7_s6/I0
12.313	0.609	tINS	FF	8	R16C21[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_7_s6/F
14.241	1.928	tNET	FF	1	R17C23[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_0_s5/I3
14.704	0.463	tINS	FR	1	R17C23[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_0_s5/F
14.953	0.249	tNET	RR	1	R17C23[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R17C23[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_0_s0/CLK
16.816	-0.032	tSu		1	R17C23[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 4.839, 32.759%; route: 9.594, 64.942%; tC2Q: 0.340, 2.299%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path86

Path Summary:

Slack	1.870
Data Arrival Time	14.681
Data Required Time	16.551
From	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/crc16_buf_3_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	4	BSRAM_R28[14]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKB
2.745	2.564	tC2Q	RF	1	BSRAM_R28[14]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DO[2]
4.783	2.038	tNET	FF	1	R11C38[3][A]	usb_fifo/o_usb_txdat_6_s21/I1
5.246	0.464	tINS	FF	1	R11C38[3][A]	usb_fifo/o_usb_txdat_6_s21/F
5.246	0.000	tNET	FF	1	R11C38[3][A]	usb_fifo/o_usb_txdat_6_s20/I0
5.357	0.110	tINS	FF	1	R11C38[3][A]	usb_fifo/o_usb_txdat_6_s20/O
7.048	1.691	tNET	FF	1	R7C26[2][A]	usb_txdat_6_s3/I0
7.657	0.609	tINS	FF	2	R7C26[2][A]	usb_txdat_6_s3/F
8.383	0.726	tNET	FF	1	R5C24[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s22/I1
8.992	0.609	tINS	FF	1	R5C24[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s22/F
8.996	0.004	tNET	FF	1	R5C24[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s21/I0
9.810	0.814	tINS	FF	1	R5C24[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s21/F
10.173	0.363	tNET	FF	1	R5C22[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s17/I3
10.938	0.765	tINS	FF	1	R5C22[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s17/F
11.546	0.608	tNET	FF	1	R5C24[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s15/I1
12.156	0.609	tINS	FF	2	R5C24[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n642_s15/F
12.756	0.600	tNET	FF	1	R4C22[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n774_s3/I1
13.219	0.464	tINS	FF	4	R4C22[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n774_s3/F
14.072	0.853	tNET	FF	1	R5C20[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s11/I0
14.681	0.609	tINS	FF	1	R5C20[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n773_s11/F
14.681	0.000	tNET	FF	1	R5C20[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/crc16_buf_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R5C20[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/crc16_buf_3_s1/CLK
16.551	-0.296	tSu		1	R5C20[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/crc16_buf_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.054, 34.851%; route: 6.883, 47.467%; tC2Q: 2.564, 17.681%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path87

Path Summary:

Slack	1.876
Data Arrival Time	14.675
Data Required Time	16.551
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wptr_4_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.914	0.983	tNET	FF	1	R7C15[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_opmode_o_d_1_s/I2
6.728	0.814	tINS	FF	12	R7C15[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_opmode_o_d_1_s/F
8.783	2.055	tNET	FF	1	R4C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/fifo_wr_data_7_s1/I1
9.247	0.464	tINS	FF	17	R4C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/fifo_wr_data_7_s1/F
10.972	1.726	tNET	FF	1	R7C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n24_s1/I3
11.581	0.609	tINS	FF	7	R7C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n24_s1/F
12.210	0.629	tNET	FF	1	R8C6[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbinnext_3_s4/I3
12.820	0.609	tINS	FF	3	R8C6[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbinnext_3_s4/F
13.189	0.370	tNET	FF	1	R8C4[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbinnext_4_s2/I1
13.954	0.765	tINS	FF	3	R8C4[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbinnext_4_s2/F
14.675	0.721	tNET	FF	1	R8C4[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wptr_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R8C4[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wptr_4_s0/CLK
16.551	-0.296	tSu		1	R8C4[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wptr_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.605, 38.669%; route: 8.550, 58.988%; tC2Q: 0.340, 2.343%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path88

Path Summary:

Slack	1.964
Data Arrival Time	14.851
Data Required Time	16.816
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_8_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/CLK
0.520	0.340	tC2Q	RF	77	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q
1.860	1.340	tNET	FF	1	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I1
2.469	0.609	tINS	FF	5	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
2.481	0.012	tNET	FF	1	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
3.268	0.786	tINS	FR	7	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
3.581	0.313	tNET	RR	1	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
4.045	0.464	tINS	RF	4	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
4.057	0.012	tNET	FF	1	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
4.871	0.814	tINS	FF	5	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
5.238	0.366	tNET	FF	1	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
5.832	0.594	tINS	FR	2	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
6.145	0.313	tNET	RR	1	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
6.609	0.464	tINS	RF	10	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
7.229	0.620	tNET	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
7.693	0.464	tINS	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
8.302	0.608	tNET	FF	2	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
8.709	0.408	tINS	FR	1	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
8.709	0.000	tNET	RR	2	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
8.751	0.042	tINS	RF	1	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
8.751	0.000	tNET	FF	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
9.143	0.391	tINS	FR	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/SUM
9.454	0.312	tNET	RR	1	R13C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s9/I1
9.918	0.464	tINS	RF	6	R13C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s9/F
10.522	0.603	tNET	FF	1	R14C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s6/I3
10.986	0.464	tINS	FF	4	R14C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s6/F
11.602	0.617	tNET	FF	1	R13C11[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1115_s7/I2
12.066	0.464	tINS	FF	5	R13C11[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1115_s7/F
12.670	0.603	tNET	FF	1	R14C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s7/I3
13.430	0.760	tINS	FR	18	R14C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s7/F
14.851	1.421	tNET	RR	1	R17C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_8_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R17C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_8_s1/CLK
16.816	-0.032	tSu		1	R17C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_8_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	14
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 7.188, 48.999%; route: 7.142, 48.686%; tC2Q: 0.340, 2.315%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path89

Path Summary:

Slack	1.964
Data Arrival Time	14.851
Data Required Time	16.816
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_13_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/CLK
0.520	0.340	tC2Q	RF	77	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q
1.860	1.340	tNET	FF	1	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I1
2.469	0.609	tINS	FF	5	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
2.481	0.012	tNET	FF	1	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
3.268	0.786	tINS	FR	7	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
3.581	0.313	tNET	RR	1	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
4.045	0.464	tINS	RF	4	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
4.057	0.012	tNET	FF	1	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
4.871	0.814	tINS	FF	5	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
5.238	0.366	tNET	FF	1	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
5.832	0.594	tINS	FR	2	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
6.145	0.313	tNET	RR	1	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
6.609	0.464	tINS	RF	10	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
7.229	0.620	tNET	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
7.693	0.464	tINS	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
8.302	0.608	tNET	FF	2	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
8.709	0.408	tINS	FR	1	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
8.709	0.000	tNET	RR	2	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
8.751	0.042	tINS	RF	1	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
8.751	0.000	tNET	FF	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
9.143	0.391	tINS	FR	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/SUM
9.454	0.312	tNET	RR	1	R13C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s9/I1
9.918	0.464	tINS	RF	6	R13C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s9/F
10.522	0.603	tNET	FF	1	R14C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s6/I3
10.986	0.464	tINS	FF	4	R14C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s6/F
11.602	0.617	tNET	FF	1	R13C11[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1115_s7/I2
12.066	0.464	tINS	FF	5	R13C11[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1115_s7/F
12.670	0.603	tNET	FF	1	R14C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s7/I3
13.430	0.760	tINS	FR	18	R14C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s7/F
14.851	1.421	tNET	RR	1	R17C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_13_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R17C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_13_s1/CLK
16.816	-0.032	tSu		1	R17C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_13_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	14
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 7.188, 48.999%; route: 7.142, 48.686%; tC2Q: 0.340, 2.315%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path90

Path Summary:

Slack	1.971
Data Arrival Time	14.844
Data Required Time	16.816
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_9_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/CLK
0.520	0.340	tC2Q	RF	77	R13C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_2_s5/Q
1.860	1.340	tNET	FF	1	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I1
2.469	0.609	tINS	FF	5	R15C12[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
2.481	0.012	tNET	FF	1	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
3.268	0.786	tINS	FR	7	R15C12[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
3.581	0.313	tNET	RR	1	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
4.045	0.464	tINS	RF	4	R15C13[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
4.057	0.012	tNET	FF	1	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
4.871	0.814	tINS	FF	5	R15C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
5.238	0.366	tNET	FF	1	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
5.832	0.594	tINS	FR	2	R13C13[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
6.145	0.313	tNET	RR	1	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
6.609	0.464	tINS	RF	10	R14C13[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
7.229	0.620	tNET	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
7.693	0.464	tINS	FF	1	R13C12[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
8.302	0.608	tNET	FF	2	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
8.709	0.408	tINS	FR	1	R13C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
8.709	0.000	tNET	RR	2	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
8.751	0.042	tINS	RF	1	R13C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
8.751	0.000	tNET	FF	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
9.143	0.391	tINS	FR	2	R13C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/SUM
9.454	0.312	tNET	RR	1	R13C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s9/I1
9.918	0.464	tINS	RF	6	R13C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s9/F
10.522	0.603	tNET	FF	1	R14C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s6/I3
10.986	0.464	tINS	FF	4	R14C10[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s6/F
11.602	0.617	tNET	FF	1	R13C11[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1115_s7/I2
12.066	0.464	tINS	FF	5	R13C11[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1115_s7/F
12.670	0.603	tNET	FF	1	R14C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s7/I3
13.430	0.760	tINS	FR	18	R14C10[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s7/F
14.844	1.414	tNET	RR	1	R17C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_9_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R17C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_9_s1/CLK
16.816	-0.032	tSu		1	R17C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_9_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	14
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 7.188, 49.022%; route: 7.136, 48.662%; tC2Q: 0.340, 2.316%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path91

Path Summary:

Slack	1.976
Data Arrival Time	14.840
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_state_0_s1
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_0_s12
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R4C26[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_state_0_s1/CLK
0.520	0.340	tC2Q	RF	7	R4C26[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_state_0_s1/Q
1.857	1.337	tNET	FF	1	R3C29[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/n1075_s12/I0
2.622	0.765	tINS	FF	8	R3C29[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/n1075_s12/F
3.849	1.228	tNET	FF	1	R5C30[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/n1150_s20/I1
4.313	0.464	tINS	FF	6	R5C30[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/n1150_s20/F
6.010	1.697	tNET	FF	1	R6C26[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s3/I3
6.824	0.814	tINS	FF	12	R6C26[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s3/F
8.391	1.566	tNET	FF	1	R8C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s1/I1
9.000	0.609	tINS	FF	5	R8C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s1/F
10.215	1.215	tNET	FF	1	R6C19[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s24/I2
10.979	0.765	tINS	FF	1	R6C19[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s24/F
11.575	0.596	tNET	FF	1	R6C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s21/I0
12.340	0.765	tINS	FF	1	R6C21[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s21/F
12.344	0.004	tNET	FF	1	R6C21[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s18/I2
12.807	0.463	tINS	FR	1	R6C21[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s18/F
13.118	0.310	tNET	RR	1	R5C21[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s16/I3
13.712	0.594	tINS	RR	7	R5C21[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_11_s16/F
14.840	1.128	tNET	RR	1	R9C20[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_0_s12/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R9C20[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_0_s12/CLK
16.816	-0.032	tSu		1	R9C20[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_state_0_s12

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.239, 35.739%; route: 9.080, 61.944%; tC2Q: 0.340, 2.317%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path92

Path Summary:

Slack	1.985
Data Arrival Time	6.495
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_2_s0
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	8	IOB17[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK
0.579	0.400	tC2Q	RF	1	IOB17[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q1
1.301	0.721	tNET	FF	1	R27C17[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I2
2.065	0.765	tINS	FF	1	R27C17[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F
2.909	0.844	tNET	FF	1	R27C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3
3.724	0.814	tINS	FF	11	R27C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F
4.934	1.211	tNET	FF	1	R26C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1
5.695	0.760	tINS	FR	16	R26C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F
6.495	0.800	tNET	RR	1	R24C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_2_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R24C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_2_s0/CLK
8.480	-0.032	tSu		1	R24C10[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.339, 37.041%; route: 3.576, 56.623%; tC2Q: 0.400, 6.336%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path93

Path Summary:

Slack	1.985
Data Arrival Time	6.495
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_11_s0
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.179	0.179	tNET	RR	8	IOB17[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK
0.579	0.400	tC2Q	RF	1	IOB17[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q1
1.301	0.721	tNET	FF	1	R27C17[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I2
2.065	0.765	tINS	FF	1	R27C17[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F
2.909	0.844	tNET	FF	1	R27C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3
3.724	0.814	tINS	FF	11	R27C11[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F
4.934	1.211	tNET	FF	1	R26C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1
5.695	0.760	tINS	FR	16	R26C9[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F
6.495	0.800	tNET	RR	1	R24C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_11_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R24C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_11_s0/CLK
8.480	-0.032	tSu		1	R24C10[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_11_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.339, 37.041%; route: 3.576, 56.623%; tC2Q: 0.400, 6.336%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path94

Path Summary:

Slack	2.002
Data Arrival Time	14.549
Data Required Time	16.551
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wptr_0_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.914	0.983	tNET	FF	1	R7C15[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_opmode_o_d_1_s/I2
6.728	0.814	tINS	FF	12	R7C15[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_opmode_o_d_1_s/F
8.783	2.055	tNET	FF	1	R4C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/fifo_wr_data_7_s1/I1
9.247	0.464	tINS	FF	17	R4C9[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/fifo_wr_data_7_s1/F
10.972	1.726	tNET	FF	1	R7C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n24_s1/I3
11.566	0.594	tINS	FR	7	R7C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n24_s1/F
11.888	0.322	tNET	RR	1	R7C6[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbinnext_1_s3/I1
12.498	0.609	tINS	RF	2	R7C6[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbinnext_1_s3/F
12.506	0.008	tNET	FF	1	R7C6[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wgraynext_0_s1/I2
13.115	0.609	tINS	FF	2	R7C6[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wgraynext_0_s1/F
14.549	1.435	tNET	FF	1	R6C4[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wptr_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R6C4[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wptr_0_s0/CLK
16.551	-0.296	tSu		1	R6C4[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wptr_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.434, 37.822%; route: 8.594, 59.814%; tC2Q: 0.340, 2.364%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path95

Path Summary:

Slack	2.018
Data Arrival Time	14.797
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_10_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.177	0.853	tNET	FF	1	R6C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_11_s3/I0
13.937	0.760	tINS	FR	12	R6C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_11_s3/F
14.797	0.860	tNET	RR	1	R7C16[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_10_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R7C16[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_10_s1/CLK
16.816	-0.032	tSu		1	R7C16[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_10_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.756, 39.381%; route: 8.521, 58.296%; tC2Q: 0.340, 2.324%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path96

Path Summary:

Slack	2.018
Data Arrival Time	14.797
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_11_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.177	0.853	tNET	FF	1	R6C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_11_s3/I0
13.937	0.760	tINS	FR	12	R6C17[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_11_s3/F
14.797	0.860	tNET	RR	1	R7C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_11_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R7C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_11_s1/CLK
16.816	-0.032	tSu		1	R7C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/cnt_11_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.756, 39.381%; route: 8.521, 58.296%; tC2Q: 0.340, 2.324%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path97

Path Summary:

Slack	2.062
Data Arrival Time	14.490
Data Required Time	16.551
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_txready_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
14.490	2.166	tNET	FF	1	R4C19[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_txready_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R4C19[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_txready_s0/CLK
16.551	-0.296	tSu		1	R4C19[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/s_txready_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 4.996, 34.914%; route: 8.973, 62.712%; tC2Q: 0.340, 2.374%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path98

Path Summary:

Slack	2.081
Data Arrival Time	14.734
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_5_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.422	1.098	tNET	FF	1	R5C19[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s8/I3
14.208	0.786	tINS	FR	9	R5C19[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/n919_s8/F
14.734	0.526	tNET	RR	1	R5C21[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_5_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R5C21[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_5_s0/CLK
16.816	-0.032	tSu		1	R5C21[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_packet/PHY_DATAOUT_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 5.782, 39.730%; route: 8.432, 57.937%; tC2Q: 0.340, 2.334%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path99

Path Summary:

Slack	2.095
Data Arrival Time	14.721
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_1_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.051	0.727	tNET	FF	1	R5C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s7/I0
13.660	0.609	tINS	FF	1	R5C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s7/F
13.664	0.004	tNET	FF	1	R5C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s3/I3
14.127	0.463	tINS	FR	9	R5C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s3/F
14.721	0.594	tNET	RR	1	R4C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_1_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R4C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_1_s1/CLK
16.816	-0.032	tSu		1	R4C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 6.068, 41.733%; route: 8.133, 55.931%; tC2Q: 0.340, 2.336%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path100

Path Summary:

Slack	2.095
Data Arrival Time	14.721
Data Required Time	16.816
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_3_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.181	0.181	tNET	RR	1	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/CLK
0.520	0.340	tC2Q	RF	2	R14C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_3_s0/Q
1.959	1.438	tNET	FF	1	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/I1
2.773	0.814	tINS	FF	2	R9C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s6/F
2.781	0.008	tNET	FF	1	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I3
3.546	0.765	tINS	FF	4	R9C17[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F
4.166	0.620	tNET	FF	1	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/I2
4.930	0.765	tINS	FF	10	R7C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s0/F
5.555	0.624	tNET	FF	1	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2
6.369	0.814	tINS	FF	11	R6C15[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F
8.781	2.412	tNET	FF	1	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/I1
9.545	0.765	tINS	FF	8	R23C7[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n543_s2/F
11.243	1.697	tNET	FF	1	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/I1
11.852	0.609	tINS	FF	2	R5C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s0/F
11.860	0.008	tNET	FF	1	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/I0
12.324	0.464	tINS	FF	5	R5C9[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/utmi_txready_o_d_s/F
13.051	0.727	tNET	FF	1	R5C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s7/I0
13.660	0.609	tINS	FF	1	R5C17[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s7/F
13.664	0.004	tNET	FF	1	R5C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s3/I3
14.127	0.463	tINS	FR	9	R5C17[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_0_s3/F
14.721	0.594	tNET	RR	1	R4C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_3_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk60
16.667	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
16.848	0.181	tNET	RR	1	R4C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_3_s1/CLK
16.816	-0.032	tSu		1	R4C16[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/test_data_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 6.068, 41.733%; route: 8.133, 55.931%; tC2Q: 0.340, 2.336%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.305
Data Arrival Time	0.560
Data Required Time	0.255
From	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_next_8_s0
To	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R9C38[0][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_next_8_s0/CLK
0.384	0.247	tC2Q	RF	2	R9C38[0][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_next_8_s0/Q
0.560	0.177	tNET	FF	1	BSRAM_R10[9]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/ADB[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	BSRAM_R10[9]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKB
0.255	0.119	tHld		1	BSRAM_R10[9]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.177, 41.685%; tC2Q: 0.247, 58.315%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path2

Path Summary:

Slack	0.326
Data Arrival Time	0.581
Data Required Time	0.255
From	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_next_9_s0
To	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R9C38[0][B]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_next_9_s0/CLK
0.384	0.247	tC2Q	RR	2	R9C38[0][B]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_next_9_s0/Q
0.581	0.197	tNET	RR	1	BSRAM_R10[9]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/ADB[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	BSRAM_R10[9]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKB
0.255	0.119	tHld		1	BSRAM_R10[9]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.197, 44.393%; tC2Q: 0.247, 55.607%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path3

Path Summary:

Slack	0.357
Data Arrival Time	0.558
Data Required Time	0.201
From	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_5_s0
To	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_1_s
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R11C23[1][B]	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_5_s0/CLK
0.384	0.247	tC2Q	RF	2	R11C23[1][B]	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_5_s0/Q
0.558	0.174	tNET	FF	1	BSRAM_R10[6]	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_1_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	BSRAM_R10[6]	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_1_s/CLKA
0.201	0.064	tHld		1	BSRAM_R10[6]	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.174, 41.295%; tC2Q: 0.247, 58.705%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path4

Path Summary:

Slack	0.357
Data Arrival Time	0.558
Data Required Time	0.201
From	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_0_s0
To	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R11C20[2][A]	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_0_s0/CLK
0.384	0.247	tC2Q	RF	2	R11C20[2][A]	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_0_s0/Q
0.558	0.174	tNET	FF	1	BSRAM_R10[5]	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	BSRAM_R10[5]	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/CLKA
0.201	0.064	tHld		1	BSRAM_R10[5]	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.174, 41.295%; tC2Q: 0.247, 58.705%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path5

Path Summary:

Slack	0.380
Data Arrival Time	0.581
Data Required Time	0.201
From	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_1_s0
To	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R11C20[0][A]	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_1_s0/CLK
0.384	0.247	tC2Q	RR	2	R11C20[0][A]	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_1_s0/Q
0.581	0.197	tNET	RR	1	BSRAM_R10[5]	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	BSRAM_R10[5]	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/CLKA
0.201	0.064	tHld		1	BSRAM_R10[5]	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.197, 44.393%; tC2Q: 0.247, 55.607%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path6

Path Summary:

Slack	0.414
Data Arrival Time	0.560
Data Required Time	0.146
From	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_pktval_s0
To	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/pkg_wp_6_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R16C36[1][A]	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_pktval_s0/CLK
0.384	0.247	tC2Q	RR	13	R16C36[1][A]	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_pktval_s0/Q
0.560	0.176	tNET	RR	1	R16C36[2][B]	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/pkg_wp_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R16C36[2][B]	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/pkg_wp_6_s0/CLK
0.146	0.009	tHld		1	R16C36[2][B]	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/pkg_wp_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.176, 41.613%; tC2Q: 0.247, 58.387%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path7

Path Summary:

Slack	0.414
Data Arrival Time	0.560
Data Required Time	0.146
From	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_pktval_s0
To	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/pkg_wp_10_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R16C36[1][A]	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_pktval_s0/CLK
0.384	0.247	tC2Q	RR	13	R16C36[1][A]	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_pktval_s0/Q
0.560	0.176	tNET	RR	1	R16C36[2][A]	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/pkg_wp_10_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R16C36[2][A]	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/pkg_wp_10_s0/CLK
0.146	0.009	tHld		1	R16C36[2][A]	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/pkg_wp_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.176, 41.613%; tC2Q: 0.247, 58.387%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path8

Path Summary:

Slack	0.415
Data Arrival Time	0.560
Data Required Time	0.145
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/E4_0_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/DVE_1_s0
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.136	0.136	tNET	RR	1	R22C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/E4_0_s0/CLK
0.383	0.247	tC2Q	RR	8	R22C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/E4_0_s0/Q
0.560	0.177	tNET	RR	1	R22C11[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/DVE_1_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.136	0.136	tNET	RR	1	R22C11[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/DVE_1_s0/CLK
0.145	0.009	tHld		1	R22C11[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/DVE_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.177, 41.734%; tC2Q: 0.247, 58.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path9

Path Summary:

Slack	0.436
Data Arrival Time	0.581
Data Required Time	0.145
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/E4_2_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/DVE_0_s0
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.136	0.136	tNET	RR	1	R22C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/E4_2_s0/CLK
0.383	0.247	tC2Q	RR	7	R22C11[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/E4_2_s0/Q
0.581	0.198	tNET	RR	1	R22C12[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/DVE_0_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.136	0.136	tNET	RR	1	R22C12[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/DVE_0_s0/CLK
0.145	0.009	tHld		1	R22C12[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/DVE_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.198, 44.502%; tC2Q: 0.247, 55.498%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path10

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_q_s4
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_q_s4
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R21C13[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_q_s4/CLK
0.384	0.247	tC2Q	RR	4	R21C13[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_q_s4/Q
0.386	0.002	tNET	RR	1	R21C13[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n55_s2/I0
0.661	0.276	tINS	RF	1	R21C13[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n55_s2/F
0.661	0.000	tNET	FF	1	R21C13[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_q_s4/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R21C13[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_q_s4/CLK
0.137	0.000	tHld		1	R21C13[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_q_s4

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path11

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/ones_count_q_0_s1
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/ones_count_q_0_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R3C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/ones_count_q_0_s1/CLK
0.384	0.247	tC2Q	RR	5	R3C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/ones_count_q_0_s1/Q
0.386	0.002	tNET	RR	1	R3C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n766_s2/I0
0.661	0.276	tINS	RF	1	R3C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n766_s2/F
0.661	0.000	tNET	FF	1	R3C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/ones_count_q_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R3C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/ones_count_q_0_s1/CLK
0.137	0.000	tHld		1	R3C11[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/ones_count_q_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path12

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/ones_count_q_1_s1
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/ones_count_q_1_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R3C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/ones_count_q_1_s1/CLK
0.384	0.247	tC2Q	RR	4	R3C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/ones_count_q_1_s1/Q
0.386	0.002	tNET	RR	1	R3C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n765_s3/I1
0.661	0.276	tINS	RF	1	R3C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n765_s3/F
0.661	0.000	tNET	FF	1	R3C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/ones_count_q_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R3C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/ones_count_q_1_s1/CLK
0.137	0.000	tHld		1	R3C11[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/ones_count_q_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path13

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/sample_cnt_q_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/sample_cnt_q_1_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R3C13[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/sample_cnt_q_1_s0/CLK
0.384	0.247	tC2Q	RR	6	R3C13[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/sample_cnt_q_1_s0/Q
0.386	0.002	tNET	RR	1	R3C13[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n702_s2/I2
0.661	0.276	tINS	RF	1	R3C13[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n702_s2/F
0.661	0.000	tNET	FF	1	R3C13[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/sample_cnt_q_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R3C13[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/sample_cnt_q_1_s0/CLK
0.137	0.000	tHld		1	R3C13[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/sample_cnt_q_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path14

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/sample_cnt_q_5_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/sample_cnt_q_5_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R3C12[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/sample_cnt_q_5_s0/CLK
0.384	0.247	tC2Q	RR	3	R3C12[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/sample_cnt_q_5_s0/Q
0.386	0.002	tNET	RR	1	R3C12[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n698_s2/I2
0.661	0.276	tINS	RF	1	R3C12[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n698_s2/F
0.661	0.000	tNET	FF	1	R3C12[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/sample_cnt_q_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R3C12[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/sample_cnt_q_5_s0/CLK
0.137	0.000	tHld		1	R3C12[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/sample_cnt_q_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path15

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_3_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_3_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R4C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_3_s0/CLK
0.384	0.247	tC2Q	RR	6	R4C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_3_s0/Q
0.386	0.002	tNET	RR	1	R4C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n621_s1/I1
0.661	0.276	tINS	RF	1	R4C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n621_s1/F
0.661	0.000	tNET	FF	1	R4C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R4C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_3_s0/CLK
0.137	0.000	tHld		1	R4C7[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path16

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_9_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_9_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R3C8[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_9_s0/CLK
0.384	0.247	tC2Q	RR	6	R3C8[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_9_s0/Q
0.386	0.002	tNET	RR	1	R3C8[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n615_s1/I1
0.661	0.276	tINS	RF	1	R3C8[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n615_s1/F
0.661	0.000	tNET	FF	1	R3C8[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R3C8[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_9_s0/CLK
0.137	0.000	tHld		1	R3C8[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_9_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path17

Path Summary:

Slack	0.524
Data Arrival Time	0.660
Data Required Time	0.136
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/rx_en_s2
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/rx_en_s2
Launch Clk	clk120:[R]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.136	0.136	tNET	RR	1	R26C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/rx_en_s2/CLK
0.383	0.247	tC2Q	RR	2	R26C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/rx_en_s2/Q
0.384	0.002	tNET	RR	1	R26C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n239_s4/I1
0.660	0.276	tINS	RF	1	R26C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n239_s4/F
0.660	0.000	tNET	FF	1	R26C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/rx_en_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk120
0.000	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.136	0.136	tNET	RR	1	R26C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/rx_en_s2/CLK
0.136	0.000	tHld		1	R26C9[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/rx_en_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path18

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/q_tx_cnt_7_s1
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/q_tx_cnt_7_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R25C6[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/q_tx_cnt_7_s1/CLK
0.384	0.247	tC2Q	RR	2	R25C6[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/q_tx_cnt_7_s1/Q
0.386	0.002	tNET	RR	1	R25C6[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n405_s10/I1
0.661	0.276	tINS	RF	1	R25C6[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n405_s10/F
0.661	0.000	tNET	FF	1	R25C6[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/q_tx_cnt_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R25C6[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/q_tx_cnt_7_s1/CLK
0.137	0.000	tHld		1	R25C6[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/q_tx_cnt_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path19

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/se0_det_counter_11_s3
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/se0_det_counter_11_s3
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C3[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/se0_det_counter_11_s3/CLK
0.384	0.247	tC2Q	RR	2	R15C3[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/se0_det_counter_11_s3/Q
0.386	0.002	tNET	RR	1	R15C3[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n65_s5/I3
0.661	0.276	tINS	RF	1	R15C3[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n65_s5/F
0.661	0.000	tNET	FF	1	R15C3[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/se0_det_counter_11_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C3[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/se0_det_counter_11_s3/CLK
0.137	0.000	tHld		1	R15C3[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/se0_det_counter_11_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path20

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/se0_det_counter_2_s1
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/se0_det_counter_2_s1
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C3[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/se0_det_counter_2_s1/CLK
0.384	0.247	tC2Q	RR	3	R15C3[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/se0_det_counter_2_s1/Q
0.386	0.002	tNET	RR	1	R15C3[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n74_s2/I3
0.661	0.276	tINS	RF	1	R15C3[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n74_s2/F
0.661	0.000	tNET	FF	1	R15C3[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/se0_det_counter_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C3[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/se0_det_counter_2_s1/CLK
0.137	0.000	tHld		1	R15C3[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/se0_det_counter_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path21

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_interface_set_s6
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_interface_set_s6
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C22[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_interface_set_s6/CLK
0.384	0.247	tC2Q	RR	3	R15C22[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_interface_set_s6/Q
0.386	0.002	tNET	RR	1	R15C22[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1619_s5/I1
0.661	0.276	tINS	RF	1	R15C22[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1619_s5/F
0.661	0.000	tNET	FF	1	R15C22[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_interface_set_s6/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C22[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_interface_set_s6/CLK
0.137	0.000	tHld		1	R15C22[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_interface_set_s6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path22

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_1_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_1_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R14C23[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_1_s0/CLK
0.384	0.247	tC2Q	RR	2	R14C23[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_1_s0/Q
0.386	0.002	tNET	RR	1	R14C23[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1880_s17/I0
0.661	0.276	tINS	RF	1	R14C23[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1880_s17/F
0.661	0.000	tNET	FF	1	R14C23[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R14C23[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_1_s0/CLK
0.137	0.000	tHld		1	R14C23[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path23

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_4_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_4_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C23[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_4_s0/CLK
0.384	0.247	tC2Q	RR	2	R15C23[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_4_s0/Q
0.386	0.002	tNET	RR	1	R15C23[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1874_s17/I0
0.661	0.276	tINS	RF	1	R15C23[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1874_s17/F
0.661	0.000	tNET	FF	1	R15C23[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C23[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_4_s0/CLK
0.137	0.000	tHld		1	R15C23[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path24

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_6_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_6_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R14C23[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_6_s0/CLK
0.384	0.247	tC2Q	RR	2	R14C23[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_6_s0/Q
0.386	0.002	tNET	RR	1	R14C23[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1870_s17/I0
0.661	0.276	tINS	RF	1	R14C23[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1870_s17/F
0.661	0.000	tNET	FF	1	R14C23[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R14C23[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_6_s0/CLK
0.137	0.000	tHld		1	R14C23[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path25

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R17C22[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0/CLK
0.384	0.247	tC2Q	RR	16	R17C22[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0/Q
0.386	0.002	tNET	RR	1	R17C22[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n363_s11/I2
0.661	0.276	tINS	RF	1	R17C22[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n363_s11/F
0.661	0.000	tNET	FF	1	R17C22[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R17C22[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0/CLK
0.137	0.000	tHld		1	R17C22[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.384
Data Arrival Time	7.976
Data Required Time	8.360
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.976	3.279	tNET	FF	8	BSRAM_R10[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/RESETB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	BSRAM_R10[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/CLKB
8.360	-0.152	tSu		1	BSRAM_R10[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.279, 90.614%; tC2Q: 0.340, 9.386%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path2

Path Summary:

Slack	0.490
Data Arrival Time	7.990
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_2_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.990	3.293	tNET	FF	1	R21C3[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R21C3[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_2_s0/CLK
8.480	-0.032	tSu		1	R21C3[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_2_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.293, 90.652%; tC2Q: 0.340, 9.348%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path3

Path Summary:

Slack	0.490
Data Arrival Time	7.990
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_3_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.990	3.293	tNET	FF	1	R21C3[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R21C3[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_3_s0/CLK
8.480	-0.032	tSu		1	R21C3[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_3_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.293, 90.652%; tC2Q: 0.340, 9.348%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path4

Path Summary:

Slack	0.490
Data Arrival Time	7.990
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_4_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.990	3.293	tNET	FF	1	R21C3[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R21C3[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_4_s0/CLK
8.480	-0.032	tSu		1	R21C3[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_4_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.293, 90.652%; tC2Q: 0.340, 9.348%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path5

Path Summary:

Slack	0.490
Data Arrival Time	7.990
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_1_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.990	3.293	tNET	FF	1	R21C3[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R21C3[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_1_s0/CLK
8.480	-0.032	tSu		1	R21C3[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_1_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.293, 90.652%; tC2Q: 0.340, 9.348%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path6

Path Summary:

Slack	0.490
Data Arrival Time	7.990
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_2_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.990	3.293	tNET	FF	1	R21C3[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R21C3[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_2_s0/CLK
8.480	-0.032	tSu		1	R21C3[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_2_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.293, 90.652%; tC2Q: 0.340, 9.348%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path7

Path Summary:

Slack	0.497
Data Arrival Time	7.983
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.983	3.286	tNET	FF	1	R9C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R9C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0/CLK
8.480	-0.032	tSu		1	R9C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.286, 90.633%; tC2Q: 0.340, 9.367%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path8

Path Summary:

Slack	0.497
Data Arrival Time	7.983
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_3_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.983	3.286	tNET	FF	1	R8C5[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R8C5[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_3_s0/CLK
8.480	-0.032	tSu		1	R8C5[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_3_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.286, 90.633%; tC2Q: 0.340, 9.367%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path9

Path Summary:

Slack	0.497
Data Arrival Time	7.983
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_0_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.983	3.286	tNET	FF	1	R9C5[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R9C5[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_0_s0/CLK
8.480	-0.032	tSu		1	R9C5[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_0_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.286, 90.633%; tC2Q: 0.340, 9.367%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path10

Path Summary:

Slack	0.497
Data Arrival Time	7.983
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_1_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.983	3.286	tNET	FF	1	R9C5[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R9C5[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_1_s0/CLK
8.480	-0.032	tSu		1	R9C5[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_1_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.286, 90.633%; tC2Q: 0.340, 9.367%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path11

Path Summary:

Slack	0.497
Data Arrival Time	7.983
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_5_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.983	3.286	tNET	FF	1	R8C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R8C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_5_s0/CLK
8.480	-0.032	tSu		1	R8C5[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_5_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.286, 90.633%; tC2Q: 0.340, 9.367%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path12

Path Summary:

Slack	0.497
Data Arrival Time	7.983
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Full_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.983	3.286	tNET	FF	1	R21C4[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Full_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R21C4[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Full_s0/CLK
8.480	-0.032	tSu		1	R21C4[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Full_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.286, 90.633%; tC2Q: 0.340, 9.367%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path13

Path Summary:

Slack	0.497
Data Arrival Time	7.983
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_0_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.983	3.286	tNET	FF	1	R23C5[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R23C5[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_0_s0/CLK
8.480	-0.032	tSu		1	R23C5[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_0_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.286, 90.633%; tC2Q: 0.340, 9.367%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path14

Path Summary:

Slack	0.497
Data Arrival Time	7.983
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_1_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.983	3.286	tNET	FF	1	R23C5[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R23C5[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_1_s0/CLK
8.480	-0.032	tSu		1	R23C5[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_1_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.286, 90.633%; tC2Q: 0.340, 9.367%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path15

Path Summary:

Slack	0.497
Data Arrival Time	7.983
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_2_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.983	3.286	tNET	FF	1	R23C5[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R23C5[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_2_s0/CLK
8.480	-0.032	tSu		1	R23C5[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_2_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.286, 90.633%; tC2Q: 0.340, 9.367%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path16

Path Summary:

Slack	0.497
Data Arrival Time	7.983
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_0_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.983	3.286	tNET	FF	1	R21C5[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R21C5[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_0_s0/CLK
8.480	-0.032	tSu		1	R21C5[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_0_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.286, 90.633%; tC2Q: 0.340, 9.367%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path17

Path Summary:

Slack	0.497
Data Arrival Time	7.983
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_4_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.983	3.286	tNET	FF	1	R21C5[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R21C5[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_4_s0/CLK
8.480	-0.032	tSu		1	R21C5[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_4_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.286, 90.633%; tC2Q: 0.340, 9.367%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path18

Path Summary:

Slack	0.497
Data Arrival Time	7.983
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_5_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.983	3.286	tNET	FF	1	R21C5[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R21C5[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_5_s0/CLK
8.480	-0.032	tSu		1	R21C5[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_5_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.286, 90.633%; tC2Q: 0.340, 9.367%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path19

Path Summary:

Slack	0.497
Data Arrival Time	7.983
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_1_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.983	3.286	tNET	FF	1	R21C4[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R21C4[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_1_s0/CLK
8.480	-0.032	tSu		1	R21C4[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_1_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.286, 90.633%; tC2Q: 0.340, 9.367%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path20

Path Summary:

Slack	0.497
Data Arrival Time	7.983
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_5_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.983	3.286	tNET	FF	1	R21C5[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R21C5[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_5_s0/CLK
8.480	-0.032	tSu		1	R21C5[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_5_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.286, 90.633%; tC2Q: 0.340, 9.367%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path21

Path Summary:

Slack	0.497
Data Arrival Time	7.983
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_0_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.983	3.286	tNET	FF	1	R21C2[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R21C2[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_0_s0/CLK
8.480	-0.032	tSu		1	R21C2[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_0_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.286, 90.633%; tC2Q: 0.340, 9.367%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path22

Path Summary:

Slack	0.497
Data Arrival Time	7.983
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_3_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.983	3.286	tNET	FF	1	R21C2[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R21C2[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_3_s0/CLK
8.480	-0.032	tSu		1	R21C2[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_3_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.286, 90.633%; tC2Q: 0.340, 9.367%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path23

Path Summary:

Slack	0.497
Data Arrival Time	7.983
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_4_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.983	3.286	tNET	FF	1	R21C2[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R21C2[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_4_s0/CLK
8.480	-0.032	tSu		1	R21C2[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_4_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.286, 90.633%; tC2Q: 0.340, 9.367%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path24

Path Summary:

Slack	0.504
Data Arrival Time	7.976
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_0_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.976	3.279	tNET	FF	1	R9C4[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R9C4[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_0_s0/CLK
8.480	-0.032	tSu		1	R9C4[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_0_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.279, 90.614%; tC2Q: 0.340, 9.386%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path25

Path Summary:

Slack	0.504
Data Arrival Time	7.976
Data Required Time	8.480
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_1_s0
Launch Clk	clk120:[F]
Latch Clk	clk120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk120
4.167	0.000	tCL	FF	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	1	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
4.697	0.340	tC2Q	FF	46	R23C5[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.976	3.279	tNET	FF	1	R8C4[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk120
8.333	0.000	tCL	RR	161	BOTTOMSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.512	0.179	tNET	RR	1	R8C4[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_1_s0/CLK
8.480	-0.032	tSu		1	R8C4[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_1_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.190, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.279, 90.614%; tC2Q: 0.340, 9.386%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/Empty_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R8C42[1][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/Empty_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R8C42[1][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/Empty_s0/CLK
0.146	0.009	tHld		1	R8C42[1][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/Empty_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path2

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/AlmostFull_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R9C44[0][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/AlmostFull_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R9C44[0][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/AlmostFull_s0/CLK
0.146	0.009	tHld		1	R9C44[0][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/AlmostFull_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path3

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/Full_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R7C44[0][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/Full_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R7C44[0][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/Full_s0/CLK
0.146	0.009	tHld		1	R7C44[0][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/Full_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path4

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_0_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R6C45[2][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R6C45[2][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_0_s0/CLK
0.146	0.009	tHld		1	R6C45[2][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path5

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_1_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R8C45[1][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R8C45[1][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_1_s0/CLK
0.146	0.009	tHld		1	R8C45[1][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path6

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_2_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R8C45[2][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R8C45[2][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_2_s0/CLK
0.146	0.009	tHld		1	R8C45[2][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path7

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_3_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R9C44[0][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R9C44[0][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_3_s0/CLK
0.146	0.009	tHld		1	R9C44[0][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path8

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_4_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R7C45[0][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R7C45[0][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_4_s0/CLK
0.146	0.009	tHld		1	R7C45[0][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path9

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_5_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R7C45[1][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R7C45[1][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_5_s0/CLK
0.146	0.009	tHld		1	R7C45[1][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path10

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_0_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R8C46[1][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R8C46[1][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_0_s0/CLK
0.146	0.009	tHld		1	R8C46[1][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path11

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_1_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R8C45[0][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R8C45[0][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_1_s0/CLK
0.146	0.009	tHld		1	R8C45[0][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path12

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_2_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R8C45[0][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R8C45[0][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_2_s0/CLK
0.146	0.009	tHld		1	R8C45[0][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path13

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_3_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R5C43[1][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R5C43[1][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_3_s0/CLK
0.146	0.009	tHld		1	R5C43[1][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path14

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_4_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R7C46[0][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R7C46[0][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_4_s0/CLK
0.146	0.009	tHld		1	R7C46[0][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path15

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_5_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R6C44[0][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R6C44[0][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_5_s0/CLK
0.146	0.009	tHld		1	R6C44[0][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path16

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_6_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R6C44[0][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R6C44[0][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_6_s0/CLK
0.146	0.009	tHld		1	R6C44[0][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path17

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_0_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R7C40[0][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R7C40[0][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_0_s0/CLK
0.146	0.009	tHld		1	R7C40[0][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path18

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_1_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R7C42[2][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R7C42[2][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_1_s0/CLK
0.146	0.009	tHld		1	R7C42[2][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path19

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_2_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R8C41[2][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R8C41[2][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_2_s0/CLK
0.146	0.009	tHld		1	R8C41[2][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path20

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_3_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R7C42[2][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R7C42[2][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_3_s0/CLK
0.146	0.009	tHld		1	R7C42[2][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path21

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_4_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R8C41[2][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R8C41[2][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_4_s0/CLK
0.146	0.009	tHld		1	R8C41[2][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path22

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_5_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R8C41[0][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R8C41[0][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_5_s0/CLK
0.146	0.009	tHld		1	R8C41[0][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path23

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_0_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R8C42[1][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R8C42[1][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_0_s0/CLK
0.146	0.009	tHld		1	R8C42[1][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path24

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_1_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R7C43[2][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R7C43[2][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_1_s0/CLK
0.146	0.009	tHld		1	R7C43[2][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path25

Path Summary:

Slack	1.344
Data Arrival Time	1.490
Data Required Time	0.146
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_2_s0
Launch Clk	clk60:[R]
Latch Clk	clk60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.384	0.247	tC2Q	RR	753	R15C31[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
1.490	1.106	tNET	RR	1	R8C42[2][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk60
0.000	0.000	tCL	RR	1442	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R8C42[2][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_2_s0/CLK
0.146	0.009	tHld		1	R8C42[2][A]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.106, 81.748%; tC2Q: 0.247, 18.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.185
Actual Width:	4.111
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.469	0.136	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_2_s0/CLK

MPW2

MPW Summary:

Slack:	3.185
Actual Width:	4.111
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/data_out_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/data_out_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.469	0.136	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/data_out_0_s0/CLK

MPW3

MPW Summary:

Slack:	3.185
Actual Width:	4.111
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.469	0.136	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_3_s0/CLK

MPW4

MPW Summary:

Slack:	3.185
Actual Width:	4.111
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.469	0.136	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_2_s0/CLK

MPW5

MPW Summary:

Slack:	3.185
Actual Width:	4.111
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.469	0.136	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_1_s0/CLK

MPW6

MPW Summary:

Slack:	3.185
Actual Width:	4.111
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.469	0.136	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_0_s0/CLK

MPW7

MPW Summary:

Slack:	3.185
Actual Width:	4.111
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.469	0.136	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_1_s0/CLK

MPW8

MPW Summary:

Slack:	3.185
Actual Width:	4.111
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.469	0.136	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_2_s0/CLK

MPW9

MPW Summary:

Slack:	3.185
Actual Width:	4.111
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.469	0.136	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/CLKB

MPW10

MPW Summary:

Slack:	3.185
Actual Width:	4.111
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.357	0.190	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
8.469	0.136	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_0_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
1442	PHY_CLKOUT	0.039	0.195
753	usb_busreset	8.667	2.440
474	RESET	1.509	2.788
161	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/sclk	0.115	0.190
77	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/state_0[2]	0.039	2.125
65	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1619_4	6.293	1.589
64	endpt_sel[0]	2.346	2.881
64	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1619_11	6.293	3.026
48	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/DESC_INDEX[0]	2.104	2.694
47	DESCROM_RADDR[3]	1.420	1.986

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C2	100.00%
R2C3	100.00%
R2C16	100.00%
R2C18	100.00%
R2C19	100.00%
R4C24	100.00%
R4C25	100.00%
R13C7	100.00%
R13C8	100.00%
R24C28	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk60 -period 16.667 -waveform {0 8.334} [get_nets {PHY_CLKOUT}]
TC_CLOCK	Actived	create_clock -name clk120 -period 8.333 -waveform {0 4.167} [get_nets {u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/sclk}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk60}] -to [get_clocks {clk120}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk120}] -to [get_clocks {clk60}]
TC_REPORT_TIMING	Actived	report_timing -setup -max_paths 100 -max_common_paths 1