Timing Messages
| Report Title | Timing Analysis Report |
| Design File | D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj60k_usb2_loopback_speed\prj60k_usb2_loopback_speed_dual_lvds\project\impl\gwsynthesis\gowin_usb_refdesign.vg |
| Physical Constraints File | D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj60k_usb2_loopback_speed\prj60k_usb2_loopback_speed_dual_lvds\project\src\usb_ref.cst |
| Timing Constraint File | D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj60k_usb2_loopback_speed\prj60k_usb2_loopback_speed_dual_lvds\project\src\gowin_usb_refdesign.sdc |
| Tool Version | V1.9.12 (64-bit) |
| Part Number | GW5AT-LV60UG225C1/I0 |
| Device | GW5AT-60 |
| Device Version | B |
| Created Time | Thu Nov 6 09:29:39 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
| Setup Delay Model | Slow 0.855V 0C C1/I0 |
| Hold Delay Model | Fast 0.945V 85C C1/I0 |
| Numbers of Paths Analyzed | 10700 |
| Numbers of Endpoints Analyzed | 12068 |
| Numbers of Falling Endpoints | 4 |
| Numbers of Setup Violated Endpoints | 0 |
| Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk60 | Base | 16.667 | 59.999 | 0.000 | 8.334 | PHY_CLKOUT | ||
| 2 | clk120 | Base | 8.333 | 120.005 | 0.000 | 4.167 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/sclk | ||
| 3 | CLK_IN | Base | 41.667 | 24.000 | 0.000 | 20.833 | CLK_IN_ibuf/I | ||
| 4 | pll/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | Generated | 1.042 | 960.000 | 0.000 | 0.521 | CLK_IN_ibuf/I | CLK_IN | pll/u_pll/PLLA_inst/CLKOUT1 |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk60 | 59.999(MHz) | 75.418(MHz) | 17 | TOP |
| 2 | clk120 | 120.005(MHz) | 130.922(MHz) | 4 | TOP |
| 3 | CLK_IN | 24.000(MHz) | 188.014(MHz) | 6 | TOP |
No timing paths to get frequency of pll/u_pll/PLLA_inst/CLKOUT1.default_gen_clk!
Total Negative Slack Summary:
| Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
|---|---|---|---|
| clk60 | Setup | 0.000 | 0 |
| clk60 | Hold | 0.000 | 0 |
| clk120 | Setup | 0.000 | 0 |
| clk120 | Hold | 0.000 | 0 |
| CLK_IN | Setup | 0.000 | 0 |
| CLK_IN | Hold | 0.000 | 0 |
| pll/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | Setup | 0.000 | 0 |
| pll/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.695 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_15_s0/RESET | clk120:[R] | clk120:[R] | 8.333 | 0.028 | 7.238 |
| 2 | 0.695 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_4_s0/RESET | clk120:[R] | clk120:[R] | 8.333 | 0.028 | 7.238 |
| 3 | 0.695 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_11_s0/RESET | clk120:[R] | clk120:[R] | 8.333 | 0.028 | 7.238 |
| 4 | 0.704 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_3_s0/RESET | clk120:[R] | clk120:[R] | 8.333 | 0.019 | 7.238 |
| 5 | 0.704 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_7_s0/RESET | clk120:[R] | clk120:[R] | 8.333 | 0.019 | 7.238 |
| 6 | 0.924 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_12_s0/RESET | clk120:[R] | clk120:[R] | 8.333 | 0.019 | 7.017 |
| 7 | 1.012 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_0_s0/RESET | clk120:[R] | clk120:[R] | 8.333 | 0.019 | 6.930 |
| 8 | 1.012 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_8_s0/RESET | clk120:[R] | clk120:[R] | 8.333 | 0.019 | 6.930 |
| 9 | 1.021 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_13_s0/RESET | clk120:[R] | clk120:[R] | 8.333 | 0.009 | 6.930 |
| 10 | 1.081 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_1_s0/RESET | clk120:[R] | clk120:[R] | 8.333 | 0.009 | 6.870 |
| 11 | 1.081 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_5_s0/RESET | clk120:[R] | clk120:[R] | 8.333 | 0.009 | 6.870 |
| 12 | 1.081 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_9_s0/RESET | clk120:[R] | clk120:[R] | 8.333 | 0.009 | 6.870 |
| 13 | 1.207 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_14_s0/RESET | clk120:[R] | clk120:[R] | 8.333 | 0.019 | 6.735 |
| 14 | 1.264 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_2_s0/RESET | clk120:[R] | clk120:[R] | 8.333 | 0.019 | 6.677 |
| 15 | 1.264 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_6_s0/RESET | clk120:[R] | clk120:[R] | 8.333 | 0.019 | 6.677 |
| 16 | 1.351 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_10_s0/RESET | clk120:[R] | clk120:[R] | 8.333 | 0.019 | 6.591 |
| 17 | 1.562 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides16/Q4 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/dru_locked_s2/D | clk120:[R] | clk120:[R] | 8.333 | 0.019 | 6.689 |
| 18 | 2.071 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides16/Q6 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s0/D | clk120:[R] | clk120:[R] | 8.333 | 0.019 | 6.254 |
| 19 | 2.143 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides16/Q9 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s0/D | clk120:[R] | clk120:[R] | 8.333 | 0.019 | 6.184 |
| 20 | 2.243 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/eop_dect_0_s0/D | clk120:[R] | clk120:[R] | 8.333 | 0.019 | 6.008 |
| 21 | 2.304 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/rx_en_s2/D | clk120:[R] | clk120:[R] | 8.333 | 0.019 | 5.946 |
| 22 | 2.304 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/eop_dect_2_s0/D | clk120:[R] | clk120:[R] | 8.333 | 0.019 | 5.946 |
| 23 | 2.304 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/eop_dect_1_s0/D | clk120:[R] | clk120:[R] | 8.333 | 0.019 | 5.946 |
| 24 | 2.304 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/eop_dect_3_s0/D | clk120:[R] | clk120:[R] | 8.333 | 0.019 | 5.946 |
| 25 | 2.312 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0/D | clk120:[R] | clk120:[R] | 8.333 | 0.009 | 5.947 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.141 | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_1_s0/Q | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/DI[1] | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 0.178 |
| 2 | 0.141 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_d0_0_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/oser16txd/D0 | clk120:[R] | clk120:[R] | 0.000 | -0.003 | 0.240 |
| 3 | 0.154 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_d0_0_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/oser16txd/D1 | clk120:[R] | clk120:[R] | 0.000 | -0.003 | 0.240 |
| 4 | 0.202 | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_0_s0/Q | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/DI[0] | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 0.239 |
| 5 | 0.208 | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_2_s0/Q | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/DI[2] | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 0.245 |
| 6 | 0.244 | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_3_s0/Q | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/DI[3] | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 0.281 |
| 7 | 0.248 | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_next_7_s0/Q | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/ADB[9] | clk60:[R] | clk60:[R] | 0.000 | -0.004 | 0.287 |
| 8 | 0.251 | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_6_s0/Q | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_1_s/DI[2] | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 0.288 |
| 9 | 0.253 | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_next_6_s0/Q | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/ADB[8] | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 0.288 |
| 10 | 0.254 | usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/Q_1_s0/Q | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/DI[1] | clk60:[R] | clk60:[R] | 0.000 | -0.012 | 0.302 |
| 11 | 0.256 | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/wp_6_s0/Q | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s/ADA[8] | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 0.293 |
| 12 | 0.263 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbin_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/ADA[4] | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 0.300 |
| 13 | 0.263 | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_next_0_s0/Q | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/ADB[2] | clk60:[R] | clk60:[R] | 0.000 | -0.004 | 0.302 |
| 14 | 0.269 | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_next_0_s0/Q | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/ADB[2] | clk60:[R] | clk60:[R] | 0.000 | 0.004 | 0.300 |
| 15 | 0.275 | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wq1_rptr_2_s0/Q | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wq2_rptr_2_s0/D | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 0.222 |
| 16 | 0.275 | usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/rptr_3_s0/Q | usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/wq1_rptr_3_s0/D | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 0.222 |
| 17 | 0.275 | usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/rptr_4_s0/Q | usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/wq1_rptr_4_s0/D | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 0.222 |
| 18 | 0.275 | u_usb_uart_config/test_tx_count_5_s1/Q | u_usb_uart_config/test_tx_count_5_s1/D | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 0.300 |
| 19 | 0.275 | u_usb_uart_config/test_rd_addr_7_s1/Q | u_usb_uart_config/test_rd_addr_7_s1/D | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 0.300 |
| 20 | 0.275 | u_usb_uart_config/endpt0_txcork_s0/Q | u_usb_uart_config/endpt0_txcork_s0/D | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 0.300 |
| 21 | 0.275 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_q_s4/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_q_s4/D | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 0.300 |
| 22 | 0.275 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rx_dp_q_s4/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rx_dp_q_s4/D | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 0.300 |
| 23 | 0.275 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_ms_s4/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_ms_s4/D | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 0.300 |
| 24 | 0.275 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_14_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_14_s0/D | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 0.300 |
| 25 | 0.275 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/q_tx_cnt_0_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/q_tx_cnt_0_s0/D | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 0.300 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 1.727 | reset_cnt_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_r_1_s0/PRESET | clk60:[R] | clk60:[F] | 8.334 | 0.032 | 6.283 |
| 2 | 1.727 | reset_cnt_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_r_0_s0/PRESET | clk60:[R] | clk60:[F] | 8.334 | 0.032 | 6.283 |
| 3 | 1.868 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_0_s0/CLEAR | clk120:[F] | clk120:[R] | 4.166 | -0.013 | 1.964 |
| 4 | 1.868 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_2_s0/CLEAR | clk120:[F] | clk120:[R] | 4.166 | -0.013 | 1.964 |
| 5 | 2.260 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0/PRESET | clk120:[F] | clk120:[R] | 4.166 | -0.013 | 1.571 |
| 6 | 2.260 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_0_s0/CLEAR | clk120:[F] | clk120:[R] | 4.166 | -0.013 | 1.571 |
| 7 | 2.260 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_1_s0/CLEAR | clk120:[F] | clk120:[R] | 4.166 | -0.013 | 1.571 |
| 8 | 2.260 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_3_s0/CLEAR | clk120:[F] | clk120:[R] | 4.166 | -0.013 | 1.571 |
| 9 | 2.260 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_0_s0/CLEAR | clk120:[F] | clk120:[R] | 4.166 | -0.013 | 1.571 |
| 10 | 2.260 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_1_s0/CLEAR | clk120:[F] | clk120:[R] | 4.166 | -0.013 | 1.571 |
| 11 | 2.260 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_3_s0/CLEAR | clk120:[F] | clk120:[R] | 4.166 | -0.013 | 1.571 |
| 12 | 2.392 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_0_s0/CLEAR | clk120:[F] | clk120:[R] | 4.166 | -0.004 | 1.430 |
| 13 | 2.392 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_1_s0/CLEAR | clk120:[F] | clk120:[R] | 4.166 | -0.004 | 1.430 |
| 14 | 2.392 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_2_s0/CLEAR | clk120:[F] | clk120:[R] | 4.166 | -0.004 | 1.430 |
| 15 | 2.392 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_1_s0/CLEAR | clk120:[F] | clk120:[R] | 4.166 | -0.004 | 1.430 |
| 16 | 2.505 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_4_s0/CLEAR | clk120:[F] | clk120:[R] | 4.166 | -0.013 | 1.326 |
| 17 | 2.627 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_3_s0/CLEAR | clk120:[F] | clk120:[R] | 4.166 | -0.013 | 1.205 |
| 18 | 2.627 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_4_s0/CLEAR | clk120:[F] | clk120:[R] | 4.166 | -0.013 | 1.205 |
| 19 | 2.627 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_5_s0/CLEAR | clk120:[F] | clk120:[R] | 4.166 | -0.013 | 1.205 |
| 20 | 2.714 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_1_s0/CLEAR | clk120:[F] | clk120:[R] | 4.166 | -0.004 | 1.109 |
| 21 | 2.714 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_3_s0/CLEAR | clk120:[F] | clk120:[R] | 4.166 | -0.004 | 1.109 |
| 22 | 2.714 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_2_s0/CLEAR | clk120:[F] | clk120:[R] | 4.166 | -0.004 | 1.109 |
| 23 | 2.714 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_5_s0/CLEAR | clk120:[F] | clk120:[R] | 4.166 | -0.004 | 1.109 |
| 24 | 2.722 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_2_s0/CLEAR | clk120:[F] | clk120:[R] | 4.166 | -0.013 | 1.110 |
| 25 | 2.722 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_4_s0/CLEAR | clk120:[F] | clk120:[R] | 4.166 | -0.013 | 1.110 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 1.367 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_1_s/RESET | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 1.356 |
| 2 | 1.367 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/RESET | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 1.356 |
| 3 | 1.367 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/RESET | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 1.356 |
| 4 | 1.367 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/RESET | clk60:[R] | clk60:[R] | 0.000 | 0.004 | 1.352 |
| 5 | 1.367 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/RESET | clk60:[R] | clk60:[R] | 0.000 | 0.004 | 1.352 |
| 6 | 1.367 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s/RESET | clk60:[R] | clk60:[R] | 0.000 | 0.004 | 1.352 |
| 7 | 1.371 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s/RESET | clk60:[R] | clk60:[R] | 0.000 | 0.008 | 1.352 |
| 8 | 1.375 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/RESET | clk60:[R] | clk60:[R] | 0.000 | 0.008 | 1.356 |
| 9 | 1.375 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_1_s/RESET | clk60:[R] | clk60:[R] | 0.000 | 0.008 | 1.356 |
| 10 | 1.375 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s/RESET | clk60:[R] | clk60:[R] | 0.000 | 0.004 | 1.360 |
| 11 | 1.375 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_0_s/RESET | clk60:[R] | clk60:[R] | 0.000 | 0.004 | 1.360 |
| 12 | 1.375 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/RESET | clk60:[R] | clk60:[R] | 0.000 | 0.004 | 1.360 |
| 13 | 1.404 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/wbin_2_s0/CLEAR | clk60:[R] | clk60:[R] | 0.000 | 0.004 | 1.347 |
| 14 | 1.408 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_5_s0/CLEAR | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 1.355 |
| 15 | 1.408 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_4_s0/CLEAR | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 1.355 |
| 16 | 1.408 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_6_s0/CLEAR | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 1.355 |
| 17 | 1.408 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rq2_wptr_1_s0/CLEAR | clk60:[R] | clk60:[R] | 0.000 | 0.000 | 1.355 |
| 18 | 1.408 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_4_s0/CLEAR | clk60:[R] | clk60:[R] | 0.000 | 0.004 | 1.351 |
| 19 | 1.408 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_3_s0/CLEAR | clk60:[R] | clk60:[R] | 0.000 | 0.004 | 1.351 |
| 20 | 1.408 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_5_s0/CLEAR | clk60:[R] | clk60:[R] | 0.000 | 0.004 | 1.351 |
| 21 | 1.408 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_1_s0/CLEAR | clk60:[R] | clk60:[R] | 0.000 | 0.004 | 1.351 |
| 22 | 1.408 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_2_s0/CLEAR | clk60:[R] | clk60:[R] | 0.000 | 0.004 | 1.351 |
| 23 | 1.408 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rq2_wptr_3_s0/CLEAR | clk60:[R] | clk60:[R] | 0.000 | 0.004 | 1.351 |
| 24 | 1.408 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rq2_wptr_5_s0/CLEAR | clk60:[R] | clk60:[R] | 0.000 | 0.004 | 1.351 |
| 25 | 1.408 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rq1_wptr_3_s0/CLEAR | clk60:[R] | clk60:[R] | 0.000 | 0.004 | 1.351 |
Minimum Pulse Width Table:
| Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
|---|---|---|---|---|---|---|
| 1 | 1.243 | 2.243 | 1.000 | Low Pulse Width | clk120 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s |
| 2 | 1.243 | 2.243 | 1.000 | Low Pulse Width | clk120 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s |
| 3 | 1.245 | 2.245 | 1.000 | High Pulse Width | clk120 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s |
| 4 | 1.245 | 2.245 | 1.000 | High Pulse Width | clk120 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s |
| 5 | 1.982 | 2.232 | 0.250 | Low Pulse Width | clk120 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_2_s0 |
| 6 | 1.982 | 2.232 | 0.250 | Low Pulse Width | clk120 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_4_s0 |
| 7 | 1.982 | 2.232 | 0.250 | Low Pulse Width | clk120 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_1_s0 |
| 8 | 1.982 | 2.232 | 0.250 | Low Pulse Width | clk120 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_0_s0 |
| 9 | 1.982 | 2.232 | 0.250 | Low Pulse Width | clk120 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_s0 |
| 10 | 1.982 | 2.232 | 0.250 | Low Pulse Width | clk120 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_3_s1 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.695 |
| Data Arrival Time | 10.214 |
| Data Required Time | 10.909 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_15_s0 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 8 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK |
| 3.612 | 0.635 | tC2Q | RR | 1 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 |
| 3.939 | 0.327 | tNET | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I3 |
| 4.401 | 0.461 | tINS | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F |
| 4.924 | 0.524 | tNET | RR | 1 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3 |
| 5.386 | 0.461 | tINS | RR | 11 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F |
| 8.532 | 3.146 | tNET | RR | 1 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1 |
| 9.048 | 0.516 | tINS | RR | 16 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F |
| 10.214 | 1.166 | tNET | RR | 1 | R57C100[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_15_s0/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.282 | 2.949 | tNET | RR | 1 | R57C100[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_15_s0/CLK |
| 10.909 | -0.373 | tSu | 1 | R57C100[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_15_s0 |
Path Statistics:
| Clock Skew | -0.028 |
| Setup Relationship | 8.333 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 1.439, 19.879%; route: 5.164, 71.347%; tC2Q: 0.635, 8.774% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.949, 100.000% |
Path2
Path Summary:
| Slack | 0.695 |
| Data Arrival Time | 10.214 |
| Data Required Time | 10.909 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_4_s0 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 8 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK |
| 3.612 | 0.635 | tC2Q | RR | 1 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 |
| 3.939 | 0.327 | tNET | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I3 |
| 4.401 | 0.461 | tINS | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F |
| 4.924 | 0.524 | tNET | RR | 1 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3 |
| 5.386 | 0.461 | tINS | RR | 11 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F |
| 8.532 | 3.146 | tNET | RR | 1 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1 |
| 9.048 | 0.516 | tINS | RR | 16 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F |
| 10.214 | 1.166 | tNET | RR | 1 | R57C100[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_4_s0/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.282 | 2.949 | tNET | RR | 1 | R57C100[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_4_s0/CLK |
| 10.909 | -0.373 | tSu | 1 | R57C100[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_4_s0 |
Path Statistics:
| Clock Skew | -0.028 |
| Setup Relationship | 8.333 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 1.439, 19.879%; route: 5.164, 71.347%; tC2Q: 0.635, 8.774% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.949, 100.000% |
Path3
Path Summary:
| Slack | 0.695 |
| Data Arrival Time | 10.214 |
| Data Required Time | 10.909 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_11_s0 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 8 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK |
| 3.612 | 0.635 | tC2Q | RR | 1 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 |
| 3.939 | 0.327 | tNET | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I3 |
| 4.401 | 0.461 | tINS | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F |
| 4.924 | 0.524 | tNET | RR | 1 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3 |
| 5.386 | 0.461 | tINS | RR | 11 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F |
| 8.532 | 3.146 | tNET | RR | 1 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1 |
| 9.048 | 0.516 | tINS | RR | 16 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F |
| 10.214 | 1.166 | tNET | RR | 1 | R57C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_11_s0/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.282 | 2.949 | tNET | RR | 1 | R57C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_11_s0/CLK |
| 10.909 | -0.373 | tSu | 1 | R57C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_11_s0 |
Path Statistics:
| Clock Skew | -0.028 |
| Setup Relationship | 8.333 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 1.439, 19.879%; route: 5.164, 71.347%; tC2Q: 0.635, 8.774% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.949, 100.000% |
Path4
Path Summary:
| Slack | 0.704 |
| Data Arrival Time | 10.214 |
| Data Required Time | 10.919 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_3_s0 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 8 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK |
| 3.612 | 0.635 | tC2Q | RR | 1 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 |
| 3.939 | 0.327 | tNET | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I3 |
| 4.401 | 0.461 | tINS | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F |
| 4.924 | 0.524 | tNET | RR | 1 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3 |
| 5.386 | 0.461 | tINS | RR | 11 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F |
| 8.532 | 3.146 | tNET | RR | 1 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1 |
| 9.048 | 0.516 | tINS | RR | 16 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F |
| 10.214 | 1.166 | tNET | RR | 1 | R57C101[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_3_s0/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R57C101[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_3_s0/CLK |
| 10.919 | -0.373 | tSu | 1 | R57C101[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_3_s0 |
Path Statistics:
| Clock Skew | -0.019 |
| Setup Relationship | 8.333 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 1.439, 19.879%; route: 5.164, 71.347%; tC2Q: 0.635, 8.774% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path5
Path Summary:
| Slack | 0.704 |
| Data Arrival Time | 10.214 |
| Data Required Time | 10.919 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_7_s0 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 8 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK |
| 3.612 | 0.635 | tC2Q | RR | 1 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 |
| 3.939 | 0.327 | tNET | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I3 |
| 4.401 | 0.461 | tINS | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F |
| 4.924 | 0.524 | tNET | RR | 1 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3 |
| 5.386 | 0.461 | tINS | RR | 11 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F |
| 8.532 | 3.146 | tNET | RR | 1 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1 |
| 9.048 | 0.516 | tINS | RR | 16 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F |
| 10.214 | 1.166 | tNET | RR | 1 | R57C101[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_7_s0/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R57C101[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_7_s0/CLK |
| 10.919 | -0.373 | tSu | 1 | R57C101[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_7_s0 |
Path Statistics:
| Clock Skew | -0.019 |
| Setup Relationship | 8.333 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 1.439, 19.879%; route: 5.164, 71.347%; tC2Q: 0.635, 8.774% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path6
Path Summary:
| Slack | 0.924 |
| Data Arrival Time | 9.994 |
| Data Required Time | 10.919 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_12_s0 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 8 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK |
| 3.612 | 0.635 | tC2Q | RR | 1 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 |
| 3.939 | 0.327 | tNET | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I3 |
| 4.401 | 0.461 | tINS | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F |
| 4.924 | 0.524 | tNET | RR | 1 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3 |
| 5.386 | 0.461 | tINS | RR | 11 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F |
| 8.532 | 3.146 | tNET | RR | 1 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1 |
| 9.048 | 0.516 | tINS | RR | 16 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F |
| 9.994 | 0.946 | tNET | RR | 1 | R57C99[3][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_12_s0/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R57C99[3][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_12_s0/CLK |
| 10.919 | -0.373 | tSu | 1 | R57C99[3][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_12_s0 |
Path Statistics:
| Clock Skew | -0.019 |
| Setup Relationship | 8.333 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 1.439, 20.502%; route: 4.944, 70.449%; tC2Q: 0.635, 9.049% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path7
Path Summary:
| Slack | 1.012 |
| Data Arrival Time | 9.907 |
| Data Required Time | 10.919 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_0_s0 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 8 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK |
| 3.612 | 0.635 | tC2Q | RR | 1 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 |
| 3.939 | 0.327 | tNET | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I3 |
| 4.401 | 0.461 | tINS | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F |
| 4.924 | 0.524 | tNET | RR | 1 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3 |
| 5.386 | 0.461 | tINS | RR | 11 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F |
| 8.532 | 3.146 | tNET | RR | 1 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1 |
| 9.048 | 0.516 | tINS | RR | 16 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F |
| 9.907 | 0.859 | tNET | RR | 1 | R58C99[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_0_s0/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R58C99[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_0_s0/CLK |
| 10.919 | -0.373 | tSu | 1 | R58C99[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_0_s0 |
Path Statistics:
| Clock Skew | -0.019 |
| Setup Relationship | 8.333 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 1.439, 20.761%; route: 4.856, 70.076%; tC2Q: 0.635, 9.163% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path8
Path Summary:
| Slack | 1.012 |
| Data Arrival Time | 9.907 |
| Data Required Time | 10.919 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_8_s0 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 8 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK |
| 3.612 | 0.635 | tC2Q | RR | 1 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 |
| 3.939 | 0.327 | tNET | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I3 |
| 4.401 | 0.461 | tINS | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F |
| 4.924 | 0.524 | tNET | RR | 1 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3 |
| 5.386 | 0.461 | tINS | RR | 11 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F |
| 8.532 | 3.146 | tNET | RR | 1 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1 |
| 9.048 | 0.516 | tINS | RR | 16 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F |
| 9.907 | 0.859 | tNET | RR | 1 | R58C99[2][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_8_s0/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R58C99[2][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_8_s0/CLK |
| 10.919 | -0.373 | tSu | 1 | R58C99[2][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_8_s0 |
Path Statistics:
| Clock Skew | -0.019 |
| Setup Relationship | 8.333 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 1.439, 20.761%; route: 4.856, 70.076%; tC2Q: 0.635, 9.163% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path9
Path Summary:
| Slack | 1.021 |
| Data Arrival Time | 9.907 |
| Data Required Time | 10.928 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_13_s0 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 8 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK |
| 3.612 | 0.635 | tC2Q | RR | 1 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 |
| 3.939 | 0.327 | tNET | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I3 |
| 4.401 | 0.461 | tINS | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F |
| 4.924 | 0.524 | tNET | RR | 1 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3 |
| 5.386 | 0.461 | tINS | RR | 11 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F |
| 8.532 | 3.146 | tNET | RR | 1 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1 |
| 9.048 | 0.516 | tINS | RR | 16 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F |
| 9.907 | 0.859 | tNET | RR | 1 | R58C98[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_13_s0/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.300 | 2.967 | tNET | RR | 1 | R58C98[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_13_s0/CLK |
| 10.928 | -0.373 | tSu | 1 | R58C98[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_13_s0 |
Path Statistics:
| Clock Skew | -0.009 |
| Setup Relationship | 8.333 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 1.439, 20.761%; route: 4.856, 70.076%; tC2Q: 0.635, 9.163% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.967, 100.000% |
Path10
Path Summary:
| Slack | 1.081 |
| Data Arrival Time | 9.847 |
| Data Required Time | 10.928 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_1_s0 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 8 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK |
| 3.612 | 0.635 | tC2Q | RR | 1 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 |
| 3.939 | 0.327 | tNET | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I3 |
| 4.401 | 0.461 | tINS | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F |
| 4.924 | 0.524 | tNET | RR | 1 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3 |
| 5.386 | 0.461 | tINS | RR | 11 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F |
| 8.532 | 3.146 | tNET | RR | 1 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1 |
| 9.048 | 0.516 | tINS | RR | 16 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F |
| 9.847 | 0.799 | tNET | RR | 1 | R57C98[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_1_s0/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.300 | 2.967 | tNET | RR | 1 | R57C98[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_1_s0/CLK |
| 10.928 | -0.373 | tSu | 1 | R57C98[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_1_s0 |
Path Statistics:
| Clock Skew | -0.009 |
| Setup Relationship | 8.333 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 1.439, 20.943%; route: 4.796, 69.814%; tC2Q: 0.635, 9.243% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.967, 100.000% |
Path11
Path Summary:
| Slack | 1.081 |
| Data Arrival Time | 9.847 |
| Data Required Time | 10.928 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_5_s0 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 8 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK |
| 3.612 | 0.635 | tC2Q | RR | 1 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 |
| 3.939 | 0.327 | tNET | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I3 |
| 4.401 | 0.461 | tINS | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F |
| 4.924 | 0.524 | tNET | RR | 1 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3 |
| 5.386 | 0.461 | tINS | RR | 11 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F |
| 8.532 | 3.146 | tNET | RR | 1 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1 |
| 9.048 | 0.516 | tINS | RR | 16 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F |
| 9.847 | 0.799 | tNET | RR | 1 | R57C98[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_5_s0/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.300 | 2.967 | tNET | RR | 1 | R57C98[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_5_s0/CLK |
| 10.928 | -0.373 | tSu | 1 | R57C98[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_5_s0 |
Path Statistics:
| Clock Skew | -0.009 |
| Setup Relationship | 8.333 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 1.439, 20.943%; route: 4.796, 69.814%; tC2Q: 0.635, 9.243% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.967, 100.000% |
Path12
Path Summary:
| Slack | 1.081 |
| Data Arrival Time | 9.847 |
| Data Required Time | 10.928 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_9_s0 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 8 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK |
| 3.612 | 0.635 | tC2Q | RR | 1 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 |
| 3.939 | 0.327 | tNET | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I3 |
| 4.401 | 0.461 | tINS | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F |
| 4.924 | 0.524 | tNET | RR | 1 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3 |
| 5.386 | 0.461 | tINS | RR | 11 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F |
| 8.532 | 3.146 | tNET | RR | 1 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1 |
| 9.048 | 0.516 | tINS | RR | 16 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F |
| 9.847 | 0.799 | tNET | RR | 1 | R57C98[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_9_s0/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.300 | 2.967 | tNET | RR | 1 | R57C98[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_9_s0/CLK |
| 10.928 | -0.373 | tSu | 1 | R57C98[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_9_s0 |
Path Statistics:
| Clock Skew | -0.009 |
| Setup Relationship | 8.333 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 1.439, 20.943%; route: 4.796, 69.814%; tC2Q: 0.635, 9.243% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.967, 100.000% |
Path13
Path Summary:
| Slack | 1.207 |
| Data Arrival Time | 9.712 |
| Data Required Time | 10.919 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_14_s0 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 8 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK |
| 3.612 | 0.635 | tC2Q | RR | 1 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 |
| 3.939 | 0.327 | tNET | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I3 |
| 4.401 | 0.461 | tINS | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F |
| 4.924 | 0.524 | tNET | RR | 1 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3 |
| 5.386 | 0.461 | tINS | RR | 11 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F |
| 8.532 | 3.146 | tNET | RR | 1 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1 |
| 9.048 | 0.516 | tINS | RR | 16 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F |
| 9.712 | 0.664 | tNET | RR | 1 | R58C97[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_14_s0/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R58C97[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_14_s0/CLK |
| 10.919 | -0.373 | tSu | 1 | R58C97[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_14_s0 |
Path Statistics:
| Clock Skew | -0.019 |
| Setup Relationship | 8.333 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 1.439, 21.362%; route: 4.661, 69.209%; tC2Q: 0.635, 9.428% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path14
Path Summary:
| Slack | 1.264 |
| Data Arrival Time | 9.654 |
| Data Required Time | 10.919 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_2_s0 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 8 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK |
| 3.612 | 0.635 | tC2Q | RR | 1 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 |
| 3.939 | 0.327 | tNET | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I3 |
| 4.401 | 0.461 | tINS | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F |
| 4.924 | 0.524 | tNET | RR | 1 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3 |
| 5.386 | 0.461 | tINS | RR | 11 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F |
| 8.532 | 3.146 | tNET | RR | 1 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1 |
| 9.048 | 0.516 | tINS | RR | 16 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F |
| 9.654 | 0.606 | tNET | RR | 1 | R57C97[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_2_s0/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R57C97[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_2_s0/CLK |
| 10.919 | -0.373 | tSu | 1 | R57C97[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_2_s0 |
Path Statistics:
| Clock Skew | -0.019 |
| Setup Relationship | 8.333 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 1.439, 21.546%; route: 4.604, 68.944%; tC2Q: 0.635, 9.510% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path15
Path Summary:
| Slack | 1.264 |
| Data Arrival Time | 9.654 |
| Data Required Time | 10.919 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_6_s0 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 8 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK |
| 3.612 | 0.635 | tC2Q | RR | 1 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 |
| 3.939 | 0.327 | tNET | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I3 |
| 4.401 | 0.461 | tINS | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F |
| 4.924 | 0.524 | tNET | RR | 1 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3 |
| 5.386 | 0.461 | tINS | RR | 11 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F |
| 8.532 | 3.146 | tNET | RR | 1 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1 |
| 9.048 | 0.516 | tINS | RR | 16 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F |
| 9.654 | 0.606 | tNET | RR | 1 | R57C97[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_6_s0/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R57C97[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_6_s0/CLK |
| 10.919 | -0.373 | tSu | 1 | R57C97[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_6_s0 |
Path Statistics:
| Clock Skew | -0.019 |
| Setup Relationship | 8.333 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 1.439, 21.546%; route: 4.604, 68.944%; tC2Q: 0.635, 9.510% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path16
Path Summary:
| Slack | 1.351 |
| Data Arrival Time | 9.568 |
| Data Required Time | 10.919 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_10_s0 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 8 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK |
| 3.612 | 0.635 | tC2Q | RR | 1 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 |
| 3.939 | 0.327 | tNET | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I3 |
| 4.401 | 0.461 | tINS | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F |
| 4.924 | 0.524 | tNET | RR | 1 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3 |
| 5.386 | 0.461 | tINS | RR | 11 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F |
| 8.532 | 3.146 | tNET | RR | 1 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/I1 |
| 9.048 | 0.516 | tINS | RR | 16 | R55C93[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n23_s1/F |
| 9.568 | 0.520 | tNET | RR | 1 | R55C97[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_10_s0/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R55C97[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_10_s0/CLK |
| 10.919 | -0.373 | tSu | 1 | R55C97[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/II_10_s0 |
Path Statistics:
| Clock Skew | -0.019 |
| Setup Relationship | 8.333 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 1.439, 21.828%; route: 4.517, 68.538%; tC2Q: 0.635, 9.634% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path17
Path Summary:
| Slack | 1.562 |
| Data Arrival Time | 9.666 |
| Data Required Time | 11.227 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides16 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/dru_locked_s2 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 16 | IOR63[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides16/PCLK |
| 3.612 | 0.635 | tC2Q | RF | 5 | IOR63[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides16/Q4 |
| 5.973 | 2.361 | tNET | FF | 1 | R57C101[3][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/sync_bit_3_s5/I2 |
| 6.494 | 0.521 | tINS | FR | 1 | R57C101[3][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/sync_bit_3_s5/F |
| 6.822 | 0.327 | tNET | RR | 1 | R59C101[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/sync_bit_3_s3/I0 |
| 7.348 | 0.526 | tINS | RR | 1 | R59C101[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/sync_bit_3_s3/F |
| 7.351 | 0.003 | tNET | RR | 1 | R59C101[3][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/sync_bit_3_s0/I3 |
| 7.848 | 0.498 | tINS | RR | 3 | R59C101[3][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/sync_bit_3_s0/F |
| 8.718 | 0.870 | tNET | RR | 1 | R57C95[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s1/I2 |
| 9.234 | 0.516 | tINS | RR | 1 | R57C95[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s1/F |
| 9.403 | 0.169 | tNET | RR | 1 | R55C95[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n352_s3/I0 |
| 9.666 | 0.262 | tINS | RR | 1 | R55C95[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n352_s3/F |
| 9.666 | 0.000 | tNET | RR | 1 | R55C95[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/dru_locked_s2/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R55C95[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/dru_locked_s2/CLK |
| 11.227 | -0.064 | tSu | 1 | R55C95[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/dru_locked_s2 |
Path Statistics:
| Clock Skew | -0.019 |
| Setup Relationship | 8.333 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 2.324, 34.741%; route: 3.730, 55.765%; tC2Q: 0.635, 9.494% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path18
Path Summary:
| Slack | 2.071 |
| Data Arrival Time | 9.231 |
| Data Required Time | 11.301 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides16 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s0 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 16 | IOR63[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides16/PCLK |
| 3.612 | 0.635 | tC2Q | RR | 5 | IOR63[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides16/Q6 |
| 6.091 | 2.479 | tNET | RR | 1 | R55C98[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n300_s43/I2 |
| 6.617 | 0.526 | tINS | RR | 1 | R55C98[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n300_s43/F |
| 6.921 | 0.304 | tNET | RR | 1 | R57C98[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n300_s36/I0 |
| 7.183 | 0.262 | tINS | RR | 1 | R57C98[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n300_s36/F |
| 7.321 | 0.137 | tNET | RR | 1 | R57C98[3][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n300_s30/I2 |
| 7.736 | 0.415 | tINS | RR | 5 | R57C98[3][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n300_s30/F |
| 8.508 | 0.772 | tNET | RR | 1 | R58C95[3][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s4/I1 |
| 9.006 | 0.498 | tINS | RR | 1 | R58C95[3][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s4/F |
| 9.006 | 0.000 | tNET | RR | 1 | R58C95[3][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s1/I1 |
| 9.142 | 0.136 | tINS | RR | 1 | R58C95[3][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s1/O |
| 9.142 | 0.000 | tNET | RR | 1 | R58C95[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s0/I0 |
| 9.228 | 0.086 | tINS | RR | 1 | R58C95[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s0/O |
| 9.231 | 0.003 | tNET | RR | 1 | R58C95[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R58C95[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s0/CLK |
| 11.301 | 0.010 | tSu | 1 | R58C95[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s0 |
Path Statistics:
| Clock Skew | -0.019 |
| Setup Relationship | 8.333 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 1.924, 30.762%; route: 3.695, 59.085%; tC2Q: 0.635, 10.154% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path19
Path Summary:
| Slack | 2.143 |
| Data Arrival Time | 9.161 |
| Data Required Time | 11.304 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides16 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s0 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 16 | IOR63[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides16/PCLK |
| 3.517 | 0.540 | tC2Q | RR | 5 | IOR63[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides16/Q9 |
| 6.523 | 3.006 | tNET | RR | 1 | R55C97[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n300_s45/I3 |
| 6.786 | 0.262 | tINS | RR | 1 | R55C97[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n300_s45/F |
| 7.089 | 0.304 | tNET | RR | 1 | R57C97[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n300_s39/I0 |
| 7.352 | 0.262 | tINS | RR | 1 | R57C97[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n300_s39/F |
| 7.489 | 0.137 | tNET | RR | 1 | R57C97[3][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n300_s31/I2 |
| 7.904 | 0.415 | tINS | RR | 5 | R57C97[3][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n300_s31/F |
| 8.104 | 0.200 | tNET | RR | 1 | R57C95[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n299_s28/I3 |
| 8.566 | 0.461 | tINS | RR | 1 | R57C95[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n299_s28/F |
| 8.568 | 0.003 | tNET | RR | 1 | R57C95[3][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s4/I1 |
| 8.858 | 0.290 | tINS | RF | 1 | R57C95[3][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s4/F |
| 8.858 | 0.000 | tNET | FF | 1 | R57C95[3][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s1/I1 |
| 9.054 | 0.196 | tINS | FF | 1 | R57C95[3][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s1/O |
| 9.054 | 0.000 | tNET | FF | 1 | R57C95[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s0/I0 |
| 9.156 | 0.101 | tINS | FF | 1 | R57C95[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s0/O |
| 9.161 | 0.005 | tNET | FF | 1 | R57C95[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R57C95[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s0/CLK |
| 11.304 | 0.012 | tSu | 1 | R57C95[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s0 |
Path Statistics:
| Clock Skew | -0.019 |
| Setup Relationship | 8.333 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 1.989, 32.161%; route: 3.655, 59.107%; tC2Q: 0.540, 8.733% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path20
Path Summary:
| Slack | 2.243 |
| Data Arrival Time | 8.984 |
| Data Required Time | 11.227 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/eop_dect_0_s0 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 8 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK |
| 3.612 | 0.635 | tC2Q | RR | 1 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 |
| 3.939 | 0.327 | tNET | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I3 |
| 4.401 | 0.461 | tINS | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F |
| 4.924 | 0.524 | tNET | RR | 1 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3 |
| 5.386 | 0.461 | tINS | RR | 11 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F |
| 8.984 | 3.599 | tNET | RR | 1 | R54C93[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/eop_dect_0_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R54C93[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/eop_dect_0_s0/CLK |
| 11.227 | -0.064 | tSu | 1 | R54C93[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/eop_dect_0_s0 |
Path Statistics:
| Clock Skew | -0.019 |
| Setup Relationship | 8.333 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 0.922, 15.356%; route: 4.450, 74.074%; tC2Q: 0.635, 10.570% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path21
Path Summary:
| Slack | 2.304 |
| Data Arrival Time | 8.923 |
| Data Required Time | 11.227 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/rx_en_s2 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 8 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK |
| 3.612 | 0.635 | tC2Q | RR | 1 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 |
| 3.939 | 0.327 | tNET | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I3 |
| 4.401 | 0.461 | tINS | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F |
| 4.924 | 0.524 | tNET | RR | 1 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3 |
| 5.386 | 0.461 | tINS | RR | 11 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F |
| 8.397 | 3.011 | tNET | RR | 1 | R55C93[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n239_s4/I2 |
| 8.923 | 0.526 | tINS | RR | 1 | R55C93[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n239_s4/F |
| 8.923 | 0.000 | tNET | RR | 1 | R55C93[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/rx_en_s2/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R55C93[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/rx_en_s2/CLK |
| 11.227 | -0.064 | tSu | 1 | R55C93[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/rx_en_s2 |
Path Statistics:
| Clock Skew | -0.019 |
| Setup Relationship | 8.333 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 1.449, 24.364%; route: 3.862, 64.957%; tC2Q: 0.635, 10.679% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path22
Path Summary:
| Slack | 2.304 |
| Data Arrival Time | 8.923 |
| Data Required Time | 11.227 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/eop_dect_2_s0 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 8 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK |
| 3.612 | 0.635 | tC2Q | RR | 1 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 |
| 3.939 | 0.327 | tNET | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I3 |
| 4.401 | 0.461 | tINS | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F |
| 4.924 | 0.524 | tNET | RR | 1 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3 |
| 5.386 | 0.461 | tINS | RR | 11 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F |
| 8.397 | 3.011 | tNET | RR | 1 | R55C93[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n216_s1/I1 |
| 8.923 | 0.526 | tINS | RR | 1 | R55C93[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n216_s1/F |
| 8.923 | 0.000 | tNET | RR | 1 | R55C93[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/eop_dect_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R55C93[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/eop_dect_2_s0/CLK |
| 11.227 | -0.064 | tSu | 1 | R55C93[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/eop_dect_2_s0 |
Path Statistics:
| Clock Skew | -0.019 |
| Setup Relationship | 8.333 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 1.449, 24.364%; route: 3.862, 64.957%; tC2Q: 0.635, 10.679% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path23
Path Summary:
| Slack | 2.304 |
| Data Arrival Time | 8.923 |
| Data Required Time | 11.227 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/eop_dect_1_s0 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 8 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK |
| 3.612 | 0.635 | tC2Q | RR | 1 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 |
| 3.939 | 0.327 | tNET | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I3 |
| 4.401 | 0.461 | tINS | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F |
| 4.924 | 0.524 | tNET | RR | 1 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3 |
| 5.386 | 0.461 | tINS | RR | 11 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F |
| 8.397 | 3.011 | tNET | RR | 1 | R55C93[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n217_s2/I0 |
| 8.923 | 0.526 | tINS | RR | 1 | R55C93[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n217_s2/F |
| 8.923 | 0.000 | tNET | RR | 1 | R55C93[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/eop_dect_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R55C93[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/eop_dect_1_s0/CLK |
| 11.227 | -0.064 | tSu | 1 | R55C93[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/eop_dect_1_s0 |
Path Statistics:
| Clock Skew | -0.019 |
| Setup Relationship | 8.333 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 1.449, 24.364%; route: 3.862, 64.957%; tC2Q: 0.635, 10.679% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path24
Path Summary:
| Slack | 2.304 |
| Data Arrival Time | 8.923 |
| Data Required Time | 11.227 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/eop_dect_3_s0 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.977 | 2.977 | tNET | RR | 8 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/PCLK |
| 3.612 | 0.635 | tC2Q | RR | 1 | IOR70[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/dn_ref_ides8/Q0 |
| 3.939 | 0.327 | tNET | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/I3 |
| 4.401 | 0.461 | tINS | RR | 1 | R70C146[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s5/F |
| 4.924 | 0.524 | tNET | RR | 1 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/I3 |
| 5.386 | 0.461 | tINS | RR | 11 | R57C146[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n350_s1/F |
| 8.397 | 3.011 | tNET | RR | 1 | R55C93[2][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n215_s2/I0 |
| 8.923 | 0.526 | tINS | RR | 1 | R55C93[2][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n215_s2/F |
| 8.923 | 0.000 | tNET | RR | 1 | R55C93[2][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/eop_dect_3_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R55C93[2][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/eop_dect_3_s0/CLK |
| 11.227 | -0.064 | tSu | 1 | R55C93[2][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/eop_dect_3_s0 |
Path Statistics:
| Clock Skew | -0.019 |
| Setup Relationship | 8.333 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.977, 100.000% |
| Arrival Data Path Delay | cell: 1.449, 24.364%; route: 3.862, 64.957%; tC2Q: 0.635, 10.679% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path25
Path Summary:
| Slack | 2.312 |
| Data Arrival Time | 8.915 |
| Data Required Time | 11.227 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0 |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.967 | 2.967 | tNET | RR | 1 | R63C98[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/CLK |
| 3.350 | 0.382 | tC2Q | RR | 4 | R63C98[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/Q |
| 3.920 | 0.570 | tNET | RR | 1 | R62C101[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n28_s0/I0 |
| 4.381 | 0.461 | tINS | RR | 3 | R62C101[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n28_s0/F |
| 4.569 | 0.188 | tNET | RR | 1 | R62C100[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_3_s4/I3 |
| 5.030 | 0.461 | tINS | RR | 6 | R62C100[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_3_s4/F |
| 5.415 | 0.385 | tNET | RR | 1 | R63C101[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_4_s3/I1 |
| 5.876 | 0.461 | tINS | RR | 2 | R63C101[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_4_s3/F |
| 6.016 | 0.140 | tNET | RR | 1 | R63C101[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rgraynext_2_s1/I2 |
| 6.279 | 0.262 | tINS | RR | 2 | R63C101[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rgraynext_2_s1/F |
| 6.464 | 0.185 | tNET | RR | 2 | R63C100[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n163_s0/I0 |
| 7.020 | 0.556 | tINS | RF | 1 | R63C100[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n163_s0/COUT |
| 7.020 | 0.000 | tNET | FF | 2 | R63C100[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n164_s0/CIN |
| 7.070 | 0.050 | tINS | FR | 1 | R63C100[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n164_s0/COUT |
| 7.070 | 0.000 | tNET | RR | 2 | R63C100[2][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n165_s0/CIN |
| 7.120 | 0.050 | tINS | RF | 2 | R63C100[2][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n165_s0/COUT |
| 7.561 | 0.441 | tNET | FF | 1 | R63C98[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/w_empty_s0/I0 |
| 8.087 | 0.526 | tINS | FR | 2 | R63C98[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/w_empty_s0/F |
| 8.915 | 0.827 | tNET | RR | 1 | R62C101[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R62C101[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0/CLK |
| 11.227 | -0.064 | tSu | 1 | R62C101[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0 |
Path Statistics:
| Clock Skew | -0.009 |
| Setup Relationship | 8.333 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.967, 100.000% |
| Arrival Data Path Delay | cell: 2.829, 47.562%; route: 2.736, 46.007%; tC2Q: 0.382, 6.431% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.141 |
| Data Arrival Time | 0.855 |
| Data Required Time | 0.714 |
| From | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_1_s0 |
| To | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R55C47[1][A] | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_1_s0/CLK |
| 0.818 | 0.141 | tC2Q | RF | 2 | R55C47[1][A] | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_1_s0/Q |
| 0.855 | 0.037 | tNET | FF | 1 | BSRAM_R56[10] | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/DI[1] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | BSRAM_R56[10] | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/CLKA |
| 0.714 | 0.037 | tHld | 1 | BSRAM_R56[10] | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.037, 20.787%; tC2Q: 0.141, 79.213% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
Path2
Path Summary:
| Slack | 0.141 |
| Data Arrival Time | 1.270 |
| Data Required Time | 1.128 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_d0_0_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/oser16txd |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 1.030 | 1.030 | tNET | RR | 1 | R66C146[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_d0_0_s0/CLK |
| 1.174 | 0.144 | tC2Q | RR | 2 | R66C146[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_d0_0_s0/Q |
| 1.270 | 0.096 | tNET | RR | 1 | IOR66[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/oser16txd/D0 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 1.033 | 1.033 | tNET | RR | 1 | IOR66[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/oser16txd/PCLK |
| 1.128 | 0.095 | tHld | 1 | IOR66[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/oser16txd |
Path Statistics:
| Clock Skew | 0.003 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.030, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.096, 40.000%; tC2Q: 0.144, 60.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.033, 100.000% |
Path3
Path Summary:
| Slack | 0.154 |
| Data Arrival Time | 1.270 |
| Data Required Time | 1.116 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_d0_0_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/oser16txd |
| Launch Clk | clk120:[R] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 1.030 | 1.030 | tNET | RR | 1 | R66C146[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_d0_0_s0/CLK |
| 1.174 | 0.144 | tC2Q | RR | 2 | R66C146[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_d0_0_s0/Q |
| 1.270 | 0.096 | tNET | RR | 1 | IOR66[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/oser16txd/D1 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk120 | ||||
| 0.000 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 1.033 | 1.033 | tNET | RR | 1 | IOR66[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/oser16txd/PCLK |
| 1.116 | 0.083 | tHld | 1 | IOR66[A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/oser16txd |
Path Statistics:
| Clock Skew | 0.003 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.030, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.096, 40.000%; tC2Q: 0.144, 60.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.033, 100.000% |
Path4
Path Summary:
| Slack | 0.202 |
| Data Arrival Time | 0.916 |
| Data Required Time | 0.714 |
| From | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_0_s0 |
| To | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R55C47[0][A] | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_0_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 2 | R55C47[0][A] | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_0_s0/Q |
| 0.916 | 0.095 | tNET | RR | 1 | BSRAM_R56[10] | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/DI[0] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | BSRAM_R56[10] | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/CLKA |
| 0.714 | 0.037 | tHld | 1 | BSRAM_R56[10] | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.095, 39.749%; tC2Q: 0.144, 60.251% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
Path5
Path Summary:
| Slack | 0.208 |
| Data Arrival Time | 0.922 |
| Data Required Time | 0.714 |
| From | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_2_s0 |
| To | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R55C47[0][B] | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_2_s0/CLK |
| 0.818 | 0.141 | tC2Q | RF | 2 | R55C47[0][B] | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_2_s0/Q |
| 0.922 | 0.104 | tNET | FF | 1 | BSRAM_R56[10] | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/DI[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | BSRAM_R56[10] | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/CLKA |
| 0.714 | 0.037 | tHld | 1 | BSRAM_R56[10] | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.104, 42.449%; tC2Q: 0.141, 57.551% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
Path6
Path Summary:
| Slack | 0.244 |
| Data Arrival Time | 0.958 |
| Data Required Time | 0.714 |
| From | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_3_s0 |
| To | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R55C47[1][B] | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_3_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 2 | R55C47[1][B] | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_3_s0/Q |
| 0.958 | 0.137 | tNET | RR | 1 | BSRAM_R56[10] | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/DI[3] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | BSRAM_R56[10] | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/CLKA |
| 0.714 | 0.037 | tHld | 1 | BSRAM_R56[10] | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.137, 48.754%; tC2Q: 0.144, 51.246% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
Path7
Path Summary:
| Slack | 0.248 |
| Data Arrival Time | 0.956 |
| Data Required Time | 0.708 |
| From | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_next_7_s0 |
| To | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.669 | 0.669 | tNET | RR | 1 | R55C61[2][B] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_next_7_s0/CLK |
| 0.813 | 0.144 | tC2Q | RR | 2 | R55C61[2][B] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_next_7_s0/Q |
| 0.956 | 0.143 | tNET | RR | 1 | BSRAM_R56[13][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/ADB[9] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | BSRAM_R56[13][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/CLKB |
| 0.708 | 0.035 | tHld | 1 | BSRAM_R56[13][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.669, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.143, 49.826%; tC2Q: 0.144, 50.174% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
Path8
Path Summary:
| Slack | 0.251 |
| Data Arrival Time | 0.961 |
| Data Required Time | 0.710 |
| From | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_6_s0 |
| To | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_1_s |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | R55C52[1][A] | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_6_s0/CLK |
| 0.817 | 0.144 | tC2Q | RR | 2 | R55C52[1][A] | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_6_s0/Q |
| 0.961 | 0.144 | tNET | RR | 1 | BSRAM_R56[11][A] | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_1_s/DI[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | BSRAM_R56[11][A] | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_1_s/CLKA |
| 0.710 | 0.037 | tHld | 1 | BSRAM_R56[11][A] | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_1_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.144, 50.000%; tC2Q: 0.144, 50.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
Path9
Path Summary:
| Slack | 0.253 |
| Data Arrival Time | 0.965 |
| Data Required Time | 0.712 |
| From | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_next_6_s0 |
| To | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R69C76[2][A] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_next_6_s0/CLK |
| 0.818 | 0.141 | tC2Q | RF | 2 | R69C76[2][A] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_next_6_s0/Q |
| 0.965 | 0.147 | tNET | FF | 1 | BSRAM_R56[16] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/ADB[8] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | BSRAM_R56[16] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/CLKB |
| 0.712 | 0.035 | tHld | 1 | BSRAM_R56[16] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.147, 51.042%; tC2Q: 0.141, 48.958% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
Path10
Path Summary:
| Slack | 0.254 |
| Data Arrival Time | 0.971 |
| Data Required Time | 0.718 |
| From | usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/Q_1_s0 |
| To | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.669 | 0.669 | tNET | RR | 1 | R68C72[1][B] | usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/Q_1_s0/CLK |
| 0.810 | 0.141 | tC2Q | RF | 2 | R68C72[1][B] | usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/Q_1_s0/Q |
| 0.971 | 0.161 | tNET | FF | 1 | BSRAM_R56[16] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/DI[1] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.681 | 0.681 | tNET | RR | 1 | BSRAM_R56[16] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/CLKA |
| 0.718 | 0.037 | tHld | 1 | BSRAM_R56[16] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
Path Statistics:
| Clock Skew | 0.012 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.669, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.161, 53.311%; tC2Q: 0.141, 46.689% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.681, 100.000% |
Path11
Path Summary:
| Slack | 0.256 |
| Data Arrival Time | 0.962 |
| Data Required Time | 0.706 |
| From | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/wp_6_s0 |
| To | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.669 | 0.669 | tNET | RR | 1 | R54C65[1][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/wp_6_s0/CLK |
| 0.813 | 0.144 | tC2Q | RR | 10 | R54C65[1][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/wp_6_s0/Q |
| 0.962 | 0.149 | tNET | RR | 1 | BSRAM_R56[14] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s/ADA[8] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.669 | 0.669 | tNET | RR | 1 | BSRAM_R56[14] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s/CLKA |
| 0.706 | 0.037 | tHld | 1 | BSRAM_R56[14] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.669, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.149, 50.853%; tC2Q: 0.144, 49.147% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.669, 100.000% |
Path12
Path Summary:
| Slack | 0.263 |
| Data Arrival Time | 0.973 |
| Data Required Time | 0.710 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbin_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | R60C99[2][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbin_1_s0/CLK |
| 0.817 | 0.144 | tC2Q | RR | 5 | R60C99[2][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbin_1_s0/Q |
| 0.973 | 0.156 | tNET | RR | 1 | BSRAM_R56[21][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/ADA[4] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | BSRAM_R56[21][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/CLKA |
| 0.710 | 0.037 | tHld | 1 | BSRAM_R56[21][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.156, 52.000%; tC2Q: 0.144, 48.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
Path13
Path Summary:
| Slack | 0.263 |
| Data Arrival Time | 0.975 |
| Data Required Time | 0.712 |
| From | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_next_0_s0 |
| To | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | R59C77[0][A] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_next_0_s0/CLK |
| 0.814 | 0.141 | tC2Q | RF | 2 | R59C77[0][A] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_next_0_s0/Q |
| 0.975 | 0.161 | tNET | FF | 1 | BSRAM_R56[16] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/ADB[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | BSRAM_R56[16] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/CLKB |
| 0.712 | 0.035 | tHld | 1 | BSRAM_R56[16] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.161, 53.311%; tC2Q: 0.141, 46.689% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
Path14
Path Summary:
| Slack | 0.269 |
| Data Arrival Time | 0.973 |
| Data Required Time | 0.704 |
| From | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_next_0_s0 |
| To | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | R55C64[2][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_next_0_s0/CLK |
| 0.817 | 0.144 | tC2Q | RR | 2 | R55C64[2][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_next_0_s0/Q |
| 0.973 | 0.156 | tNET | RR | 1 | BSRAM_R56[15][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/ADB[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.669 | 0.669 | tNET | RR | 1 | BSRAM_R56[15][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKB |
| 0.704 | 0.035 | tHld | 1 | BSRAM_R56[15][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.156, 52.000%; tC2Q: 0.144, 48.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.669, 100.000% |
Path15
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 0.895 |
| Data Required Time | 0.620 |
| From | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wq1_rptr_2_s0 |
| To | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wq2_rptr_2_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | R41C60[1][B] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wq1_rptr_2_s0/CLK |
| 0.817 | 0.144 | tC2Q | RR | 1 | R41C60[1][B] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wq1_rptr_2_s0/Q |
| 0.895 | 0.078 | tNET | RR | 1 | R41C60[0][B] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wq2_rptr_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | R41C60[0][B] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wq2_rptr_2_s0/CLK |
| 0.620 | -0.053 | tHld | 1 | R41C60[0][B] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wq2_rptr_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
Path16
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 0.891 |
| Data Required Time | 0.616 |
| From | usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/rptr_3_s0 |
| To | usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/wq1_rptr_3_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.669 | 0.669 | tNET | RR | 1 | R60C61[2][B] | usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/rptr_3_s0/CLK |
| 0.813 | 0.144 | tC2Q | RR | 1 | R60C61[2][B] | usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/rptr_3_s0/Q |
| 0.891 | 0.078 | tNET | RR | 1 | R60C61[0][B] | usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/wq1_rptr_3_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.669 | 0.669 | tNET | RR | 1 | R60C61[0][B] | usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/wq1_rptr_3_s0/CLK |
| 0.616 | -0.053 | tHld | 1 | R60C61[0][B] | usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/wq1_rptr_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.669, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.669, 100.000% |
Path17
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 0.891 |
| Data Required Time | 0.616 |
| From | usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/rptr_4_s0 |
| To | usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/wq1_rptr_4_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.669 | 0.669 | tNET | RR | 1 | R59C61[3][A] | usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/rptr_4_s0/CLK |
| 0.813 | 0.144 | tC2Q | RR | 1 | R59C61[3][A] | usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/rptr_4_s0/Q |
| 0.891 | 0.078 | tNET | RR | 1 | R59C61[0][B] | usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/wq1_rptr_4_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.669 | 0.669 | tNET | RR | 1 | R59C61[0][B] | usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/wq1_rptr_4_s0/CLK |
| 0.616 | -0.053 | tHld | 1 | R59C61[0][B] | usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/wq1_rptr_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.669, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.669, 100.000% |
Path18
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 0.977 |
| Data Required Time | 0.702 |
| From | u_usb_uart_config/test_tx_count_5_s1 |
| To | u_usb_uart_config/test_tx_count_5_s1 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R44C80[1][A] | u_usb_uart_config/test_tx_count_5_s1/CLK |
| 0.818 | 0.141 | tC2Q | RF | 2 | R44C80[1][A] | u_usb_uart_config/test_tx_count_5_s1/Q |
| 0.824 | 0.006 | tNET | FF | 1 | R44C80[1][A] | u_usb_uart_config/n1839_s2/I2 |
| 0.977 | 0.153 | tINS | FF | 1 | R44C80[1][A] | u_usb_uart_config/n1839_s2/F |
| 0.977 | 0.000 | tNET | FF | 1 | R44C80[1][A] | u_usb_uart_config/test_tx_count_5_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R44C80[1][A] | u_usb_uart_config/test_tx_count_5_s1/CLK |
| 0.702 | 0.025 | tHld | 1 | R44C80[1][A] | u_usb_uart_config/test_tx_count_5_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
Path19
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 0.973 |
| Data Required Time | 0.698 |
| From | u_usb_uart_config/test_rd_addr_7_s1 |
| To | u_usb_uart_config/test_rd_addr_7_s1 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | R49C79[0][A] | u_usb_uart_config/test_rd_addr_7_s1/CLK |
| 0.814 | 0.141 | tC2Q | RF | 7 | R49C79[0][A] | u_usb_uart_config/test_rd_addr_7_s1/Q |
| 0.820 | 0.006 | tNET | FF | 1 | R49C79[0][A] | u_usb_uart_config/n1829_s2/I1 |
| 0.973 | 0.153 | tINS | FF | 1 | R49C79[0][A] | u_usb_uart_config/n1829_s2/F |
| 0.973 | 0.000 | tNET | FF | 1 | R49C79[0][A] | u_usb_uart_config/test_rd_addr_7_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | R49C79[0][A] | u_usb_uart_config/test_rd_addr_7_s1/CLK |
| 0.698 | 0.025 | tHld | 1 | R49C79[0][A] | u_usb_uart_config/test_rd_addr_7_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
Path20
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 0.977 |
| Data Required Time | 0.702 |
| From | u_usb_uart_config/endpt0_txcork_s0 |
| To | u_usb_uart_config/endpt0_txcork_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R46C80[0][A] | u_usb_uart_config/endpt0_txcork_s0/CLK |
| 0.818 | 0.141 | tC2Q | RF | 2 | R46C80[0][A] | u_usb_uart_config/endpt0_txcork_s0/Q |
| 0.824 | 0.006 | tNET | FF | 1 | R46C80[0][A] | u_usb_uart_config/n1730_s2/I1 |
| 0.977 | 0.153 | tINS | FF | 1 | R46C80[0][A] | u_usb_uart_config/n1730_s2/F |
| 0.977 | 0.000 | tNET | FF | 1 | R46C80[0][A] | u_usb_uart_config/endpt0_txcork_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R46C80[0][A] | u_usb_uart_config/endpt0_txcork_s0/CLK |
| 0.702 | 0.025 | tHld | 1 | R46C80[0][A] | u_usb_uart_config/endpt0_txcork_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
Path21
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 0.973 |
| Data Required Time | 0.698 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_q_s4 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_q_s4 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | R70C99[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_q_s4/CLK |
| 0.814 | 0.141 | tC2Q | RF | 4 | R70C99[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_q_s4/Q |
| 0.820 | 0.006 | tNET | FF | 1 | R70C99[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n55_s2/I0 |
| 0.973 | 0.153 | tINS | FF | 1 | R70C99[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n55_s2/F |
| 0.973 | 0.000 | tNET | FF | 1 | R70C99[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_q_s4/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | R70C99[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_q_s4/CLK |
| 0.698 | 0.025 | tHld | 1 | R70C99[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_q_s4 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
Path22
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 0.977 |
| Data Required Time | 0.702 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rx_dp_q_s4 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rx_dp_q_s4 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R68C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rx_dp_q_s4/CLK |
| 0.818 | 0.141 | tC2Q | RF | 9 | R68C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rx_dp_q_s4/Q |
| 0.824 | 0.006 | tNET | FF | 1 | R68C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n43_s2/I0 |
| 0.977 | 0.153 | tINS | FF | 1 | R68C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n43_s2/F |
| 0.977 | 0.000 | tNET | FF | 1 | R68C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rx_dp_q_s4/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R68C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rx_dp_q_s4/CLK |
| 0.702 | 0.025 | tHld | 1 | R68C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rx_dp_q_s4 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
Path23
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 0.973 |
| Data Required Time | 0.698 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_ms_s4 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_ms_s4 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | R68C101[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_ms_s4/CLK |
| 0.814 | 0.141 | tC2Q | RF | 2 | R68C101[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_ms_s4/Q |
| 0.820 | 0.006 | tNET | FF | 1 | R68C101[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n33_s2/I0 |
| 0.973 | 0.153 | tINS | FF | 1 | R68C101[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n33_s2/F |
| 0.973 | 0.000 | tNET | FF | 1 | R68C101[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_ms_s4/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | R68C101[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_ms_s4/CLK |
| 0.698 | 0.025 | tHld | 1 | R68C101[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/rxd_ms_s4 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
Path24
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 0.977 |
| Data Required Time | 0.702 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_14_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_14_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R68C96[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_14_s0/CLK |
| 0.818 | 0.141 | tC2Q | RF | 7 | R68C96[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_14_s0/Q |
| 0.824 | 0.006 | tNET | FF | 1 | R68C96[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n610_s1/I1 |
| 0.977 | 0.153 | tINS | FF | 1 | R68C96[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n610_s1/F |
| 0.977 | 0.000 | tNET | FF | 1 | R68C96[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_14_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R68C96[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_14_s0/CLK |
| 0.702 | 0.025 | tHld | 1 | R68C96[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_14_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
Path25
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 0.973 |
| Data Required Time | 0.698 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/q_tx_cnt_0_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/q_tx_cnt_0_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | R53C97[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/q_tx_cnt_0_s0/CLK |
| 0.814 | 0.141 | tC2Q | RF | 3 | R53C97[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/q_tx_cnt_0_s0/Q |
| 0.820 | 0.006 | tNET | FF | 1 | R53C97[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n412_s8/I1 |
| 0.973 | 0.153 | tINS | FF | 1 | R53C97[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n412_s8/F |
| 0.973 | 0.000 | tNET | FF | 1 | R53C97[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/q_tx_cnt_0_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | R53C97[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/q_tx_cnt_0_s0/CLK |
| 0.698 | 0.025 | tHld | 1 | R53C97[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/q_tx_cnt_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 1.727 |
| Data Arrival Time | 8.401 |
| Data Required Time | 10.128 |
| From | reset_cnt_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_r_1_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[F] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 2.118 | 2.118 | tNET | RR | 1 | R57C75[0][A] | reset_cnt_1_s0/CLK |
| 2.501 | 0.382 | tC2Q | RR | 2 | R57C75[0][A] | reset_cnt_1_s0/Q |
| 2.641 | 0.140 | tNET | RR | 1 | R57C75[3][A] | n116_s106/I2 |
| 3.162 | 0.521 | tINS | RR | 1 | R57C75[3][A] | n116_s106/F |
| 3.164 | 0.003 | tNET | RR | 1 | R57C75[3][B] | n116_s105/I0 |
| 3.579 | 0.415 | tINS | RR | 1 | R57C75[3][B] | n116_s105/F |
| 3.737 | 0.157 | tNET | RR | 1 | R57C76[3][A] | n116_s100/I2 |
| 4.152 | 0.415 | tINS | RR | 1 | R57C76[3][A] | n116_s100/F |
| 4.154 | 0.003 | tNET | RR | 1 | R57C76[3][B] | n116_s98/I1 |
| 4.569 | 0.415 | tINS | RR | 3 | R57C76[3][B] | n116_s98/F |
| 5.057 | 0.487 | tNET | RR | 1 | R58C77[3][B] | RESET_s1/I1 |
| 5.439 | 0.382 | tINS | RF | 478 | R58C77[3][B] | RESET_s1/F |
| 8.401 | 2.961 | tNET | FF | 1 | R51C98[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_r_1_s0/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.334 | 8.334 | active clock edge time | ||||
| 8.334 | 0.000 | clk60 | ||||
| 8.334 | 0.000 | tCL | FF | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 10.420 | 2.086 | tNET | FF | 1 | R51C98[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_r_1_s0/CLK |
| 10.128 | -0.292 | tSu | 1 | R51C98[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_r_1_s0 |
Path Statistics:
| Clock Skew | -0.032 |
| Setup Relationship | 8.334 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.118, 100.000% |
| Arrival Data Path Delay | cell: 2.149, 34.202%; route: 3.751, 59.710%; tC2Q: 0.382, 6.088% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.086, 100.000% |
Path2
Path Summary:
| Slack | 1.727 |
| Data Arrival Time | 8.401 |
| Data Required Time | 10.128 |
| From | reset_cnt_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_r_0_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[F] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 2.118 | 2.118 | tNET | RR | 1 | R57C75[0][A] | reset_cnt_1_s0/CLK |
| 2.501 | 0.382 | tC2Q | RR | 2 | R57C75[0][A] | reset_cnt_1_s0/Q |
| 2.641 | 0.140 | tNET | RR | 1 | R57C75[3][A] | n116_s106/I2 |
| 3.162 | 0.521 | tINS | RR | 1 | R57C75[3][A] | n116_s106/F |
| 3.164 | 0.003 | tNET | RR | 1 | R57C75[3][B] | n116_s105/I0 |
| 3.579 | 0.415 | tINS | RR | 1 | R57C75[3][B] | n116_s105/F |
| 3.737 | 0.157 | tNET | RR | 1 | R57C76[3][A] | n116_s100/I2 |
| 4.152 | 0.415 | tINS | RR | 1 | R57C76[3][A] | n116_s100/F |
| 4.154 | 0.003 | tNET | RR | 1 | R57C76[3][B] | n116_s98/I1 |
| 4.569 | 0.415 | tINS | RR | 3 | R57C76[3][B] | n116_s98/F |
| 5.057 | 0.487 | tNET | RR | 1 | R58C77[3][B] | RESET_s1/I1 |
| 5.439 | 0.382 | tINS | RF | 478 | R58C77[3][B] | RESET_s1/F |
| 8.401 | 2.961 | tNET | FF | 1 | R51C98[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_r_0_s0/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.334 | 8.334 | active clock edge time | ||||
| 8.334 | 0.000 | clk60 | ||||
| 8.334 | 0.000 | tCL | FF | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 10.420 | 2.086 | tNET | FF | 1 | R51C98[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_r_0_s0/CLK |
| 10.128 | -0.292 | tSu | 1 | R51C98[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_r_0_s0 |
Path Statistics:
| Clock Skew | -0.032 |
| Setup Relationship | 8.334 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.118, 100.000% |
| Arrival Data Path Delay | cell: 2.149, 34.202%; route: 3.751, 59.710%; tC2Q: 0.382, 6.088% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.086, 100.000% |
Path3
Path Summary:
| Slack | 1.868 |
| Data Arrival Time | 9.076 |
| Data Required Time | 10.944 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_0_s0 |
| Launch Clk | clk120:[F] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | clk120 | ||||
| 4.167 | 0.000 | tCL | FF | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | 1 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK |
| 7.554 | 0.442 | tC2Q | FF | 46 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q |
| 9.076 | 1.521 | tNET | FF | 1 | R63C99[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R63C99[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_0_s0/CLK |
| 10.944 | -0.347 | tSu | 1 | R63C99[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_0_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.945, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.521, 77.467%; tC2Q: 0.442, 22.533% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path4
Path Summary:
| Slack | 1.868 |
| Data Arrival Time | 9.076 |
| Data Required Time | 10.944 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_2_s0 |
| Launch Clk | clk120:[F] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | clk120 | ||||
| 4.167 | 0.000 | tCL | FF | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | 1 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK |
| 7.554 | 0.442 | tC2Q | FF | 46 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q |
| 9.076 | 1.521 | tNET | FF | 1 | R63C99[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R63C99[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_2_s0/CLK |
| 10.944 | -0.347 | tSu | 1 | R63C99[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_2_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.945, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.521, 77.467%; tC2Q: 0.442, 22.533% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path5
Path Summary:
| Slack | 2.260 |
| Data Arrival Time | 8.683 |
| Data Required Time | 10.944 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0 |
| Launch Clk | clk120:[F] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | clk120 | ||||
| 4.167 | 0.000 | tCL | FF | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | 1 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK |
| 7.554 | 0.442 | tC2Q | FF | 46 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q |
| 8.683 | 1.129 | tNET | FF | 1 | R62C101[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R62C101[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0/CLK |
| 10.944 | -0.347 | tSu | 1 | R62C101[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.945, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.129, 71.838%; tC2Q: 0.442, 28.162% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path6
Path Summary:
| Slack | 2.260 |
| Data Arrival Time | 8.683 |
| Data Required Time | 10.944 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_0_s0 |
| Launch Clk | clk120:[F] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | clk120 | ||||
| 4.167 | 0.000 | tCL | FF | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | 1 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK |
| 7.554 | 0.442 | tC2Q | FF | 46 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q |
| 8.683 | 1.129 | tNET | FF | 1 | R61C101[2][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R61C101[2][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_0_s0/CLK |
| 10.944 | -0.347 | tSu | 1 | R61C101[2][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_0_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.945, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.129, 71.838%; tC2Q: 0.442, 28.162% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path7
Path Summary:
| Slack | 2.260 |
| Data Arrival Time | 8.683 |
| Data Required Time | 10.944 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_1_s0 |
| Launch Clk | clk120:[F] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | clk120 | ||||
| 4.167 | 0.000 | tCL | FF | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | 1 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK |
| 7.554 | 0.442 | tC2Q | FF | 46 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q |
| 8.683 | 1.129 | tNET | FF | 1 | R62C101[3][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R62C101[3][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_1_s0/CLK |
| 10.944 | -0.347 | tSu | 1 | R62C101[3][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_1_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.945, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.129, 71.838%; tC2Q: 0.442, 28.162% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path8
Path Summary:
| Slack | 2.260 |
| Data Arrival Time | 8.683 |
| Data Required Time | 10.944 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_3_s0 |
| Launch Clk | clk120:[F] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | clk120 | ||||
| 4.167 | 0.000 | tCL | FF | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | 1 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK |
| 7.554 | 0.442 | tC2Q | FF | 46 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q |
| 8.683 | 1.129 | tNET | FF | 1 | R61C101[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R61C101[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_3_s0/CLK |
| 10.944 | -0.347 | tSu | 1 | R61C101[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_3_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.945, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.129, 71.838%; tC2Q: 0.442, 28.162% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path9
Path Summary:
| Slack | 2.260 |
| Data Arrival Time | 8.683 |
| Data Required Time | 10.944 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_0_s0 |
| Launch Clk | clk120:[F] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | clk120 | ||||
| 4.167 | 0.000 | tCL | FF | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | 1 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK |
| 7.554 | 0.442 | tC2Q | FF | 46 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q |
| 8.683 | 1.129 | tNET | FF | 1 | R62C101[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R62C101[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_0_s0/CLK |
| 10.944 | -0.347 | tSu | 1 | R62C101[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_0_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.945, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.129, 71.838%; tC2Q: 0.442, 28.162% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path10
Path Summary:
| Slack | 2.260 |
| Data Arrival Time | 8.683 |
| Data Required Time | 10.944 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_1_s0 |
| Launch Clk | clk120:[F] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | clk120 | ||||
| 4.167 | 0.000 | tCL | FF | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | 1 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK |
| 7.554 | 0.442 | tC2Q | FF | 46 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q |
| 8.683 | 1.129 | tNET | FF | 1 | R62C101[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R62C101[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_1_s0/CLK |
| 10.944 | -0.347 | tSu | 1 | R62C101[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_1_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.945, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.129, 71.838%; tC2Q: 0.442, 28.162% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path11
Path Summary:
| Slack | 2.260 |
| Data Arrival Time | 8.683 |
| Data Required Time | 10.944 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_3_s0 |
| Launch Clk | clk120:[F] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | clk120 | ||||
| 4.167 | 0.000 | tCL | FF | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | 1 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK |
| 7.554 | 0.442 | tC2Q | FF | 46 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q |
| 8.683 | 1.129 | tNET | FF | 1 | R61C101[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R61C101[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_3_s0/CLK |
| 10.944 | -0.347 | tSu | 1 | R61C101[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_3_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.945, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.129, 71.838%; tC2Q: 0.442, 28.162% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path12
Path Summary:
| Slack | 2.392 |
| Data Arrival Time | 8.542 |
| Data Required Time | 10.934 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_0_s0 |
| Launch Clk | clk120:[F] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | clk120 | ||||
| 4.167 | 0.000 | tCL | FF | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | 1 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK |
| 7.554 | 0.442 | tC2Q | FF | 46 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q |
| 8.542 | 0.988 | tNET | FF | 1 | R51C96[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.282 | 2.949 | tNET | RR | 1 | R51C96[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_0_s0/CLK |
| 10.934 | -0.347 | tSu | 1 | R51C96[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_0_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.945, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.988, 69.056%; tC2Q: 0.442, 30.944% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.949, 100.000% |
Path13
Path Summary:
| Slack | 2.392 |
| Data Arrival Time | 8.542 |
| Data Required Time | 10.934 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_1_s0 |
| Launch Clk | clk120:[F] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | clk120 | ||||
| 4.167 | 0.000 | tCL | FF | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | 1 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK |
| 7.554 | 0.442 | tC2Q | FF | 46 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q |
| 8.542 | 0.988 | tNET | FF | 1 | R51C96[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.282 | 2.949 | tNET | RR | 1 | R51C96[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_1_s0/CLK |
| 10.934 | -0.347 | tSu | 1 | R51C96[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_1_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.945, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.988, 69.056%; tC2Q: 0.442, 30.944% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.949, 100.000% |
Path14
Path Summary:
| Slack | 2.392 |
| Data Arrival Time | 8.542 |
| Data Required Time | 10.934 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_2_s0 |
| Launch Clk | clk120:[F] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | clk120 | ||||
| 4.167 | 0.000 | tCL | FF | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | 1 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK |
| 7.554 | 0.442 | tC2Q | FF | 46 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q |
| 8.542 | 0.988 | tNET | FF | 1 | R51C96[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.282 | 2.949 | tNET | RR | 1 | R51C96[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_2_s0/CLK |
| 10.934 | -0.347 | tSu | 1 | R51C96[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_2_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.945, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.988, 69.056%; tC2Q: 0.442, 30.944% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.949, 100.000% |
Path15
Path Summary:
| Slack | 2.392 |
| Data Arrival Time | 8.542 |
| Data Required Time | 10.934 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_1_s0 |
| Launch Clk | clk120:[F] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | clk120 | ||||
| 4.167 | 0.000 | tCL | FF | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | 1 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK |
| 7.554 | 0.442 | tC2Q | FF | 46 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q |
| 8.542 | 0.988 | tNET | FF | 1 | R51C96[2][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.282 | 2.949 | tNET | RR | 1 | R51C96[2][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_1_s0/CLK |
| 10.934 | -0.347 | tSu | 1 | R51C96[2][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq1_rptr_1_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.945, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.988, 69.056%; tC2Q: 0.442, 30.944% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.949, 100.000% |
Path16
Path Summary:
| Slack | 2.505 |
| Data Arrival Time | 8.438 |
| Data Required Time | 10.944 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_4_s0 |
| Launch Clk | clk120:[F] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | clk120 | ||||
| 4.167 | 0.000 | tCL | FF | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | 1 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK |
| 7.554 | 0.442 | tC2Q | FF | 46 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q |
| 8.438 | 0.884 | tNET | FF | 1 | R63C101[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_4_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R63C101[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_4_s0/CLK |
| 10.944 | -0.347 | tSu | 1 | R63C101[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_4_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.945, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.884, 66.635%; tC2Q: 0.442, 33.365% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path17
Path Summary:
| Slack | 2.627 |
| Data Arrival Time | 8.317 |
| Data Required Time | 10.944 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_3_s0 |
| Launch Clk | clk120:[F] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | clk120 | ||||
| 4.167 | 0.000 | tCL | FF | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | 1 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK |
| 7.554 | 0.442 | tC2Q | FF | 46 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q |
| 8.317 | 0.762 | tNET | FF | 1 | R51C95[2][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R51C95[2][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_3_s0/CLK |
| 10.944 | -0.347 | tSu | 1 | R51C95[2][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_3_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.945, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.762, 63.278%; tC2Q: 0.442, 36.722% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path18
Path Summary:
| Slack | 2.627 |
| Data Arrival Time | 8.317 |
| Data Required Time | 10.944 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_4_s0 |
| Launch Clk | clk120:[F] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | clk120 | ||||
| 4.167 | 0.000 | tCL | FF | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | 1 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK |
| 7.554 | 0.442 | tC2Q | FF | 46 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q |
| 8.317 | 0.762 | tNET | FF | 1 | R51C95[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_4_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R51C95[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_4_s0/CLK |
| 10.944 | -0.347 | tSu | 1 | R51C95[1][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_4_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.945, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.762, 63.278%; tC2Q: 0.442, 36.722% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path19
Path Summary:
| Slack | 2.627 |
| Data Arrival Time | 8.317 |
| Data Required Time | 10.944 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_5_s0 |
| Launch Clk | clk120:[F] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | clk120 | ||||
| 4.167 | 0.000 | tCL | FF | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | 1 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK |
| 7.554 | 0.442 | tC2Q | FF | 46 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q |
| 8.317 | 0.762 | tNET | FF | 1 | R51C95[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_5_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R51C95[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_5_s0/CLK |
| 10.944 | -0.347 | tSu | 1 | R51C95[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_5_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.945, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.762, 63.278%; tC2Q: 0.442, 36.722% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path20
Path Summary:
| Slack | 2.714 |
| Data Arrival Time | 8.221 |
| Data Required Time | 10.934 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_1_s0 |
| Launch Clk | clk120:[F] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | clk120 | ||||
| 4.167 | 0.000 | tCL | FF | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | 1 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK |
| 7.554 | 0.442 | tC2Q | FF | 46 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q |
| 8.221 | 0.666 | tNET | FF | 1 | R62C100[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.282 | 2.949 | tNET | RR | 1 | R62C100[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_1_s0/CLK |
| 10.934 | -0.347 | tSu | 1 | R62C100[0][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_1_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.945, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.666, 60.090%; tC2Q: 0.442, 39.910% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.949, 100.000% |
Path21
Path Summary:
| Slack | 2.714 |
| Data Arrival Time | 8.221 |
| Data Required Time | 10.934 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_3_s0 |
| Launch Clk | clk120:[F] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | clk120 | ||||
| 4.167 | 0.000 | tCL | FF | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | 1 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK |
| 7.554 | 0.442 | tC2Q | FF | 46 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q |
| 8.221 | 0.666 | tNET | FF | 1 | R62C100[3][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.282 | 2.949 | tNET | RR | 1 | R62C100[3][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_3_s0/CLK |
| 10.934 | -0.347 | tSu | 1 | R62C100[3][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_3_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.945, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.666, 60.090%; tC2Q: 0.442, 39.910% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.949, 100.000% |
Path22
Path Summary:
| Slack | 2.714 |
| Data Arrival Time | 8.221 |
| Data Required Time | 10.934 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_2_s0 |
| Launch Clk | clk120:[F] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | clk120 | ||||
| 4.167 | 0.000 | tCL | FF | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | 1 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK |
| 7.554 | 0.442 | tC2Q | FF | 46 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q |
| 8.221 | 0.666 | tNET | FF | 1 | R62C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.282 | 2.949 | tNET | RR | 1 | R62C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_2_s0/CLK |
| 10.934 | -0.347 | tSu | 1 | R62C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_2_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.945, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.666, 60.090%; tC2Q: 0.442, 39.910% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.949, 100.000% |
Path23
Path Summary:
| Slack | 2.714 |
| Data Arrival Time | 8.221 |
| Data Required Time | 10.934 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_5_s0 |
| Launch Clk | clk120:[F] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | clk120 | ||||
| 4.167 | 0.000 | tCL | FF | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | 1 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK |
| 7.554 | 0.442 | tC2Q | FF | 46 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q |
| 8.221 | 0.666 | tNET | FF | 1 | R62C100[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_5_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.282 | 2.949 | tNET | RR | 1 | R62C100[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_5_s0/CLK |
| 10.934 | -0.347 | tSu | 1 | R62C100[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_5_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.945, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.666, 60.090%; tC2Q: 0.442, 39.910% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.949, 100.000% |
Path24
Path Summary:
| Slack | 2.722 |
| Data Arrival Time | 8.222 |
| Data Required Time | 10.944 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_2_s0 |
| Launch Clk | clk120:[F] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | clk120 | ||||
| 4.167 | 0.000 | tCL | FF | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | 1 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK |
| 7.554 | 0.442 | tC2Q | FF | 46 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q |
| 8.222 | 0.667 | tNET | FF | 1 | R60C101[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R60C101[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_2_s0/CLK |
| 10.944 | -0.347 | tSu | 1 | R60C101[1][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_2_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.945, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.667, 60.135%; tC2Q: 0.442, 39.865% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path25
Path Summary:
| Slack | 2.722 |
| Data Arrival Time | 8.222 |
| Data Required Time | 10.944 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_4_s0 |
| Launch Clk | clk120:[F] |
| Latch Clk | clk120:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | clk120 | ||||
| 4.167 | 0.000 | tCL | FF | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | 1 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK |
| 7.554 | 0.442 | tC2Q | FF | 46 | R50C100[0][A] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q |
| 8.222 | 0.667 | tNET | FF | 1 | R60C101[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_4_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | clk120 | ||||
| 8.333 | 0.000 | tCL | RR | 165 | RIGHTSIDE[0] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 11.291 | 2.958 | tNET | RR | 1 | R60C101[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_4_s0/CLK |
| 10.944 | -0.347 | tSu | 1 | R60C101[2][B] | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_4_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.945, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.667, 60.135%; tC2Q: 0.442, 39.865% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 1.367 |
| Data Arrival Time | 2.033 |
| Data Required Time | 0.666 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_1_s |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.033 | 1.212 | tNET | RR | 4 | BSRAM_R56[11][A] | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_1_s/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | BSRAM_R56[11][A] | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_1_s/CLKB |
| 0.666 | -0.011 | tHld | 1 | BSRAM_R56[11][A] | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_1_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.212, 89.381%; tC2Q: 0.144, 10.619% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
Path2
Path Summary:
| Slack | 1.367 |
| Data Arrival Time | 2.033 |
| Data Required Time | 0.666 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.033 | 1.212 | tNET | RR | 4 | BSRAM_R56[13][B] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | BSRAM_R56[13][B] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/CLKB |
| 0.666 | -0.011 | tHld | 1 | BSRAM_R56[13][B] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.212, 89.381%; tC2Q: 0.144, 10.619% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
Path3
Path Summary:
| Slack | 1.367 |
| Data Arrival Time | 2.033 |
| Data Required Time | 0.666 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.033 | 1.212 | tNET | RR | 4 | BSRAM_R56[16] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | BSRAM_R56[16] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/CLKB |
| 0.666 | -0.011 | tHld | 1 | BSRAM_R56[16] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.212, 89.381%; tC2Q: 0.144, 10.619% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
Path4
Path Summary:
| Slack | 1.367 |
| Data Arrival Time | 2.029 |
| Data Required Time | 0.662 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.029 | 1.208 | tNET | RR | 4 | BSRAM_R56[10] | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | BSRAM_R56[10] | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/CLKB |
| 0.662 | -0.011 | tHld | 1 | BSRAM_R56[10] | usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.208, 89.349%; tC2Q: 0.144, 10.651% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
Path5
Path Summary:
| Slack | 1.367 |
| Data Arrival Time | 2.029 |
| Data Required Time | 0.662 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.029 | 1.208 | tNET | RR | 4 | BSRAM_R56[13][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | BSRAM_R56[13][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/CLKB |
| 0.662 | -0.011 | tHld | 1 | BSRAM_R56[13][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.208, 89.349%; tC2Q: 0.144, 10.651% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
Path6
Path Summary:
| Slack | 1.367 |
| Data Arrival Time | 2.029 |
| Data Required Time | 0.662 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.029 | 1.208 | tNET | RR | 4 | BSRAM_R56[18] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | BSRAM_R56[18] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s/CLKB |
| 0.662 | -0.011 | tHld | 1 | BSRAM_R56[18] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.208, 89.349%; tC2Q: 0.144, 10.651% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
Path7
Path Summary:
| Slack | 1.371 |
| Data Arrival Time | 2.029 |
| Data Required Time | 0.658 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.029 | 1.208 | tNET | RR | 4 | BSRAM_R56[15][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.669 | 0.669 | tNET | RR | 1 | BSRAM_R56[15][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s/CLKB |
| 0.658 | -0.011 | tHld | 1 | BSRAM_R56[15][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s |
Path Statistics:
| Clock Skew | -0.008 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.208, 89.349%; tC2Q: 0.144, 10.651% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.669, 100.000% |
Path8
Path Summary:
| Slack | 1.375 |
| Data Arrival Time | 2.033 |
| Data Required Time | 0.658 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.033 | 1.212 | tNET | RR | 4 | BSRAM_R56[15][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.669 | 0.669 | tNET | RR | 1 | BSRAM_R56[15][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKB |
| 0.658 | -0.011 | tHld | 1 | BSRAM_R56[15][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0 |
Path Statistics:
| Clock Skew | -0.008 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.212, 89.381%; tC2Q: 0.144, 10.619% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.669, 100.000% |
Path9
Path Summary:
| Slack | 1.375 |
| Data Arrival Time | 2.033 |
| Data Required Time | 0.658 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_1_s |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.033 | 1.212 | tNET | RR | 4 | BSRAM_R56[9][B] | usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_1_s/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.669 | 0.669 | tNET | RR | 1 | BSRAM_R56[9][B] | usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_1_s/CLKB |
| 0.658 | -0.011 | tHld | 1 | BSRAM_R56[9][B] | usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_1_s |
Path Statistics:
| Clock Skew | -0.008 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.212, 89.381%; tC2Q: 0.144, 10.619% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.669, 100.000% |
Path10
Path Summary:
| Slack | 1.375 |
| Data Arrival Time | 2.037 |
| Data Required Time | 0.662 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.037 | 1.216 | tNET | RR | 4 | BSRAM_R56[14] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | BSRAM_R56[14] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s/CLKB |
| 0.662 | -0.011 | tHld | 1 | BSRAM_R56[14] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.216, 89.412%; tC2Q: 0.144, 10.588% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
Path11
Path Summary:
| Slack | 1.375 |
| Data Arrival Time | 2.037 |
| Data Required Time | 0.662 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_0_s |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.037 | 1.216 | tNET | RR | 4 | BSRAM_R56[9][A] | usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_0_s/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | BSRAM_R56[9][A] | usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_0_s/CLKB |
| 0.662 | -0.011 | tHld | 1 | BSRAM_R56[9][A] | usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_0_s |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.216, 89.412%; tC2Q: 0.144, 10.588% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
Path12
Path Summary:
| Slack | 1.375 |
| Data Arrival Time | 2.037 |
| Data Required Time | 0.662 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.037 | 1.216 | tNET | RR | 4 | BSRAM_R56[17][A] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | BSRAM_R56[17][A] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKB |
| 0.662 | -0.011 | tHld | 1 | BSRAM_R56[17][A] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.216, 89.412%; tC2Q: 0.144, 10.588% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
Path13
Path Summary:
| Slack | 1.404 |
| Data Arrival Time | 2.024 |
| Data Required Time | 0.620 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/wbin_2_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.024 | 1.203 | tNET | RR | 1 | R40C64[1][A] | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/wbin_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | R40C64[1][A] | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/wbin_2_s0/CLK |
| 0.620 | -0.053 | tHld | 1 | R40C64[1][A] | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/wbin_2_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.203, 89.310%; tC2Q: 0.144, 10.690% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
Path14
Path Summary:
| Slack | 1.408 |
| Data Arrival Time | 2.032 |
| Data Required Time | 0.624 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_5_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.032 | 1.211 | tNET | RR | 1 | R41C55[0][B] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_5_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R41C55[0][B] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_5_s0/CLK |
| 0.624 | -0.053 | tHld | 1 | R41C55[0][B] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.211, 89.373%; tC2Q: 0.144, 10.627% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
Path15
Path Summary:
| Slack | 1.408 |
| Data Arrival Time | 2.032 |
| Data Required Time | 0.624 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_4_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.032 | 1.211 | tNET | RR | 1 | R41C55[0][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_4_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R41C55[0][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_4_s0/CLK |
| 0.624 | -0.053 | tHld | 1 | R41C55[0][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.211, 89.373%; tC2Q: 0.144, 10.627% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
Path16
Path Summary:
| Slack | 1.408 |
| Data Arrival Time | 2.032 |
| Data Required Time | 0.624 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_6_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.032 | 1.211 | tNET | RR | 1 | R41C59[3][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_6_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R41C59[3][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_6_s0/CLK |
| 0.624 | -0.053 | tHld | 1 | R41C59[3][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.211, 89.373%; tC2Q: 0.144, 10.627% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
Path17
Path Summary:
| Slack | 1.408 |
| Data Arrival Time | 2.032 |
| Data Required Time | 0.624 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rq2_wptr_1_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.032 | 1.211 | tNET | RR | 1 | R41C55[1][B] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rq2_wptr_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R41C55[1][B] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rq2_wptr_1_s0/CLK |
| 0.624 | -0.053 | tHld | 1 | R41C55[1][B] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rq2_wptr_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.211, 89.373%; tC2Q: 0.144, 10.627% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
Path18
Path Summary:
| Slack | 1.408 |
| Data Arrival Time | 2.028 |
| Data Required Time | 0.620 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_4_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.028 | 1.207 | tNET | RR | 1 | R41C56[0][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_4_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | R41C56[0][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_4_s0/CLK |
| 0.620 | -0.053 | tHld | 1 | R41C56[0][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_4_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.207, 89.341%; tC2Q: 0.144, 10.659% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
Path19
Path Summary:
| Slack | 1.408 |
| Data Arrival Time | 2.028 |
| Data Required Time | 0.620 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_3_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.028 | 1.207 | tNET | RR | 1 | R41C56[1][B] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | R41C56[1][B] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_3_s0/CLK |
| 0.620 | -0.053 | tHld | 1 | R41C56[1][B] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_3_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.207, 89.341%; tC2Q: 0.144, 10.659% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
Path20
Path Summary:
| Slack | 1.408 |
| Data Arrival Time | 2.028 |
| Data Required Time | 0.620 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_5_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.028 | 1.207 | tNET | RR | 1 | R41C56[3][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_5_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | R41C56[3][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_5_s0/CLK |
| 0.620 | -0.053 | tHld | 1 | R41C56[3][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wptr_5_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.207, 89.341%; tC2Q: 0.144, 10.659% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
Path21
Path Summary:
| Slack | 1.408 |
| Data Arrival Time | 2.028 |
| Data Required Time | 0.620 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_1_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.028 | 1.207 | tNET | RR | 1 | R41C60[1][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | R41C60[1][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_1_s0/CLK |
| 0.620 | -0.053 | tHld | 1 | R41C60[1][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_1_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.207, 89.341%; tC2Q: 0.144, 10.659% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
Path22
Path Summary:
| Slack | 1.408 |
| Data Arrival Time | 2.028 |
| Data Required Time | 0.620 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_2_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.028 | 1.207 | tNET | RR | 1 | R41C60[2][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | R41C60[2][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_2_s0/CLK |
| 0.620 | -0.053 | tHld | 1 | R41C60[2][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rptr_2_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.207, 89.341%; tC2Q: 0.144, 10.659% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
Path23
Path Summary:
| Slack | 1.408 |
| Data Arrival Time | 2.028 |
| Data Required Time | 0.620 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rq2_wptr_3_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.028 | 1.207 | tNET | RR | 1 | R41C56[0][B] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rq2_wptr_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | R41C56[0][B] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rq2_wptr_3_s0/CLK |
| 0.620 | -0.053 | tHld | 1 | R41C56[0][B] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rq2_wptr_3_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.207, 89.341%; tC2Q: 0.144, 10.659% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
Path24
Path Summary:
| Slack | 1.408 |
| Data Arrival Time | 2.028 |
| Data Required Time | 0.620 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rq2_wptr_5_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.028 | 1.207 | tNET | RR | 1 | R41C56[2][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rq2_wptr_5_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | R41C56[2][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rq2_wptr_5_s0/CLK |
| 0.620 | -0.053 | tHld | 1 | R41C56[2][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rq2_wptr_5_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.207, 89.341%; tC2Q: 0.144, 10.659% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
Path25
Path Summary:
| Slack | 1.408 |
| Data Arrival Time | 2.028 |
| Data Required Time | 0.620 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0 |
| To | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rq1_wptr_3_s0 |
| Launch Clk | clk60:[R] |
| Latch Clk | clk60:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.677 | 0.677 | tNET | RR | 1 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK |
| 0.821 | 0.144 | tC2Q | RR | 888 | R73C88[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q |
| 2.028 | 1.207 | tNET | RR | 1 | R41C56[1][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rq1_wptr_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk60 | ||||
| 0.000 | 0.000 | tCL | RR | 3597 | PLL_L[0] | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.673 | 0.673 | tNET | RR | 1 | R41C56[1][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rq1_wptr_3_s0/CLK |
| 0.620 | -0.053 | tHld | 1 | R41C56[1][A] | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rq1_wptr_3_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.677, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.207, 89.341%; tC2Q: 0.144, 10.659% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.673, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
| Slack: | 1.243 |
| Actual Width: | 2.243 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | clk120 |
| Objects: | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.167 | 0.000 | active clock edge time | ||
| 4.167 | 0.000 | clk120 | ||
| 4.167 | 0.000 | tCL | FF | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | clk120 | ||
| 8.333 | 0.000 | tCL | RR | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 9.355 | 1.022 | tNET | RR | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/CLKA |
MPW2
MPW Summary:
| Slack: | 1.243 |
| Actual Width: | 2.243 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | clk120 |
| Objects: | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.167 | 0.000 | active clock edge time | ||
| 4.167 | 0.000 | clk120 | ||
| 4.167 | 0.000 | tCL | FF | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.112 | 2.945 | tNET | FF | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/CLKB |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | clk120 | ||
| 8.333 | 0.000 | tCL | RR | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 9.355 | 1.022 | tNET | RR | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/CLKB |
MPW3
MPW Summary:
| Slack: | 1.245 |
| Actual Width: | 2.245 |
| Required Width: | 1.000 |
| Type: | High Pulse Width |
| Clock: | clk120 |
| Objects: | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | clk120 | ||
| 0.000 | 0.000 | tCL | RR | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.949 | 2.949 | tNET | RR | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.167 | 0.000 | active clock edge time | ||
| 4.167 | 0.000 | clk120 | ||
| 4.167 | 0.000 | tCL | FF | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 5.194 | 1.027 | tNET | FF | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/CLKA |
MPW4
MPW Summary:
| Slack: | 1.245 |
| Actual Width: | 2.245 |
| Required Width: | 1.000 |
| Type: | High Pulse Width |
| Clock: | clk120 |
| Objects: | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | clk120 | ||
| 0.000 | 0.000 | tCL | RR | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 2.949 | 2.949 | tNET | RR | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/CLKB |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.167 | 0.000 | active clock edge time | ||
| 4.167 | 0.000 | clk120 | ||
| 4.167 | 0.000 | tCL | FF | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 5.194 | 1.027 | tNET | FF | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/CLKB |
MPW5
MPW Summary:
| Slack: | 1.982 |
| Actual Width: | 2.232 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | clk120 |
| Objects: | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_2_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.167 | 0.000 | active clock edge time | ||
| 4.167 | 0.000 | clk120 | ||
| 4.167 | 0.000 | tCL | FF | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.131 | 2.964 | tNET | FF | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_2_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | clk120 | ||
| 8.333 | 0.000 | tCL | RR | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 9.363 | 1.030 | tNET | RR | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_2_s0/CLK |
MPW6
MPW Summary:
| Slack: | 1.982 |
| Actual Width: | 2.232 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | clk120 |
| Objects: | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_4_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.167 | 0.000 | active clock edge time | ||
| 4.167 | 0.000 | clk120 | ||
| 4.167 | 0.000 | tCL | FF | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.131 | 2.964 | tNET | FF | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_4_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | clk120 | ||
| 8.333 | 0.000 | tCL | RR | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 9.363 | 1.030 | tNET | RR | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_4_s0/CLK |
MPW7
MPW Summary:
| Slack: | 1.982 |
| Actual Width: | 2.232 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | clk120 |
| Objects: | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_1_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.167 | 0.000 | active clock edge time | ||
| 4.167 | 0.000 | clk120 | ||
| 4.167 | 0.000 | tCL | FF | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.131 | 2.964 | tNET | FF | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_1_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | clk120 | ||
| 8.333 | 0.000 | tCL | RR | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 9.363 | 1.030 | tNET | RR | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_1_s0/CLK |
MPW8
MPW Summary:
| Slack: | 1.982 |
| Actual Width: | 2.232 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | clk120 |
| Objects: | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_0_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.167 | 0.000 | active clock edge time | ||
| 4.167 | 0.000 | clk120 | ||
| 4.167 | 0.000 | tCL | FF | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.131 | 2.964 | tNET | FF | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_0_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | clk120 | ||
| 8.333 | 0.000 | tCL | RR | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 9.363 | 1.030 | tNET | RR | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_0_s0/CLK |
MPW9
MPW Summary:
| Slack: | 1.982 |
| Actual Width: | 2.232 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | clk120 |
| Objects: | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.167 | 0.000 | active clock edge time | ||
| 4.167 | 0.000 | clk120 | ||
| 4.167 | 0.000 | tCL | FF | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.131 | 2.964 | tNET | FF | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | clk120 | ||
| 8.333 | 0.000 | tCL | RR | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 9.363 | 1.030 | tNET | RR | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_s0/CLK |
MPW10
MPW Summary:
| Slack: | 1.982 |
| Actual Width: | 2.232 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | clk120 |
| Objects: | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_3_s1 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.167 | 0.000 | active clock edge time | ||
| 4.167 | 0.000 | clk120 | ||
| 4.167 | 0.000 | tCL | FF | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 7.131 | 2.964 | tNET | FF | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_3_s1/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | clk120 | ||
| 8.333 | 0.000 | tCL | RR | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 9.363 | 1.030 | tNET | RR | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_3_s1/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
| FANOUT | NET NAME | WORST SLACK | MAX DELAY |
|---|---|---|---|
| 3597 | PHY_CLKOUT | 1.727 | 2.118 |
| 888 | usb_busreset | 8.989 | 2.959 |
| 478 | RESET | 1.727 | 3.301 |
| 260 | usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/rbin[5] | 12.250 | 1.876 |
| 260 | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin[5] | 10.330 | 3.276 |
| 260 | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/rbin[5] | 10.688 | 2.291 |
| 260 | usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/rbin[5] | 12.177 | 2.076 |
| 165 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/sclk | 0.695 | 2.977 |
| 130 | usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/rbin[4] | 12.461 | 1.899 |
| 130 | usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin[4] | 11.866 | 1.684 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
| GRID LOC | ROUTE CONGESTIONS |
|---|---|
| R2C75 | 100.00% |
| R2C77 | 100.00% |
| R2C81 | 100.00% |
| R2C89 | 100.00% |
| R2C105 | 100.00% |
| R2C137 | 100.00% |
| R3C129 | 100.00% |
| R5C113 | 100.00% |
| R9C81 | 100.00% |
| R17C89 | 100.00% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
| SDC Command Type | State | Detail Command |
|---|---|---|
| TC_CLOCK | Actived | create_clock -name clk60 -period 16.667 -waveform {0 8.334} [get_nets {PHY_CLKOUT}] |
| TC_CLOCK | Actived | create_clock -name clk120 -period 8.333 -waveform {0 4.167} [get_nets {u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/sclk}] |
| TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {clk60}] -to [get_clocks {clk120}] |
| TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {clk120}] -to [get_clocks {clk60}] |