Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj60k_usb2_loopback_speed\prj60k_usb2_loopback_speed_dual_lvds\project\src\TOP.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj60k_usb2_loopback_speed\prj60k_usb2_loopback_speed_dual_lvds\project\src\fixed_point_divider\fixed_point_divider.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj60k_usb2_loopback_speed\prj60k_usb2_loopback_speed_dual_lvds\project\src\gowin_pll\gowin_pll.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj60k_usb2_loopback_speed\prj60k_usb2_loopback_speed_dual_lvds\project\src\sync_fifo\sync_rx_pkt_fifo.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj60k_usb2_loopback_speed\prj60k_usb2_loopback_speed_dual_lvds\project\src\sync_fifo\sync_tx_pkt_fifo.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj60k_usb2_loopback_speed\prj60k_usb2_loopback_speed_dual_lvds\project\src\sync_fifo\usb_fifo.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj60k_usb2_loopback_speed\prj60k_usb2_loopback_speed_dual_lvds\project\src\uart\uart.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj60k_usb2_loopback_speed\prj60k_usb2_loopback_speed_dual_lvds\project\src\uart\usb_uart_config.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj60k_usb2_loopback_speed\prj60k_usb2_loopback_speed_dual_lvds\project\src\usb2_0_softphy\usb2_0_softphy.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj60k_usb2_loopback_speed\prj60k_usb2_loopback_speed_dual_lvds\project\src\usb_descriptor.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj60k_usb2_loopback_speed\prj60k_usb2_loopback_speed_dual_lvds\project\src\usb_device_controller\usb_device_controller.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj60k_usb2_loopback_speed\prj60k_usb2_loopback_speed_dual_lvds\project\src\gowin_pll\gowin_pll_mod.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj60k_usb2_loopback_speed\prj60k_usb2_loopback_speed_dual_lvds\project\src\pll_init.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj60k_usb2_loopback_speed\prj60k_usb2_loopback_speed_dual_lvds\project\src\uart\uart_rx.vhd D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj60k_usb2_loopback_speed\prj60k_usb2_loopback_speed_dual_lvds\project\src\uart\uart_tx.vhd |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12 (64-bit) |
| Part Number | GW5AT-LV60UG225C1/I0 |
| Device | GW5AT-60 |
| Device Version | B |
| Created Time | Thu Nov 6 09:15:54 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.765s, Elapsed time = 0h 0m 1s, Peak memory usage = 2009.281MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.393s, Peak memory usage = 2009.281MB Optimizing Phase 1: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.177s, Peak memory usage = 2009.281MB Optimizing Phase 2: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.349s, Peak memory usage = 2009.281MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.5s, Elapsed time = 0h 0m 0.536s, Peak memory usage = 2009.281MB Inferring Phase 1: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.398s, Peak memory usage = 2009.281MB Inferring Phase 2: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.158s, Peak memory usage = 2009.281MB Inferring Phase 3: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.114s, Peak memory usage = 2009.281MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 2009.281MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.397s, Peak memory usage = 2009.281MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.13s, Peak memory usage = 2009.281MB Tech-Mapping Phase 3: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 8s, Peak memory usage = 2009.281MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.968s, Elapsed time = 0h 0m 1s, Peak memory usage = 2009.281MB Generate output files: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 2009.281MB |
| Total Time and Memory Usage | CPU time = 0h 0m 13s, Elapsed time = 0h 0m 14s, Peak memory usage = 2009.281MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 11 |
| I/O Buf | 9 |
| IBUF | 3 |
| OBUF | 1 |
| TBUF | 1 |
| IOBUF | 2 |
| TLVDS_IBUF | 1 |
| ELVDS_TBUF | 1 |
| Register | 3829 |
| DFFSE | 39 |
| DFFRE | 2582 |
| DFFPE | 37 |
| DFFCE | 1171 |
| LUT | 4810 |
| LUT2 | 430 |
| LUT3 | 2190 |
| LUT4 | 2190 |
| ALU | 514 |
| ALU | 514 |
| INV | 56 |
| INV | 56 |
| IOLOGIC | 4 |
| IDES8 | 2 |
| IDES16 | 1 |
| OSER16 | 1 |
| BSRAM | 15 |
| SDPB | 14 |
| pROM | 1 |
| CLOCK | 3 |
| CLKDIV | 1 |
| DHCE | 1 |
| PLLA | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 5380(4866 LUT, 514 ALU) / 59904 | 9% |
| Register | 3829 / 60228 | 7% |
| --Register as Latch | 0 / 60228 | 0% |
| --Register as FF | 3829 / 60228 | 7% |
| BSRAM | 15 / 118 | 13% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | CLK_IN | Base | 41.667 | 24.000 | 0.000 | 20.833 | CLK_IN_ibuf/I | ||
| 2 | pll/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 16.667 | 60.000 | 0.000 | 8.333 | CLK_IN_ibuf/I | CLK_IN | pll/u_pll/PLLA_inst/CLKOUT0 |
| 3 | pll/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | Generated | 1.042 | 960.000 | 0.000 | 0.521 | CLK_IN_ibuf/I | CLK_IN | pll/u_pll/PLLA_inst/CLKOUT1 |
| 4 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk | Generated | 8.333 | 120.000 | 0.000 | 4.167 | pll/u_pll/PLLA_inst/CLKOUT1 | pll/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | CLK_IN | 24.000(MHz) | 162.767(MHz) | 7 | TOP |
| 2 | pll/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | 60.000(MHz) | 71.397(MHz) | 17 | TOP |
| 3 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk | 120.000(MHz) | 159.936(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -0.479 |
| Data Arrival Time | 1.414 |
| Data Required Time | 0.935 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/u_oser_rst/reset_stop_s2 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/dhcen_inst |
| Launch Clk | pll/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[F] |
| Latch Clk | pll/u_pll/PLLA_inst/CLKOUT1.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | pll/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 0.281 | 0.281 | tCL | RR | 3597 | pll/u_pll/PLLA_inst/CLKOUT0 |
| 0.656 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/u_oser_rst/reset_stop_s2/CLK |
| 1.039 | 0.382 | tC2Q | RR | 2 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/u_oser_rst/reset_stop_s2/Q |
| 1.414 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/dhcen_inst/CEN |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.521 | 0.000 | pll/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | |||
| 0.802 | 0.281 | tCL | FF | 1 | pll/u_pll/PLLA_inst/CLKOUT1 |
| 1.152 | 0.350 | tNET | FF | 3 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/dhcen_inst/CLKIN |
| 1.117 | -0.035 | tUnc | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/dhcen_inst | ||
| 0.935 | -0.182 | tSu | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/dhcen_inst |
| Clock Skew: | -0.025 |
| Setup Relationship: | 0.521 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.375, 49.505%; tC2Q: 0.382, 50.495% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:| Slack | 2.081 |
| Data Arrival Time | 6.926 |
| Data Required Time | 9.007 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides16 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s0 |
| Launch Clk | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 0.362 | 0.362 | tCL | RR | 165 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 0.737 | 0.375 | tNET | RR | 16 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides16/PCLK |
| 1.277 | 0.540 | tC2Q | RR | 5 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides16/Q7 |
| 1.652 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n300_s47/I2 |
| 2.114 | 0.461 | tINS | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n300_s47/F |
| 2.489 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n300_s42/I0 |
| 3.015 | 0.526 | tINS | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n300_s42/F |
| 3.390 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n300_s32/I2 |
| 3.851 | 0.461 | tINS | RR | 5 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n300_s32/F |
| 4.226 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n299_s28/I2 |
| 4.687 | 0.461 | tINS | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n299_s28/F |
| 5.062 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s4/I1 |
| 5.579 | 0.516 | tINS | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s4/F |
| 5.954 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s1/I1 |
| 6.090 | 0.136 | tINS | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s1/O |
| 6.465 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s0/I0 |
| 6.551 | 0.086 | tINS | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s0/O |
| 6.926 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 8.333 | 0.000 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 8.696 | 0.362 | tCL | RR | 165 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 9.071 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s0/CLK |
| 9.007 | -0.064 | tSu | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 8.333 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 2.649, 42.799%; route: 3.000, 48.475%; tC2Q: 0.540, 8.726% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:| Slack | 2.245 |
| Data Arrival Time | 6.762 |
| Data Required Time | 9.007 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_0_s1 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_1_s1 |
| Launch Clk | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 0.362 | 0.362 | tCL | RR | 165 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 0.737 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_0_s1/CLK |
| 1.120 | 0.382 | tC2Q | RR | 19 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_bit_count_0_s1/Q |
| 1.495 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n79_s2/I0 |
| 2.021 | 0.526 | tINS | RR | 10 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n79_s2/F |
| 2.396 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n120_s7/I2 |
| 2.857 | 0.461 | tINS | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n120_s7/F |
| 3.232 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n120_s5/I2 |
| 3.694 | 0.461 | tINS | RR | 2 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n120_s5/F |
| 4.069 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n120_s3/I1 |
| 4.585 | 0.516 | tINS | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n120_s3/F |
| 4.960 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n120_s1/I0 |
| 5.486 | 0.526 | tINS | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n120_s1/F |
| 5.861 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n120_s0/I0 |
| 6.387 | 0.526 | tINS | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n120_s0/F |
| 6.762 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 8.333 | 0.000 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 8.696 | 0.362 | tCL | RR | 165 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 9.071 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_1_s1/CLK |
| 9.007 | -0.064 | tSu | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 8.333 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 3.017, 50.083%; route: 2.625, 43.568%; tC2Q: 0.382, 6.349% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:| Slack | 2.313 |
| Data Arrival Time | 6.694 |
| Data Required Time | 9.007 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0 |
| Launch Clk | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 0.362 | 0.362 | tCL | RR | 165 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 0.737 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/CLK |
| 1.120 | 0.382 | tC2Q | RR | 4 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/Q |
| 1.495 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n28_s0/I0 |
| 2.021 | 0.526 | tINS | RR | 3 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n28_s0/F |
| 2.396 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_3_s4/I3 |
| 2.659 | 0.262 | tINS | RR | 6 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_3_s4/F |
| 3.034 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_4_s3/I1 |
| 3.550 | 0.516 | tINS | RR | 2 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_4_s3/F |
| 3.925 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rgraynext_2_s1/I2 |
| 4.386 | 0.461 | tINS | RR | 2 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rgraynext_2_s1/F |
| 4.761 | 0.375 | tNET | RR | 2 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n163_s0/I0 |
| 5.317 | 0.556 | tINS | RF | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n163_s0/COUT |
| 5.317 | 0.000 | tNET | FF | 2 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n164_s0/CIN |
| 5.367 | 0.050 | tINS | FR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n164_s0/COUT |
| 5.367 | 0.000 | tNET | RR | 2 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n165_s0/CIN |
| 5.418 | 0.050 | tINS | RR | 2 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n165_s0/COUT |
| 5.793 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/w_empty_s0/I0 |
| 6.319 | 0.526 | tINS | RR | 2 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/w_empty_s0/F |
| 6.694 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 8.333 | 0.000 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 8.696 | 0.362 | tCL | RR | 165 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 9.071 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0/CLK |
| 9.007 | -0.064 | tSu | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 8.333 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 2.949, 49.507%; route: 2.625, 44.071%; tC2Q: 0.382, 6.422% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:| Slack | 2.313 |
| Data Arrival Time | 6.694 |
| Data Required Time | 9.007 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_empty_s0 |
| Launch Clk | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 0.362 | 0.362 | tCL | RR | 165 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 0.737 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/CLK |
| 1.120 | 0.382 | tC2Q | RR | 4 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/Q |
| 1.495 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n28_s0/I0 |
| 2.021 | 0.526 | tINS | RR | 3 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n28_s0/F |
| 2.396 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_3_s4/I3 |
| 2.659 | 0.262 | tINS | RR | 6 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_3_s4/F |
| 3.034 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_4_s3/I1 |
| 3.550 | 0.516 | tINS | RR | 2 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_4_s3/F |
| 3.925 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rgraynext_2_s1/I2 |
| 4.386 | 0.461 | tINS | RR | 2 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rgraynext_2_s1/F |
| 4.761 | 0.375 | tNET | RR | 2 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n163_s0/I0 |
| 5.317 | 0.556 | tINS | RF | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n163_s0/COUT |
| 5.317 | 0.000 | tNET | FF | 2 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n164_s0/CIN |
| 5.367 | 0.050 | tINS | FR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n164_s0/COUT |
| 5.367 | 0.000 | tNET | RR | 2 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n165_s0/CIN |
| 5.418 | 0.050 | tINS | RR | 2 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n165_s0/COUT |
| 5.793 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/w_empty_s0/I0 |
| 6.319 | 0.526 | tINS | RR | 2 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/w_empty_s0/F |
| 6.694 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 8.333 | 0.000 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 8.696 | 0.362 | tCL | RR | 165 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 9.071 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_empty_s0/CLK |
| 9.007 | -0.064 | tSu | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 8.333 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 2.949, 49.507%; route: 2.625, 44.071%; tC2Q: 0.382, 6.422% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |