Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\USBTwoSoftPHY\data\usb2_0_softphy_top.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\USBTwoSoftPHY\data\usb2_0_softphy.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW5A-LV25UG324C2/I1
Device GW5A-25
Device Version A
Created Time Tue Jun 10 13:36:27 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module USB2_0_SoftPHY_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.37s, Peak memory usage = 81.863MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 81.863MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 81.863MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 81.863MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 81.863MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 81.863MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 81.863MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 81.863MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 81.863MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 81.863MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 81.863MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 81.863MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 109.199MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.172s, Peak memory usage = 109.199MB
Generate output files:
    CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.104s, Peak memory usage = 109.199MB
Total Time and Memory Usage CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 109.199MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 39
I/O Buf 38
    IBUF 20
    OBUF 14
    TBUF 1
    IOBUF 2
    ELVDS_IOBUF 1
Register 365
    DFFRE 23
    DFFPE 35
    DFFCE 307
LUT 894
    LUT2 113
    LUT3 287
    LUT4 494
ALU 10
    ALU 10
INV 10
    INV 10
IOLOGIC 4
    IDES8 2
    IDES16 1
    OSER16 1
BSRAM 2
    SDPB 2
CLOCK 2
    CLKDIV 1
    DHCE 1

Resource Utilization Summary

Resource Usage Utilization
Logic 914(904 LUT, 10 ALU) / 23040 4%
Register 365 / 23685 2%
  --Register as Latch 0 / 23685 0%
  --Register as FF 365 / 23685 2%
BSRAM 2 / 56 4%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 fclk_i Base 10.000 100.000 0.000 5.000 fclk_i_ibuf/I
2 clk_i Base 10.000 100.000 0.000 5.000 clk_i_ibuf/I
3 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk Generated 80.000 12.500 0.000 40.000 fclk_i_ibuf/I fclk_i usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_i 100.000(MHz) 108.909(MHz) 12 TOP
2 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk 12.500(MHz) 155.715(MHz) 8 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 0.818
Data Arrival Time 9.431
Data Required Time 10.249
From usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_0_s1
To usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_rem_ones_0_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.000 0.000 tINS RR 174 clk_i_ibuf/O
0.300 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_0_s1/CLK
0.606 0.306 tC2Q RR 16 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_0_s1/Q
0.906 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n372_s2/I0
1.327 0.421 tINS RR 8 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n372_s2/F
1.627 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n393_s6/I2
1.996 0.369 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n393_s6/F
2.296 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n393_s3/I1
2.405 0.109 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n393_s3/O
2.705 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n417_s6/I0
3.126 0.421 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n417_s6/F
3.426 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n417_s3/I1
3.535 0.109 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n417_s3/O
3.835 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n304_s9/I2
4.204 0.369 tINS RR 2 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n304_s9/F
4.504 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n304_s7/I2
4.873 0.369 tINS RR 3 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n304_s7/F
5.173 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_2_s25/I2
5.542 0.369 tINS RR 3 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_2_s25/F
5.842 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_2_s14/I1
6.255 0.413 tINS RR 3 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_2_s14/F
6.555 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n571_s9/I0
6.976 0.421 tINS RR 5 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n571_s9/F
7.276 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n570_s4/I1
7.689 0.413 tINS RR 2 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n570_s4/F
7.989 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n570_s6/I0
8.410 0.421 tINS RR 2 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n570_s6/F
8.710 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n285_s1/I0
9.131 0.421 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n285_s1/F
9.431 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_rem_ones_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.000 0.000 tINS RR 174 clk_i_ibuf/O
10.300 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_rem_ones_0_s0/CLK
10.249 -0.051 tSu 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_rem_ones_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 4.625, 50.652%; route: 4.200, 45.997%; tC2Q: 0.306, 3.351%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 2

Path Summary:
Slack 0.818
Data Arrival Time 9.431
Data Required Time 10.249
From usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_0_s1
To usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_rem_ones_2_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.000 0.000 tINS RR 174 clk_i_ibuf/O
0.300 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_0_s1/CLK
0.606 0.306 tC2Q RR 16 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_0_s1/Q
0.906 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n372_s2/I0
1.327 0.421 tINS RR 8 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n372_s2/F
1.627 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n393_s6/I2
1.996 0.369 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n393_s6/F
2.296 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n393_s3/I1
2.405 0.109 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n393_s3/O
2.705 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n417_s6/I0
3.126 0.421 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n417_s6/F
3.426 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n417_s3/I1
3.535 0.109 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n417_s3/O
3.835 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n304_s9/I2
4.204 0.369 tINS RR 2 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n304_s9/F
4.504 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n304_s7/I2
4.873 0.369 tINS RR 3 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n304_s7/F
5.173 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_2_s25/I2
5.542 0.369 tINS RR 3 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_2_s25/F
5.842 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_2_s14/I1
6.255 0.413 tINS RR 3 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_2_s14/F
6.555 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n571_s9/I0
6.976 0.421 tINS RR 5 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n571_s9/F
7.276 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n571_s4/I1
7.689 0.413 tINS RR 3 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n571_s4/F
7.989 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n284_s3/I0
8.410 0.421 tINS RR 2 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n284_s3/F
8.710 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n283_s2/I0
9.131 0.421 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n283_s2/F
9.431 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_rem_ones_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.000 0.000 tINS RR 174 clk_i_ibuf/O
10.300 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_rem_ones_2_s0/CLK
10.249 -0.051 tSu 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_rem_ones_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 4.625, 50.652%; route: 4.200, 45.997%; tC2Q: 0.306, 3.351%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 3

Path Summary:
Slack 0.826
Data Arrival Time 9.423
Data Required Time 10.249
From usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_0_s1
To usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_data_packetized_5_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.000 0.000 tINS RR 174 clk_i_ibuf/O
0.300 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_0_s1/CLK
0.606 0.306 tC2Q RR 16 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_0_s1/Q
0.906 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n372_s2/I0
1.327 0.421 tINS RR 8 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n372_s2/F
1.627 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n393_s6/I2
1.996 0.369 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n393_s6/F
2.296 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n393_s3/I1
2.405 0.109 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n393_s3/O
2.705 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n417_s6/I0
3.126 0.421 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n417_s6/F
3.426 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n417_s3/I1
3.535 0.109 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n417_s3/O
3.835 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n304_s9/I2
4.204 0.369 tINS RR 2 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n304_s9/F
4.504 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n304_s7/I2
4.873 0.369 tINS RR 3 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n304_s7/F
5.173 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_2_s25/I2
5.542 0.369 tINS RR 3 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_2_s25/F
5.842 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_2_s14/I1
6.255 0.413 tINS RR 3 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_2_s14/F
6.555 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n571_s9/I0
6.976 0.421 tINS RR 5 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n571_s9/F
7.276 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n570_s4/I1
7.689 0.413 tINS RR 2 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n570_s4/F
7.989 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n570_s6/I0
8.410 0.421 tINS RR 2 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n570_s6/F
8.710 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n570_s2/I1
9.123 0.413 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n570_s2/F
9.423 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_data_packetized_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.000 0.000 tINS RR 174 clk_i_ibuf/O
10.300 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_data_packetized_5_s0/CLK
10.249 -0.051 tSu 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_data_packetized_5_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 4.617, 50.609%; route: 4.200, 46.037%; tC2Q: 0.306, 3.354%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 4

Path Summary:
Slack 0.870
Data Arrival Time 9.379
Data Required Time 10.249
From usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_0_s1
To usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/state_0_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.000 0.000 tINS RR 174 clk_i_ibuf/O
0.300 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_0_s1/CLK
0.606 0.306 tC2Q RR 16 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_0_s1/Q
0.906 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n372_s2/I0
1.327 0.421 tINS RR 8 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n372_s2/F
1.627 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n393_s6/I2
1.996 0.369 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n393_s6/F
2.296 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n393_s3/I1
2.405 0.109 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n393_s3/O
2.705 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n417_s6/I0
3.126 0.421 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n417_s6/F
3.426 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n417_s3/I1
3.535 0.109 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n417_s3/O
3.835 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n304_s9/I2
4.204 0.369 tINS RR 2 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n304_s9/F
4.504 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n304_s7/I2
4.873 0.369 tINS RR 3 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n304_s7/F
5.173 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_2_s25/I2
5.542 0.369 tINS RR 3 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_2_s25/F
5.842 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_2_s14/I1
6.255 0.413 tINS RR 3 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_2_s14/F
6.555 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_2_s6/I1
6.968 0.413 tINS RR 4 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_2_s6/F
7.268 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n313_s1/I2
7.637 0.369 tINS RR 5 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n313_s1/F
7.937 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n748_s23/I0
8.358 0.421 tINS RR 2 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n748_s23/F
8.658 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n751_s25/I0
9.079 0.421 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n751_s25/F
9.379 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/state_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.000 0.000 tINS RR 174 clk_i_ibuf/O
10.300 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/state_0_s0/CLK
10.249 -0.051 tSu 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/state_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 4.573, 50.369%; route: 4.200, 46.261%; tC2Q: 0.306, 3.370%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 5

Path Summary:
Slack 0.870
Data Arrival Time 9.379
Data Required Time 10.249
From usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_0_s1
To usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_rem_ones_1_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.000 0.000 tINS RR 174 clk_i_ibuf/O
0.300 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_0_s1/CLK
0.606 0.306 tC2Q RR 16 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_0_s1/Q
0.906 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n372_s2/I0
1.327 0.421 tINS RR 8 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n372_s2/F
1.627 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n393_s6/I2
1.996 0.369 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n393_s6/F
2.296 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n393_s3/I1
2.405 0.109 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n393_s3/O
2.705 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n417_s6/I0
3.126 0.421 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n417_s6/F
3.426 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n417_s3/I1
3.535 0.109 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n417_s3/O
3.835 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n304_s9/I2
4.204 0.369 tINS RR 2 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n304_s9/F
4.504 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n304_s7/I2
4.873 0.369 tINS RR 3 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n304_s7/F
5.173 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_2_s25/I2
5.542 0.369 tINS RR 3 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_2_s25/F
5.842 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_2_s14/I1
6.255 0.413 tINS RR 3 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_offset_2_s14/F
6.555 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n571_s9/I0
6.976 0.421 tINS RR 5 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n571_s9/F
7.276 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n571_s4/I1
7.689 0.413 tINS RR 3 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n571_s4/F
7.989 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n284_s3/I0
8.410 0.421 tINS RR 2 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n284_s3/F
8.710 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n284_s2/I2
9.079 0.369 tINS RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n284_s2/F
9.379 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_rem_ones_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.000 0.000 tINS RR 174 clk_i_ibuf/O
10.300 0.300 tNET RR 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_rem_ones_1_s0/CLK
10.249 -0.051 tSu 1 usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_rem_ones_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 4.573, 50.369%; route: 4.200, 46.261%; tC2Q: 0.306, 3.370%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%