Timing Messages

Report Title	Timing Analysis Report
Design File	D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj25k_usb2_loopback_speed\prj25k_usb2_loopback_speed_single_lvds\project\impl\gwsynthesis\gowin_usb_refdesign.vg
Physical Constraints File	D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj25k_usb2_loopback_speed\prj25k_usb2_loopback_speed_single_lvds\project\src\usb_ref.cst
Timing Constraint File	D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj25k_usb2_loopback_speed\prj25k_usb2_loopback_speed_single_lvds\project\src\usb_ref.sdc
Tool Version	V1.9.12 (64-bit)
Part Number	GW5A-LV25UG324C1/I0
Device	GW5A-25
Device Version	A
Created Time	Wed Nov 5 09:24:24 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C C2
Hold Delay Model	Slow 0.855V 0C C2
Numbers of Paths Analyzed	10651
Numbers of Endpoints Analyzed	12164
Numbers of Falling Endpoints	4
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clk_50	Base	20.000	50.000	0.000	10.000			CLK_IN
2	clk_120	Base	8.333	120.005	0.000	4.167			u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/sclk
3	clk_60	Base	16.667	59.999	0.000	8.334			PHY_CLKOUT
4	pll0/u_pll/PLLA_inst/CLKOUT0.default_gen_clk	Generated	41.667	24.000	0.000	20.833	CLK_IN_ibuf/I	clk_50	pll0/u_pll/PLLA_inst/CLKOUT0
5	pll1/u_pll/PLLA_inst/CLKOUT1.default_gen_clk	Generated	1.042	960.000	0.000	0.521	pll0/u_pll/PLLA_inst/CLKOUT0	pll0/u_pll/PLLA_inst/CLKOUT0.default_gen_clk	pll1/u_pll/PLLA_inst/CLKOUT1

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk_50	50.000(MHz)	208.094(MHz)	7	TOP
2	clk_120	120.005(MHz)	176.928(MHz)	7	TOP
3	clk_60	59.999(MHz)	90.104(MHz)	11	TOP
4	pll0/u_pll/PLLA_inst/CLKOUT0.default_gen_clk	24.000(MHz)	298.485(MHz)	6	TOP

No timing paths to get frequency of pll1/u_pll/PLLA_inst/CLKOUT1.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk_50	Setup	0.000	0
clk_50	Hold	0.000	0
clk_120	Setup	0.000	0
clk_120	Hold	0.000	0
clk_60	Setup	0.000	0
clk_60	Hold	0.000	0
pll0/u_pll/PLLA_inst/CLKOUT0.default_gen_clk	Setup	0.000	0
pll0/u_pll/PLLA_inst/CLKOUT0.default_gen_clk	Hold	0.000	0
pll1/u_pll/PLLA_inst/CLKOUT1.default_gen_clk	Setup	0.000	0
pll1/u_pll/PLLA_inst/CLKOUT1.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	2.681	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_0_s1/CE	clk_120:[R]	clk_120:[R]	8.333	-0.001	5.404
2	3.225	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_act_s1/CE	clk_120:[R]	clk_120:[R]	8.333	-0.001	4.860
3	3.227	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_5_s0/D	clk_120:[R]	clk_120:[R]	8.333	0.000	5.055
4	3.333	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_2_s0/D	clk_120:[R]	clk_120:[R]	8.333	0.031	4.918
5	3.404	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_3_s0/CE	clk_120:[R]	clk_120:[R]	8.333	-0.025	4.705
6	3.410	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_2_s0/CE	clk_120:[R]	clk_120:[R]	8.333	-0.003	4.677
7	3.421	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_3_s0/D	clk_120:[R]	clk_120:[R]	8.333	0.044	4.817
8	3.545	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_3_s0/CE	clk_120:[R]	clk_120:[R]	8.333	0.010	4.530
9	3.567	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_4_s0/CE	clk_120:[R]	clk_120:[R]	8.333	-0.034	4.551
10	3.667	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s1/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Full_s0/D	clk_120:[R]	clk_120:[R]	8.333	0.019	4.596
11	3.721	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_6_s0/CE	clk_120:[R]	clk_120:[R]	8.333	-0.036	4.399
12	3.721	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_7_s0/CE	clk_120:[R]	clk_120:[R]	8.333	-0.036	4.399
13	3.731	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_6_s0/D	clk_120:[R]	clk_120:[R]	8.333	0.000	4.551
14	3.741	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_7_s0/D	clk_120:[R]	clk_120:[R]	8.333	0.000	4.541
15	3.817	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/D	clk_120:[R]	clk_120:[R]	8.333	0.011	4.454
16	3.853	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_1_s0/CE	clk_120:[R]	clk_120:[R]	8.333	0.005	4.226
17	3.855	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_5_s0/CE	clk_120:[R]	clk_120:[R]	8.333	-0.036	4.265
18	3.883	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_1_s0/CE	clk_120:[R]	clk_120:[R]	8.333	-0.023	4.224
19	3.886	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0/CE	clk_120:[R]	clk_120:[R]	8.333	-0.025	4.223
20	4.037	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0/CE	clk_120:[R]	clk_120:[R]	8.333	-0.011	4.058
21	4.045	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_2_s0/CE	clk_120:[R]	clk_120:[R]	8.333	-0.019	4.058
22	4.045	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_9_s0/CE	clk_120:[R]	clk_120:[R]	8.333	-0.019	4.058
23	4.069	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_4_s0/D	clk_120:[R]	clk_120:[R]	8.333	0.002	4.211
24	4.111	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s1/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_3_s0/D	clk_120:[R]	clk_120:[R]	8.333	0.029	4.142
25	4.176	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_0_s0/D	clk_120:[R]	clk_120:[R]	8.333	0.013	4.154

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.146	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_3_s0/Q	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/DI[3]	clk_60:[R]	clk_60:[R]	0.000	0.005	0.178
2	0.207	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_1_s0/Q	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/DI[1]	clk_60:[R]	clk_60:[R]	0.000	0.005	0.239
3	0.207	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/Q_6_s0/Q	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DI[2]	clk_60:[R]	clk_60:[R]	0.000	0.005	0.239
4	0.212	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_4_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/ADB[6]	clk_120:[R]	clk_120:[R]	0.000	0.008	0.239
5	0.214	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_6_s0/Q	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_1_s/DI[2]	clk_60:[R]	clk_60:[R]	0.000	0.020	0.231
6	0.215	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/rbin_num_0_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/ADB[4]	clk_60:[R]	clk_60:[R]	0.000	0.005	0.245
7	0.215	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/wp_9_s0/Q	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/ADA[11]	clk_60:[R]	clk_60:[R]	0.000	0.020	0.232
8	0.236	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/wp_2_s1/Q	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/ADA[4]	clk_60:[R]	clk_60:[R]	0.000	0.028	0.245
9	0.247	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/Q_3_s0/Q	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s/DI[3]	clk_60:[R]	clk_60:[R]	0.000	-0.002	0.286
10	0.254	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbin_0_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/ADA[3]	clk_60:[R]	clk_60:[R]	0.000	0.001	0.290
11	0.256	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/Q_1_s0/Q	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/DI[1]	clk_60:[R]	clk_60:[R]	0.000	-0.009	0.302
12	0.258	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_3_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/ADB[5]	clk_120:[R]	clk_120:[R]	0.000	0.008	0.285
13	0.259	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/ADA[5]	clk_120:[R]	clk_120:[R]	0.000	-0.007	0.302
14	0.261	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_0_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/ADA[4]	clk_120:[R]	clk_120:[R]	0.000	-0.007	0.305
15	0.263	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/rbin_num_3_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/ADB[7]	clk_60:[R]	clk_60:[R]	0.000	0.006	0.292
16	0.266	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_next_8_s0/Q	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/ADB[10]	clk_60:[R]	clk_60:[R]	0.000	0.015	0.287
17	0.269	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_next_9_s0/Q	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/ADB[11]	clk_60:[R]	clk_60:[R]	0.000	0.015	0.289
18	0.275	pll1/u_pll_init/rRomAddr_4_s1/Q	pll1/u_pll_init/rRomAddr_4_s1/D	pll0/u_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	pll0/u_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	0.000	0.000	0.300
19	0.275	pll0/u_pll_init/rReqCnt_0_s0/Q	pll0/u_pll_init/rReqCnt_0_s0/D	clk_50:[R]	clk_50:[R]	0.000	0.000	0.300
20	0.275	u_usb_uart_config/test_tx_count_3_s1/Q	u_usb_uart_config/test_tx_count_3_s1/D	clk_60:[R]	clk_60:[R]	0.000	0.000	0.300
21	0.275	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_1_s0/D	clk_60:[R]	clk_60:[R]	0.000	0.000	0.300
22	0.275	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_5_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_5_s0/D	clk_60:[R]	clk_60:[R]	0.000	0.000	0.300
23	0.275	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_8_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_8_s0/D	clk_60:[R]	clk_60:[R]	0.000	0.000	0.300
24	0.275	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_1_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_1_s0/D	clk_60:[R]	clk_60:[R]	0.000	0.000	0.300
25	0.275	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/wait_count_3_s2/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/wait_count_3_s2/D	clk_60:[R]	clk_60:[R]	0.000	0.000	0.300

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	2.160	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_2_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	-0.009	1.737
2	2.160	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_0_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	-0.009	1.737
3	2.160	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_1_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	-0.009	1.737
4	2.160	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_5_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	-0.009	1.737
5	2.160	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Full_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	-0.013	1.742
6	2.160	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_2_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	-0.013	1.742
7	2.160	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_3_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	-0.013	1.742
8	2.160	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_4_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	-0.013	1.742
9	2.160	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_5_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	-0.013	1.742
10	2.160	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_3_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	-0.013	1.742
11	2.160	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_4_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	-0.013	1.742
12	2.160	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_0_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.003	1.724
13	2.160	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_2_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.003	1.724
14	2.160	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_1_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	-0.001	1.729
15	2.167	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_4_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	-0.018	1.740
16	2.167	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_4_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	-0.018	1.740
17	2.167	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_5_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	-0.018	1.740
18	2.168	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_2_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	-0.004	1.724
19	2.168	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_3_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	-0.004	1.724
20	2.171	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_3_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	-0.020	1.737
21	2.175	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_0_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	-0.011	1.724
22	2.175	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_1_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	-0.011	1.724
23	2.175	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_1_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	-0.016	1.729
24	2.177	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_0_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	-0.036	1.748
25	2.177	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_1_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	-0.036	1.748

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.224	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/RESET	clk_60:[R]	clk_60:[R]	0.000	0.016	1.197
2	1.224	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_0_s/RESET	clk_60:[R]	clk_60:[R]	0.000	0.016	1.197
3	1.224	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/RESET	clk_60:[R]	clk_60:[R]	0.000	0.016	1.197
4	1.228	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_1_s/RESET	clk_60:[R]	clk_60:[R]	0.000	0.020	1.197
5	1.228	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/RESET	clk_60:[R]	clk_60:[R]	0.000	0.020	1.197
6	1.228	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/RESET	clk_60:[R]	clk_60:[R]	0.000	0.020	1.197
7	1.228	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s/RESET	clk_60:[R]	clk_60:[R]	0.000	0.020	1.197
8	1.228	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/RESET	clk_60:[R]	clk_60:[R]	0.000	0.020	1.197
9	1.228	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s/RESET	clk_60:[R]	clk_60:[R]	0.000	0.020	1.197
10	1.232	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/RESET	clk_60:[R]	clk_60:[R]	0.000	0.024	1.197
11	1.232	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_1_s/RESET	clk_60:[R]	clk_60:[R]	0.000	0.024	1.197
12	1.232	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s/RESET	clk_60:[R]	clk_60:[R]	0.000	0.024	1.197
13	1.262	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_0_s0/CLEAR	clk_60:[R]	clk_60:[R]	0.000	0.021	1.188
14	1.262	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_1_s0/CLEAR	clk_60:[R]	clk_60:[R]	0.000	0.021	1.188
15	1.262	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/rbin_4_s0/CLEAR	clk_60:[R]	clk_60:[R]	0.000	0.021	1.188
16	1.262	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_tx_buf_ep2/pkt_fifo_wr_num_d0_2_s0/CLEAR	clk_60:[R]	clk_60:[R]	0.000	0.021	1.188
17	1.266	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/test_rd_addr_0_s2/CLEAR	clk_60:[R]	clk_60:[R]	0.000	0.025	1.188
18	1.266	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/test_rd_addr_3_s1/CLEAR	clk_60:[R]	clk_60:[R]	0.000	0.025	1.188
19	1.266	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/s_set_len_14_s0/CLEAR	clk_60:[R]	clk_60:[R]	0.000	0.006	1.207
20	1.266	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/s_set_len_15_s0/CLEAR	clk_60:[R]	clk_60:[R]	0.000	0.006	1.207
21	1.266	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_5_s0/CLEAR	clk_60:[R]	clk_60:[R]	0.000	0.006	1.207
22	1.266	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_3_s0/CLEAR	clk_60:[R]	clk_60:[R]	0.000	0.025	1.188
23	1.266	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/rbin_1_s0/CLEAR	clk_60:[R]	clk_60:[R]	0.000	0.006	1.207
24	1.266	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/usb_tx_buf_ep2/pkt_fifo_wr_num_d0_3_s0/CLEAR	clk_60:[R]	clk_60:[R]	0.000	0.025	1.188
25	1.266	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	usb_fifo/s_usb_txlen_6_s1/CLEAR	clk_60:[R]	clk_60:[R]	0.000	0.025	1.188

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	2.570	3.432	0.862	Low Pulse Width	clk_120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s
2	2.570	3.432	0.862	Low Pulse Width	clk_120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s
3	2.573	3.435	0.862	High Pulse Width	clk_120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s
4	2.573	3.435	0.862	High Pulse Width	clk_120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s
5	3.223	3.423	0.200	Low Pulse Width	clk_120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_0_s0
6	3.223	3.423	0.200	Low Pulse Width	clk_120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_0_s0
7	3.223	3.423	0.200	Low Pulse Width	clk_120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_3_s0
8	3.223	3.423	0.200	Low Pulse Width	clk_120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_2_s0
9	3.224	3.424	0.200	Low Pulse Width	clk_120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_4_s0
10	3.224	3.424	0.200	Low Pulse Width	clk_120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_4_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	2.681
Data Arrival Time	6.941
Data Required Time	9.623
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_0_s1
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.537	1.537	tNET	RR	1	R29C41[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0/CLK
1.843	0.306	tC2Q	RR	18	R29C41[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0/Q
2.703	0.860	tNET	RR	1	R26C38[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n668_s11/I0
3.101	0.398	tINS	RR	4	R26C38[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n668_s11/F
3.107	0.006	tNET	RR	1	R26C38[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n668_s20/I2
3.439	0.332	tINS	RR	8	R26C38[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n668_s20/F
3.755	0.316	tNET	RR	1	R25C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n443_s3/I0
4.176	0.421	tINS	RR	2	R25C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n443_s3/F
4.477	0.300	tNET	RR	1	R25C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s8/I1
4.890	0.413	tINS	RR	2	R25C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s8/F
5.017	0.128	tNET	RR	1	R26C37[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n3096_s1/I3
5.434	0.417	tINS	RR	4	R26C37[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n3096_s1/F
6.063	0.629	tNET	RR	1	R33C37[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_0_s3/I0
6.461	0.398	tINS	RR	1	R33C37[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_0_s3/F
6.941	0.480	tNET	RR	1	R33C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_0_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.872	1.539	tNET	RR	1	R33C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_0_s1/CLK
9.623	-0.249	tSu		1	R33C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_0_s1

Path Statistics:

Clock Skew	0.001
Setup Relationship	8.333
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.537, 100.000%
Arrival Data Path Delay	cell: 2.379, 44.023%; route: 2.719, 50.315%; tC2Q: 0.306, 5.662%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.539, 100.000%

Path2

Path Summary:

Slack	3.225
Data Arrival Time	6.397
Data Required Time	9.623
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_act_s1
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.537	1.537	tNET	RR	1	R29C41[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0/CLK
1.843	0.306	tC2Q	RR	18	R29C41[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0/Q
2.703	0.860	tNET	RR	1	R26C38[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n668_s11/I0
3.101	0.398	tINS	RR	4	R26C38[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n668_s11/F
3.107	0.006	tNET	RR	1	R26C38[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n668_s20/I2
3.439	0.332	tINS	RR	8	R26C38[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n668_s20/F
3.755	0.316	tNET	RR	1	R25C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n443_s3/I0
4.176	0.421	tINS	RR	2	R25C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n443_s3/F
4.477	0.300	tNET	RR	1	R25C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s8/I1
4.890	0.413	tINS	RR	2	R25C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s8/F
5.017	0.128	tNET	RR	1	R26C37[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n3096_s1/I3
5.434	0.417	tINS	RR	4	R26C37[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n3096_s1/F
5.955	0.521	tNET	RR	1	R33C37[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_act_s4/I0
6.287	0.332	tINS	RR	1	R33C37[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_act_s4/F
6.397	0.110	tNET	RR	1	R33C37[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_act_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.872	1.539	tNET	RR	1	R33C37[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_act_s1/CLK
9.623	-0.249	tSu		1	R33C37[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_act_s1

Path Statistics:

Clock Skew	0.001
Setup Relationship	8.333
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.537, 100.000%
Arrival Data Path Delay	cell: 2.313, 47.593%; route: 2.241, 46.111%; tC2Q: 0.306, 6.296%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.539, 100.000%

Path3

Path Summary:

Slack	3.227
Data Arrival Time	6.617
Data Required Time	9.845
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_5_s0
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.562	1.562	tNET	RR	1	R24C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0/CLK
1.868	0.306	tC2Q	RR	12	R24C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0/Q
2.736	0.867	tNET	RR	1	R29C42[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2199_s11/I3
3.153	0.417	tINS	RR	20	R29C42[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2199_s11/F
4.204	1.051	tNET	RR	1	R25C37[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2201_s6/I2
4.621	0.417	tINS	RR	1	R25C37[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2201_s6/F
4.621	0.000	tNET	RR	1	R25C37[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2201_s4/I0
4.729	0.109	tINS	RR	1	R25C37[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2201_s4/O
4.883	0.154	tNET	RR	1	R24C37[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1645_s9/I1
5.252	0.369	tINS	RR	1	R24C37[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1645_s9/F
5.254	0.002	tNET	RR	1	R24C37[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1645_s5/I0
5.671	0.417	tINS	RR	1	R24C37[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1645_s5/F
5.673	0.002	tNET	RR	1	R24C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1645_s3/I0
6.094	0.421	tINS	RR	1	R24C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1645_s3/F
6.204	0.110	tNET	RR	1	R24C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1645_s10/I1
6.617	0.413	tINS	RR	1	R24C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1645_s10/F
6.617	0.000	tNET	RR	1	R24C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.896	1.562	tNET	RR	1	R24C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_5_s0/CLK
9.845	-0.051	tSu		1	R24C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.562, 100.000%
Arrival Data Path Delay	cell: 2.563, 50.702%; route: 2.186, 43.244%; tC2Q: 0.306, 6.053%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.562, 100.000%

Path4

Path Summary:

Slack	3.333
Data Arrival Time	6.478
Data Required Time	9.811
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_2_s0
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.560	1.560	tNET	RR	1	R25C39[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_1_s0/CLK
1.854	0.294	tC2Q	RF	18	R25C39[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_1_s0/Q
2.353	0.499	tNET	FF	1	R26C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2164_s3/I1
2.774	0.421	tINS	FR	10	R26C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2164_s3/F
3.521	0.747	tNET	RR	1	R30C38[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2185_s8/I2
3.938	0.417	tINS	RR	2	R30C38[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2185_s8/F
4.216	0.278	tNET	RR	1	R30C41[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2768_s17/I3
4.585	0.369	tINS	RR	1	R30C41[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2768_s17/F
4.587	0.002	tNET	RR	1	R30C41[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2768_s14/I0
5.000	0.413	tINS	RR	1	R30C41[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2768_s14/F
5.110	0.110	tNET	RR	1	R30C41[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2768_s10/I2
5.531	0.421	tINS	RR	1	R30C41[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2768_s10/F
5.657	0.126	tNET	RR	1	R31C41[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2768_s8/I0
6.056	0.398	tINS	RR	1	R31C41[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2768_s8/F
6.057	0.002	tNET	RR	1	R31C41[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2768_s7/I0
6.478	0.421	tINS	RR	1	R31C41[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2768_s7/F
6.478	0.000	tNET	RR	1	R31C41[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.862	1.529	tNET	RR	1	R31C41[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_2_s0/CLK
9.811	-0.051	tSu		1	R31C41[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_2_s0

Path Statistics:

Clock Skew	-0.031
Setup Relationship	8.333
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.560, 100.000%
Arrival Data Path Delay	cell: 2.860, 58.154%; route: 1.764, 35.868%; tC2Q: 0.294, 5.978%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.529, 100.000%

Path5

Path Summary:

Slack	3.404
Data Arrival Time	6.242
Data Required Time	9.647
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_3_s0
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.537	1.537	tNET	RR	1	R29C41[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0/CLK
1.843	0.306	tC2Q	RR	18	R29C41[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0/Q
2.703	0.860	tNET	RR	1	R26C38[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n668_s11/I0
3.101	0.398	tINS	RR	4	R26C38[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n668_s11/F
3.107	0.006	tNET	RR	1	R26C38[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n668_s20/I2
3.439	0.332	tINS	RR	8	R26C38[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n668_s20/F
3.755	0.316	tNET	RR	1	R25C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n443_s3/I0
4.176	0.421	tINS	RR	2	R25C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n443_s3/F
4.477	0.300	tNET	RR	1	R25C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s8/I1
4.890	0.413	tINS	RR	2	R25C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s8/F
5.017	0.128	tNET	RR	1	R26C37[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n3096_s1/I3
5.434	0.417	tINS	RR	4	R26C37[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n3096_s1/F
5.734	0.300	tNET	RR	1	R24C38[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_3_s3/I0
5.944	0.210	tINS	RR	1	R24C38[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_3_s3/F
6.242	0.298	tNET	RR	1	R24C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_3_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.896	1.562	tNET	RR	1	R24C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_3_s0/CLK
9.647	-0.249	tSu		1	R24C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_3_s0

Path Statistics:

Clock Skew	0.025
Setup Relationship	8.333
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.537, 100.000%
Arrival Data Path Delay	cell: 2.191, 46.567%; route: 2.208, 46.929%; tC2Q: 0.306, 6.504%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.562, 100.000%

Path6

Path Summary:

Slack	3.410
Data Arrival Time	6.203
Data Required Time	9.613
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_2_s0
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.526	1.526	tNET	RR	1	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/CLK
1.832	0.306	tC2Q	RR	19	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/Q
3.062	1.230	tNET	RR	1	R25C36[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n5247_s0/I0
3.431	0.369	tINS	RR	3	R25C36[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n5247_s0/F
3.733	0.302	tNET	RR	1	R25C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s5/I2
4.102	0.369	tINS	RR	5	R25C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s5/F
4.236	0.134	tNET	RR	1	R24C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_1_s11/I3
4.657	0.421	tINS	RR	3	R24C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_1_s11/F
5.512	0.855	tNET	RR	1	R29C41[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_2_s9/I1
5.925	0.413	tINS	RR	1	R29C41[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_2_s9/F
6.203	0.278	tNET	RR	1	R31C41[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.862	1.529	tNET	RR	1	R31C41[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_2_s0/CLK
9.613	-0.249	tSu		1	R31C41[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_2_s0

Path Statistics:

Clock Skew	0.003
Setup Relationship	8.333
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.526, 100.000%
Arrival Data Path Delay	cell: 1.572, 33.611%; route: 2.799, 59.846%; tC2Q: 0.306, 6.543%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.529, 100.000%

Path7

Path Summary:

Slack	3.421
Data Arrival Time	6.377
Data Required Time	9.799
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_3_s0
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.560	1.560	tNET	RR	1	R25C39[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_1_s0/CLK
1.854	0.294	tC2Q	RF	18	R25C39[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_1_s0/Q
2.353	0.499	tNET	FF	1	R26C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2164_s3/I1
2.774	0.421	tINS	FR	10	R26C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2164_s3/F
3.521	0.747	tNET	RR	1	R30C38[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2185_s8/I2
3.938	0.417	tINS	RR	2	R30C38[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2185_s8/F
4.084	0.146	tNET	RR	1	R30C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2428_s10/I2
4.273	0.188	tINS	RF	1	R30C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2428_s10/F
4.273	0.000	tNET	FF	1	R30C37[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2428_s6/I1
4.430	0.157	tINS	FF	1	R30C37[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2428_s6/O
4.731	0.301	tNET	FF	1	R30C37[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1647_s10/I1
5.062	0.332	tINS	FR	1	R30C37[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1647_s10/F
5.064	0.002	tNET	RR	1	R30C37[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1647_s6/I0
5.462	0.398	tINS	RR	1	R30C37[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1647_s6/F
5.608	0.146	tNET	RR	1	R30C38[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1647_s4/I0
6.006	0.398	tINS	RR	1	R30C38[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1647_s4/F
6.008	0.002	tNET	RR	1	R30C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1647_s1/I2
6.377	0.369	tINS	RR	1	R30C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1647_s1/F
6.377	0.000	tNET	RR	1	R30C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.850	1.517	tNET	RR	1	R30C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_3_s0/CLK
9.799	-0.051	tSu		1	R30C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_3_s0

Path Statistics:

Clock Skew	-0.044
Setup Relationship	8.333
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.560, 100.000%
Arrival Data Path Delay	cell: 2.680, 55.636%; route: 1.843, 38.260%; tC2Q: 0.294, 6.103%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.517, 100.000%

Path8

Path Summary:

Slack	3.545
Data Arrival Time	6.056
Data Required Time	9.601
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_3_s0
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.526	1.526	tNET	RR	1	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/CLK
1.832	0.306	tC2Q	RR	19	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/Q
3.062	1.230	tNET	RR	1	R25C36[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n5247_s0/I0
3.431	0.369	tINS	RR	3	R25C36[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n5247_s0/F
3.733	0.302	tNET	RR	1	R25C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s5/I2
4.102	0.369	tINS	RR	5	R25C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s5/F
4.236	0.134	tNET	RR	1	R24C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_1_s11/I3
4.657	0.421	tINS	RR	3	R24C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_1_s11/F
4.661	0.004	tNET	RR	1	R24C38[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_2_s7/I1
5.074	0.413	tINS	RR	1	R24C38[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_2_s7/F
5.076	0.002	tNET	RR	1	R24C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_7_s6/I3
5.489	0.413	tINS	RR	5	R24C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_7_s6/F
6.056	0.567	tNET	RR	1	R30C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_3_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.850	1.517	tNET	RR	1	R30C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_3_s0/CLK
9.601	-0.249	tSu		1	R30C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_3_s0

Path Statistics:

Clock Skew	-0.010
Setup Relationship	8.333
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.526, 100.000%
Arrival Data Path Delay	cell: 1.985, 43.819%; route: 2.239, 49.426%; tC2Q: 0.306, 6.755%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.517, 100.000%

Path9

Path Summary:

Slack	3.567
Data Arrival Time	6.077
Data Required Time	9.645
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_4_s0
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.526	1.526	tNET	RR	1	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/CLK
1.832	0.306	tC2Q	RR	19	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/Q
3.062	1.230	tNET	RR	1	R25C36[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n5247_s0/I0
3.431	0.369	tINS	RR	3	R25C36[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n5247_s0/F
3.733	0.302	tNET	RR	1	R25C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s5/I2
4.102	0.369	tINS	RR	5	R25C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s5/F
4.236	0.134	tNET	RR	1	R24C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_1_s11/I3
4.657	0.421	tINS	RR	3	R24C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_1_s11/F
4.661	0.004	tNET	RR	1	R24C38[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_2_s7/I1
5.074	0.413	tINS	RR	1	R24C38[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_2_s7/F
5.076	0.002	tNET	RR	1	R24C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_7_s6/I3
5.489	0.413	tINS	RR	5	R24C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_7_s6/F
6.077	0.588	tNET	RR	1	R25C41[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_4_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.894	1.560	tNET	RR	1	R25C41[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_4_s0/CLK
9.645	-0.249	tSu		1	R25C41[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_4_s0

Path Statistics:

Clock Skew	0.034
Setup Relationship	8.333
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.526, 100.000%
Arrival Data Path Delay	cell: 1.985, 43.617%; route: 2.260, 49.659%; tC2Q: 0.306, 6.724%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.560, 100.000%

Path10

Path Summary:

Slack	3.667
Data Arrival Time	6.156
Data Required Time	9.823
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s1
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Full_s0
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.560	1.560	tNET	RR	1	R25C37[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s1/CLK
1.866	0.306	tC2Q	RR	2	R25C37[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s1/Q
2.929	1.063	tNET	RR	1	R29C44[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/n24_s1/I2
3.139	0.210	tINS	RR	6	R29C44[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/n24_s1/F
3.563	0.424	tNET	RR	1	R31C45[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbinnext_1_s3/I1
3.977	0.413	tINS	RR	3	R31C45[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbinnext_1_s3/F
3.980	0.004	tNET	RR	1	R31C45[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wgraynext_0_s1/I2
4.393	0.413	tINS	RR	2	R31C45[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wgraynext_0_s1/F
4.674	0.280	tNET	RR	1	R32C44[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/wfull_val_s3/I1
5.090	0.417	tINS	RR	1	R32C44[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/wfull_val_s3/F
5.244	0.154	tNET	RR	1	R33C44[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/wfull_val_s1/I3
5.661	0.417	tINS	RR	1	R33C44[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/wfull_val_s1/F
5.787	0.126	tNET	RR	1	R32C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/wfull_val_s0/I2
6.156	0.369	tINS	RR	1	R32C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/wfull_val_s0/F
6.156	0.000	tNET	RR	1	R32C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Full_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.874	1.541	tNET	RR	1	R32C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Full_s0/CLK
9.823	-0.051	tSu		1	R32C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Full_s0

Path Statistics:

Clock Skew	-0.019
Setup Relationship	8.333
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.560, 100.000%
Arrival Data Path Delay	cell: 2.239, 48.716%; route: 2.051, 44.626%; tC2Q: 0.306, 6.658%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.541, 100.000%

Path11

Path Summary:

Slack	3.721
Data Arrival Time	5.925
Data Required Time	9.647
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_6_s0
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.526	1.526	tNET	RR	1	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/CLK
1.832	0.306	tC2Q	RR	19	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/Q
3.062	1.230	tNET	RR	1	R25C36[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n5247_s0/I0
3.431	0.369	tINS	RR	3	R25C36[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n5247_s0/F
3.733	0.302	tNET	RR	1	R25C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s5/I2
4.102	0.369	tINS	RR	5	R25C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s5/F
4.236	0.134	tNET	RR	1	R24C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_1_s11/I3
4.657	0.421	tINS	RR	3	R24C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_1_s11/F
4.661	0.004	tNET	RR	1	R24C38[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_2_s7/I1
5.074	0.413	tINS	RR	1	R24C38[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_2_s7/F
5.076	0.002	tNET	RR	1	R24C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_7_s6/I3
5.489	0.413	tINS	RR	5	R24C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_7_s6/F
5.925	0.436	tNET	RR	1	R24C41[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.896	1.562	tNET	RR	1	R24C41[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_6_s0/CLK
9.647	-0.249	tSu		1	R24C41[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_6_s0

Path Statistics:

Clock Skew	0.036
Setup Relationship	8.333
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.526, 100.000%
Arrival Data Path Delay	cell: 1.985, 45.124%; route: 2.108, 47.920%; tC2Q: 0.306, 6.956%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.562, 100.000%

Path12

Path Summary:

Slack	3.721
Data Arrival Time	5.925
Data Required Time	9.647
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_7_s0
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.526	1.526	tNET	RR	1	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/CLK
1.832	0.306	tC2Q	RR	19	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/Q
3.062	1.230	tNET	RR	1	R25C36[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n5247_s0/I0
3.431	0.369	tINS	RR	3	R25C36[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n5247_s0/F
3.733	0.302	tNET	RR	1	R25C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s5/I2
4.102	0.369	tINS	RR	5	R25C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s5/F
4.236	0.134	tNET	RR	1	R24C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_1_s11/I3
4.657	0.421	tINS	RR	3	R24C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_1_s11/F
4.661	0.004	tNET	RR	1	R24C38[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_2_s7/I1
5.074	0.413	tINS	RR	1	R24C38[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_2_s7/F
5.076	0.002	tNET	RR	1	R24C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_7_s6/I3
5.489	0.413	tINS	RR	5	R24C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_7_s6/F
5.925	0.436	tNET	RR	1	R24C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_7_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.896	1.562	tNET	RR	1	R24C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_7_s0/CLK
9.647	-0.249	tSu		1	R24C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_7_s0

Path Statistics:

Clock Skew	0.036
Setup Relationship	8.333
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.526, 100.000%
Arrival Data Path Delay	cell: 1.985, 45.124%; route: 2.108, 47.920%; tC2Q: 0.306, 6.956%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.562, 100.000%

Path13

Path Summary:

Slack	3.731
Data Arrival Time	6.113
Data Required Time	9.845
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_6_s0
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.562	1.562	tNET	RR	1	R24C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0/CLK
1.868	0.306	tC2Q	RR	12	R24C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0/Q
2.736	0.867	tNET	RR	1	R29C42[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1400_s3/I3
3.153	0.417	tINS	RR	19	R29C42[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1400_s3/F
3.723	0.570	tNET	RR	1	R24C42[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1644_s8/I2
4.144	0.421	tINS	RR	1	R24C42[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1644_s8/F
4.146	0.002	tNET	RR	1	R24C42[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1644_s6/I0
4.567	0.421	tINS	RR	2	R24C42[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1644_s6/F
4.694	0.128	tNET	RR	1	R24C41[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1644_s9/I0
5.115	0.421	tINS	RR	1	R24C41[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1644_s9/F
5.117	0.002	tNET	RR	1	R24C41[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1644_s5/I0
5.327	0.210	tINS	RR	1	R24C41[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1644_s5/F
5.329	0.002	tNET	RR	1	R24C41[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1644_s3/I0
5.742	0.413	tINS	RR	1	R24C41[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1644_s3/F
5.744	0.002	tNET	RR	1	R24C41[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1644_s10/I1
6.113	0.369	tINS	RR	1	R24C41[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1644_s10/F
6.113	0.000	tNET	RR	1	R24C41[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.896	1.562	tNET	RR	1	R24C41[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_6_s0/CLK
9.845	-0.051	tSu		1	R24C41[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.562, 100.000%
Arrival Data Path Delay	cell: 2.672, 58.712%; route: 1.573, 34.564%; tC2Q: 0.306, 6.724%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.562, 100.000%

Path14

Path Summary:

Slack	3.741
Data Arrival Time	6.103
Data Required Time	9.845
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_7_s0
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.562	1.562	tNET	RR	1	R24C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0/CLK
1.868	0.306	tC2Q	RR	12	R24C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0/Q
2.736	0.867	tNET	RR	1	R29C42[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2199_s11/I3
3.153	0.417	tINS	RR	20	R29C42[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2199_s11/F
3.764	0.611	tNET	RR	1	R25C42[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2199_s12/I2
4.133	0.369	tINS	RR	1	R25C42[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2199_s12/F
4.133	0.000	tNET	RR	1	R25C42[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2199_s4/I0
4.241	0.109	tINS	RR	1	R25C42[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2199_s4/O
4.519	0.278	tNET	RR	1	R24C41[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1643_s9/I1
4.932	0.413	tINS	RR	1	R24C41[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1643_s9/F
4.934	0.002	tNET	RR	1	R24C41[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1643_s4/I0
5.332	0.398	tINS	RR	1	R24C41[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1643_s4/F
5.334	0.002	tNET	RR	1	R24C41[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1643_s2/I0
5.732	0.398	tINS	RR	1	R24C41[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1643_s2/F
5.734	0.002	tNET	RR	1	R24C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1643_s10/I0
6.103	0.369	tINS	RR	1	R24C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1643_s10/F
6.103	0.000	tNET	RR	1	R24C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.896	1.562	tNET	RR	1	R24C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_7_s0/CLK
9.845	-0.051	tSu		1	R24C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.562, 100.000%
Arrival Data Path Delay	cell: 2.473, 54.459%; route: 1.762, 38.802%; tC2Q: 0.306, 6.739%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.562, 100.000%

Path15

Path Summary:

Slack	3.817
Data Arrival Time	5.991
Data Required Time	9.808
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.537	1.537	tNET	RR	1	R29C41[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0/CLK
1.843	0.306	tC2Q	RR	18	R29C41[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0/Q
2.703	0.860	tNET	RR	1	R26C38[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n668_s11/I0
3.101	0.398	tINS	RR	4	R26C38[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n668_s11/F
3.107	0.006	tNET	RR	1	R26C38[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n668_s20/I2
3.439	0.332	tINS	RR	8	R26C38[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n668_s20/F
3.755	0.316	tNET	RR	1	R25C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n443_s3/I0
4.176	0.421	tINS	RR	2	R25C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n443_s3/F
4.477	0.300	tNET	RR	1	R25C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s8/I1
4.890	0.413	tINS	RR	2	R25C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s8/F
5.017	0.128	tNET	RR	1	R26C37[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n3096_s1/I3
5.434	0.417	tINS	RR	4	R26C37[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n3096_s1/F
5.781	0.347	tNET	RR	1	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n3096_s0/I0
5.991	0.210	tINS	RR	1	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n3096_s0/F
5.991	0.000	tNET	RR	1	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.859	1.526	tNET	RR	1	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/CLK
9.808	-0.051	tSu		1	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	8.333
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.537, 100.000%
Arrival Data Path Delay	cell: 2.191, 49.192%; route: 1.957, 43.938%; tC2Q: 0.306, 6.870%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.526, 100.000%

Path16

Path Summary:

Slack	3.853
Data Arrival Time	5.752
Data Required Time	9.606
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_1_s0
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.526	1.526	tNET	RR	1	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/CLK
1.832	0.306	tC2Q	RR	19	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/Q
3.062	1.230	tNET	RR	1	R25C36[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n5247_s0/I0
3.431	0.369	tINS	RR	3	R25C36[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n5247_s0/F
3.733	0.302	tNET	RR	1	R25C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s5/I2
4.102	0.369	tINS	RR	5	R25C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s5/F
4.232	0.130	tNET	RR	1	R24C38[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_1_s4/I1
4.653	0.421	tINS	RR	14	R24C38[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_1_s4/F
5.752	1.099	tNET	RR	1	R31C38[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.854	1.521	tNET	RR	1	R31C38[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_1_s0/CLK
9.606	-0.249	tSu		1	R31C38[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_1_s0

Path Statistics:

Clock Skew	-0.005
Setup Relationship	8.333
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.526, 100.000%
Arrival Data Path Delay	cell: 1.159, 27.425%; route: 2.761, 65.334%; tC2Q: 0.306, 7.241%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.521, 100.000%

Path17

Path Summary:

Slack	3.855
Data Arrival Time	5.791
Data Required Time	9.647
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_5_s0
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.526	1.526	tNET	RR	1	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/CLK
1.832	0.306	tC2Q	RR	19	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/Q
3.062	1.230	tNET	RR	1	R25C36[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n5247_s0/I0
3.431	0.369	tINS	RR	3	R25C36[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n5247_s0/F
3.733	0.302	tNET	RR	1	R25C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s5/I2
4.102	0.369	tINS	RR	5	R25C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s5/F
4.236	0.134	tNET	RR	1	R24C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_1_s11/I3
4.657	0.421	tINS	RR	3	R24C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_1_s11/F
4.661	0.004	tNET	RR	1	R24C38[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_2_s7/I1
5.074	0.413	tINS	RR	1	R24C38[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_2_s7/F
5.076	0.002	tNET	RR	1	R24C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_7_s6/I3
5.489	0.413	tINS	RR	5	R24C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_7_s6/F
5.791	0.302	tNET	RR	1	R24C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_5_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.896	1.562	tNET	RR	1	R24C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_5_s0/CLK
9.647	-0.249	tSu		1	R24C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_5_s0

Path Statistics:

Clock Skew	0.036
Setup Relationship	8.333
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.526, 100.000%
Arrival Data Path Delay	cell: 1.985, 46.542%; route: 1.974, 46.284%; tC2Q: 0.306, 7.175%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.562, 100.000%

Path18

Path Summary:

Slack	3.883
Data Arrival Time	5.750
Data Required Time	9.633
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_1_s0
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.526	1.526	tNET	RR	1	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/CLK
1.832	0.306	tC2Q	RR	19	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/Q
3.062	1.230	tNET	RR	1	R25C36[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n5247_s0/I0
3.431	0.369	tINS	RR	3	R25C36[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n5247_s0/F
3.733	0.302	tNET	RR	1	R25C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s5/I2
4.102	0.369	tINS	RR	5	R25C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s5/F
4.236	0.134	tNET	RR	1	R24C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_1_s11/I3
4.657	0.421	tINS	RR	3	R24C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_1_s11/F
5.227	0.570	tNET	RR	1	R27C40[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_1_s7/I3
5.596	0.369	tINS	RR	1	R27C40[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_1_s7/F
5.750	0.154	tNET	RR	1	R27C41[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.882	1.549	tNET	RR	1	R27C41[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_1_s0/CLK
9.633	-0.249	tSu		1	R27C41[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_1_s0

Path Statistics:

Clock Skew	0.023
Setup Relationship	8.333
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.526, 100.000%
Arrival Data Path Delay	cell: 1.528, 36.174%; route: 2.390, 56.581%; tC2Q: 0.306, 7.244%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.549, 100.000%

Path19

Path Summary:

Slack	3.886
Data Arrival Time	5.760
Data Required Time	9.647
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.537	1.537	tNET	RR	1	R29C41[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0/CLK
1.843	0.306	tC2Q	RR	18	R29C41[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0/Q
2.703	0.860	tNET	RR	1	R26C38[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n668_s11/I0
3.101	0.398	tINS	RR	4	R26C38[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n668_s11/F
3.107	0.006	tNET	RR	1	R26C38[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n668_s20/I2
3.439	0.332	tINS	RR	8	R26C38[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n668_s20/F
3.755	0.316	tNET	RR	1	R25C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n443_s3/I0
4.176	0.421	tINS	RR	2	R25C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n443_s3/F
4.477	0.300	tNET	RR	1	R25C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s8/I1
4.890	0.413	tINS	RR	2	R25C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s8/F
5.017	0.128	tNET	RR	1	R26C37[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s5/I1
5.434	0.417	tINS	RR	1	R26C37[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s5/F
5.760	0.326	tNET	RR	1	R24C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.896	1.562	tNET	RR	1	R24C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0/CLK
9.647	-0.249	tSu		1	R24C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0

Path Statistics:

Clock Skew	0.025
Setup Relationship	8.333
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.537, 100.000%
Arrival Data Path Delay	cell: 1.981, 46.910%; route: 1.936, 45.844%; tC2Q: 0.306, 7.246%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.562, 100.000%

Path20

Path Summary:

Slack	4.037
Data Arrival Time	5.584
Data Required Time	9.622
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.526	1.526	tNET	RR	1	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/CLK
1.832	0.306	tC2Q	RR	19	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/Q
3.062	1.230	tNET	RR	1	R25C36[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n5247_s0/I0
3.431	0.369	tINS	RR	3	R25C36[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n5247_s0/F
3.733	0.302	tNET	RR	1	R25C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s5/I2
4.102	0.369	tINS	RR	5	R25C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s5/F
4.232	0.130	tNET	RR	1	R24C38[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_1_s4/I1
4.653	0.421	tINS	RR	14	R24C38[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_1_s4/F
5.584	0.931	tNET	RR	1	R29C41[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.871	1.537	tNET	RR	1	R29C41[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0/CLK
9.622	-0.249	tSu		1	R29C41[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_0_s0

Path Statistics:

Clock Skew	0.011
Setup Relationship	8.333
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.526, 100.000%
Arrival Data Path Delay	cell: 1.159, 28.561%; route: 2.593, 63.898%; tC2Q: 0.306, 7.541%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.537, 100.000%

Path21

Path Summary:

Slack	4.045
Data Arrival Time	5.584
Data Required Time	9.629
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_2_s0
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.526	1.526	tNET	RR	1	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/CLK
1.832	0.306	tC2Q	RR	19	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/Q
3.062	1.230	tNET	RR	1	R25C36[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n5247_s0/I0
3.431	0.369	tINS	RR	3	R25C36[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n5247_s0/F
3.733	0.302	tNET	RR	1	R25C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s5/I2
4.102	0.369	tINS	RR	5	R25C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s5/F
4.232	0.130	tNET	RR	1	R24C38[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_1_s4/I1
4.653	0.421	tINS	RR	14	R24C38[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_1_s4/F
5.584	0.931	tNET	RR	1	R29C40[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.878	1.545	tNET	RR	1	R29C40[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_2_s0/CLK
9.629	-0.249	tSu		1	R29C40[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_2_s0

Path Statistics:

Clock Skew	0.019
Setup Relationship	8.333
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.526, 100.000%
Arrival Data Path Delay	cell: 1.159, 28.561%; route: 2.593, 63.898%; tC2Q: 0.306, 7.541%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.545, 100.000%

Path22

Path Summary:

Slack	4.045
Data Arrival Time	5.584
Data Required Time	9.629
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_9_s0
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.526	1.526	tNET	RR	1	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/CLK
1.832	0.306	tC2Q	RR	19	R32C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_1_s0/Q
3.062	1.230	tNET	RR	1	R25C36[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n5247_s0/I0
3.431	0.369	tINS	RR	3	R25C36[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n5247_s0/F
3.733	0.302	tNET	RR	1	R25C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s5/I2
4.102	0.369	tINS	RR	5	R25C38[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s5/F
4.232	0.130	tNET	RR	1	R24C38[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_1_s4/I1
4.653	0.421	tINS	RR	14	R24C38[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_1_s4/F
5.584	0.931	tNET	RR	1	R29C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_9_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.878	1.545	tNET	RR	1	R29C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_9_s0/CLK
9.629	-0.249	tSu		1	R29C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_data_dly_9_s0

Path Statistics:

Clock Skew	0.019
Setup Relationship	8.333
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.526, 100.000%
Arrival Data Path Delay	cell: 1.159, 28.561%; route: 2.593, 63.898%; tC2Q: 0.306, 7.541%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.545, 100.000%

Path23

Path Summary:

Slack	4.069
Data Arrival Time	5.773
Data Required Time	9.843
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_4_s0
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.562	1.562	tNET	RR	1	R24C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0/CLK
1.868	0.306	tC2Q	RR	12	R24C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0/Q
2.736	0.867	tNET	RR	1	R29C42[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1400_s3/I3
3.153	0.417	tINS	RR	19	R29C42[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1400_s3/F
3.565	0.412	tNET	RR	1	R25C42[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1646_s8/I2
3.775	0.210	tINS	RR	1	R25C42[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1646_s8/F
3.777	0.002	tNET	RR	1	R25C42[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1646_s6/I0
4.190	0.413	tINS	RR	2	R25C42[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1646_s6/F
4.318	0.128	tNET	RR	1	R25C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1646_s9/I0
4.731	0.413	tINS	RR	1	R25C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1646_s9/F
4.857	0.126	tNET	RR	1	R25C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1646_s5/I0
5.067	0.210	tINS	RR	1	R25C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1646_s5/F
5.069	0.002	tNET	RR	1	R25C40[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1646_s3/I0
5.279	0.210	tINS	RR	1	R25C40[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1646_s3/F
5.405	0.126	tNET	RR	1	R25C41[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1646_s10/I1
5.773	0.369	tINS	RR	1	R25C41[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1646_s10/F
5.773	0.000	tNET	RR	1	R25C41[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.894	1.560	tNET	RR	1	R25C41[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_4_s0/CLK
9.843	-0.051	tSu		1	R25C41[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_4_s0

Path Statistics:

Clock Skew	-0.002
Setup Relationship	8.333
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.562, 100.000%
Arrival Data Path Delay	cell: 2.242, 53.242%; route: 1.663, 39.492%; tC2Q: 0.306, 7.267%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.560, 100.000%

Path24

Path Summary:

Slack	4.111
Data Arrival Time	5.702
Data Required Time	9.814
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s1
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_3_s0
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.560	1.560	tNET	RR	1	R25C37[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s1/CLK
1.866	0.306	tC2Q	RR	2	R25C37[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/de_eop_s1/Q
2.929	1.063	tNET	RR	1	R29C44[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/n24_s1/I2
3.139	0.210	tINS	RR	6	R29C44[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/n24_s1/F
3.563	0.424	tNET	RR	1	R31C45[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbinnext_2_s4/I3
3.977	0.413	tINS	RR	7	R31C45[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbinnext_2_s4/F
4.375	0.398	tNET	RR	1	R33C44[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbinnext_4_s3/I1
4.788	0.413	tINS	RR	3	R33C44[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbinnext_4_s3/F
4.792	0.004	tNET	RR	1	R33C44[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wgraynext_3_s1/I2
5.213	0.421	tINS	RR	2	R33C44[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wgraynext_3_s1/F
5.703	0.490	tNET	RR	1	R30C44[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.865	1.532	tNET	RR	1	R30C44[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_3_s0/CLK
9.814	-0.051	tSu		1	R30C44[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_3_s0

Path Statistics:

Clock Skew	-0.029
Setup Relationship	8.333
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.560, 100.000%
Arrival Data Path Delay	cell: 1.457, 35.176%; route: 2.379, 57.436%; tC2Q: 0.306, 7.388%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.532, 100.000%

Path25

Path Summary:

Slack	4.176
Data Arrival Time	5.714
Data Required Time	9.890
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_0_s0
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.560	1.560	tNET	RR	1	R25C39[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_1_s0/CLK
1.854	0.294	tC2Q	RF	18	R25C39[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_1_s0/Q
2.353	0.499	tNET	FF	1	R26C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2164_s3/I1
2.774	0.421	tINS	FR	10	R26C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2164_s3/F
3.062	0.288	tNET	RR	1	R27C42[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2495_s8/I2
3.484	0.421	tINS	RR	2	R27C42[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2495_s8/F
3.612	0.128	tNET	RR	1	R26C42[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1650_s6/I0
3.980	0.369	tINS	RR	1	R26C42[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1650_s6/F
4.107	0.126	tNET	RR	1	R26C43[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1650_s5/I0
4.505	0.398	tINS	RR	1	R26C43[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1650_s5/F
4.507	0.002	tNET	RR	1	R26C43[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1650_s4/I0
4.839	0.332	tINS	RR	1	R26C43[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1650_s4/F
4.949	0.110	tNET	RR	1	R26C43[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1650_s7/I1
5.159	0.210	tINS	RR	1	R26C43[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1650_s7/F
5.285	0.126	tNET	RR	1	R26C42[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2770_s12/I0
5.473	0.188	tINS	RF	1	R26C42[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2770_s12/F
5.473	0.000	tNET	FF	1	R26C42[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2770_s9/I0
5.630	0.157	tINS	FF	1	R26C42[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2770_s9/O
5.630	0.000	tNET	FF	1	R26C42[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2770_s7/I1
5.711	0.081	tINS	FF	1	R26C42[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2770_s7/O
5.715	0.004	tNET	FF	1	R26C42[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.880	1.547	tNET	RR	1	R26C42[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_0_s0/CLK
9.890	0.010	tSu		1	R26C42[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_0_s0

Path Statistics:

Clock Skew	-0.013
Setup Relationship	8.333
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.560, 100.000%
Arrival Data Path Delay	cell: 2.577, 62.037%; route: 1.283, 30.886%; tC2Q: 0.294, 7.078%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.547, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.146
Data Arrival Time	0.993
Data Required Time	0.847
From	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_3_s0
To	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.815	0.815	tNET	RR	1	R9C23[1][A]	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_3_s0/CLK
0.956	0.141	tC2Q	RF	2	R9C23[1][A]	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_3_s0/Q
0.993	0.037	tNET	FF	1	BSRAM_R10[6]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.810	0.810	tNET	RR	1	BSRAM_R10[6]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/CLKA
0.847	0.037	tHld		1	BSRAM_R10[6]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.815, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.037, 20.787%; tC2Q: 0.141, 79.213%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.810, 100.000%

Path2

Path Summary:

Slack	0.207
Data Arrival Time	1.054
Data Required Time	0.847
From	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_1_s0
To	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.815	0.815	tNET	RR	1	R9C23[0][A]	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_1_s0/CLK
0.959	0.144	tC2Q	RR	2	R9C23[0][A]	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_1_s0/Q
1.054	0.095	tNET	RR	1	BSRAM_R10[6]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.810	0.810	tNET	RR	1	BSRAM_R10[6]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/CLKA
0.847	0.037	tHld		1	BSRAM_R10[6]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.815, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.095, 39.749%; tC2Q: 0.144, 60.251%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.810, 100.000%

Path3

Path Summary:

Slack	0.207
Data Arrival Time	1.054
Data Required Time	0.847
From	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/Q_6_s0
To	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.815	0.815	tNET	RR	1	R27C29[2][A]	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/Q_6_s0/CLK
0.959	0.144	tC2Q	RR	2	R27C29[2][A]	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/Q_6_s0/Q
1.054	0.095	tNET	RR	1	BSRAM_R28[8]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.810	0.810	tNET	RR	1	BSRAM_R28[8]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKA
0.847	0.037	tHld		1	BSRAM_R28[8]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.815, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.095, 39.749%; tC2Q: 0.144, 60.251%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.810, 100.000%

Path4

Path Summary:

Slack	0.212
Data Arrival Time	1.061
Data Required Time	0.849
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_4_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.822	0.822	tNET	RR	1	R27C47[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_4_s0/CLK
0.966	0.144	tC2Q	RR	3	R27C47[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_4_s0/Q
1.061	0.095	tNET	RR	1	BSRAM_R28[14]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/ADB[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.814	0.814	tNET	RR	1	BSRAM_R28[14]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/CLKB
0.849	0.035	tHld		1	BSRAM_R28[14]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s

Path Statistics:

Clock Skew	-0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.822, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.095, 39.749%; tC2Q: 0.144, 60.251%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.814, 100.000%

Path5

Path Summary:

Slack	0.214
Data Arrival Time	1.061
Data Required Time	0.847
From	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_6_s0
To	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_1_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R22C11[1][A]	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_6_s0/CLK
0.971	0.141	tC2Q	RF	2	R22C11[1][A]	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_6_s0/Q
1.061	0.090	tNET	FF	1	BSRAM_R28[2]	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_1_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.810	0.810	tNET	RR	1	BSRAM_R28[2]	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_1_s/CLKA
0.847	0.037	tHld		1	BSRAM_R28[2]	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_1_s

Path Statistics:

Clock Skew	-0.020
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.090, 38.961%; tC2Q: 0.141, 61.039%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.810, 100.000%

Path6

Path Summary:

Slack	0.215
Data Arrival Time	1.060
Data Required Time	0.845
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/rbin_num_0_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.815	0.815	tNET	RR	1	R27C45[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/rbin_num_0_s0/CLK
0.959	0.144	tC2Q	RR	5	R27C45[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/rbin_num_0_s0/Q
1.060	0.101	tNET	RR	1	BSRAM_R28[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/ADB[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.810	0.810	tNET	RR	1	BSRAM_R28[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/CLKB
0.845	0.035	tHld		1	BSRAM_R28[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.815, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.101, 41.224%; tC2Q: 0.144, 58.776%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.810, 100.000%

Path7

Path Summary:

Slack	0.215
Data Arrival Time	1.062
Data Required Time	0.847
From	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/wp_9_s0
To	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R22C29[1][A]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/wp_9_s0/CLK
0.971	0.141	tC2Q	RF	10	R22C29[1][A]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/wp_9_s0/Q
1.062	0.091	tNET	FF	1	BSRAM_R28[8]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/ADA[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.810	0.810	tNET	RR	1	BSRAM_R28[8]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKA
0.847	0.037	tHld		1	BSRAM_R28[8]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0

Path Statistics:

Clock Skew	-0.020
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.091, 39.224%; tC2Q: 0.141, 60.776%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.810, 100.000%

Path8

Path Summary:

Slack	0.236
Data Arrival Time	1.079
Data Required Time	0.843
From	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/wp_2_s1
To	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.834	0.834	tNET	RR	1	R20C9[3][A]	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/wp_2_s1/CLK
0.975	0.141	tC2Q	RF	9	R20C9[3][A]	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/wp_2_s1/Q
1.079	0.104	tNET	FF	1	BSRAM_R10[1]	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/ADA[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.806	0.806	tNET	RR	1	BSRAM_R10[1]	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/CLKA
0.843	0.037	tHld		1	BSRAM_R10[1]	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s

Path Statistics:

Clock Skew	-0.028
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.834, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.104, 42.449%; tC2Q: 0.141, 57.551%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.806, 100.000%

Path9

Path Summary:

Slack	0.247
Data Arrival Time	1.094
Data Required Time	0.847
From	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/Q_3_s0
To	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.808	0.808	tNET	RR	1	R32C22[0][A]	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/Q_3_s0/CLK
0.952	0.144	tC2Q	RR	2	R32C22[0][A]	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/Q_3_s0/Q
1.094	0.142	tNET	RR	1	BSRAM_R28[6]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.810	0.810	tNET	RR	1	BSRAM_R28[6]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s/CLKA
0.847	0.037	tHld		1	BSRAM_R28[6]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.808, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.142, 49.650%; tC2Q: 0.144, 50.350%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.810, 100.000%

Path10

Path Summary:

Slack	0.254
Data Arrival Time	1.101
Data Required Time	0.847
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbin_0_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.811	0.811	tNET	RR	1	R27C48[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbin_0_s0/CLK
0.955	0.144	tC2Q	RR	7	R27C48[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.wbin_0_s0/Q
1.101	0.146	tNET	RR	1	BSRAM_R28[14]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/ADA[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.810	0.810	tNET	RR	1	BSRAM_R28[14]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/CLKA
0.847	0.037	tHld		1	BSRAM_R28[14]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.811, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.146, 50.345%; tC2Q: 0.144, 49.655%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.810, 100.000%

Path11

Path Summary:

Slack	0.256
Data Arrival Time	1.107
Data Required Time	0.851
From	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/Q_1_s0
To	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.805	0.805	tNET	RR	1	R29C25[2][A]	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/Q_1_s0/CLK
0.946	0.141	tC2Q	RF	2	R29C25[2][A]	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/Q_1_s0/Q
1.107	0.161	tNET	FF	1	BSRAM_R28[7]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.814	0.814	tNET	RR	1	BSRAM_R28[7]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/CLKA
0.851	0.037	tHld		1	BSRAM_R28[7]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0

Path Statistics:

Clock Skew	0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.805, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.161, 53.311%; tC2Q: 0.141, 46.689%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.814, 100.000%

Path12

Path Summary:

Slack	0.258
Data Arrival Time	1.107
Data Required Time	0.849
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_3_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.822	0.822	tNET	RR	1	R27C47[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_3_s0/CLK
0.966	0.144	tC2Q	RR	6	R27C47[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_3_s0/Q
1.107	0.141	tNET	RR	1	BSRAM_R28[14]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/ADB[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.814	0.814	tNET	RR	1	BSRAM_R28[14]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/CLKB
0.849	0.035	tHld		1	BSRAM_R28[14]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s

Path Statistics:

Clock Skew	-0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.822, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.141, 49.474%; tC2Q: 0.144, 50.526%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.814, 100.000%

Path13

Path Summary:

Slack	0.259
Data Arrival Time	1.110
Data Required Time	0.851
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.808	0.808	tNET	RR	1	R31C45[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_1_s0/CLK
0.949	0.141	tC2Q	RF	4	R31C45[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_1_s0/Q
1.110	0.161	tNET	FF	1	BSRAM_R28[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/ADA[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.814	0.814	tNET	RR	1	BSRAM_R28[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/CLKA
0.851	0.037	tHld		1	BSRAM_R28[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s

Path Statistics:

Clock Skew	0.007
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.808, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.161, 53.311%; tC2Q: 0.141, 46.689%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.814, 100.000%

Path14

Path Summary:

Slack	0.261
Data Arrival Time	1.112
Data Required Time	0.851
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_0_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.807	0.807	tNET	RR	1	R30C46[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_0_s0/CLK
0.948	0.141	tC2Q	RF	6	R30C46[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_0_s0/Q
1.112	0.164	tNET	FF	1	BSRAM_R28[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/ADA[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
0.814	0.814	tNET	RR	1	BSRAM_R28[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/CLKA
0.851	0.037	tHld		1	BSRAM_R28[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s

Path Statistics:

Clock Skew	0.007
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.807, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.164, 53.770%; tC2Q: 0.141, 46.230%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.814, 100.000%

Path15

Path Summary:

Slack	0.263
Data Arrival Time	1.108
Data Required Time	0.845
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/rbin_num_3_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.816	0.816	tNET	RR	1	R26C44[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/rbin_num_3_s0/CLK
0.960	0.144	tC2Q	RR	6	R26C44[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/rbin_num_3_s0/Q
1.108	0.148	tNET	RR	1	BSRAM_R28[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/ADB[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.810	0.810	tNET	RR	1	BSRAM_R28[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/CLKB
0.845	0.035	tHld		1	BSRAM_R28[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s

Path Statistics:

Clock Skew	-0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.816, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.148, 50.685%; tC2Q: 0.144, 49.315%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.810, 100.000%

Path16

Path Summary:

Slack	0.266
Data Arrival Time	1.115
Data Required Time	0.849
From	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_next_8_s0
To	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.829	0.829	tNET	RR	1	R23C31[0][A]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_next_8_s0/CLK
0.973	0.144	tC2Q	RR	2	R23C31[0][A]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_next_8_s0/Q
1.115	0.143	tNET	RR	1	BSRAM_R28[8]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/ADB[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.814	0.814	tNET	RR	1	BSRAM_R28[8]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKB
0.849	0.035	tHld		1	BSRAM_R28[8]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0

Path Statistics:

Clock Skew	-0.015
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.829, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.143, 49.826%; tC2Q: 0.144, 50.174%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.814, 100.000%

Path17

Path Summary:

Slack	0.269
Data Arrival Time	1.118
Data Required Time	0.849
From	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_next_9_s0
To	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.829	0.829	tNET	RR	1	R23C31[0][B]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_next_9_s0/CLK
0.973	0.144	tC2Q	RR	2	R23C31[0][B]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_next_9_s0/Q
1.118	0.145	tNET	RR	1	BSRAM_R28[8]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/ADB[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.814	0.814	tNET	RR	1	BSRAM_R28[8]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKB
0.849	0.035	tHld		1	BSRAM_R28[8]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0

Path Statistics:

Clock Skew	-0.015
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.829, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.145, 50.173%; tC2Q: 0.144, 49.827%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.814, 100.000%

Path18

Path Summary:

Slack	0.275
Data Arrival Time	3.328
Data Required Time	3.053
From	pll1/u_pll_init/rRomAddr_4_s1
To	pll1/u_pll_init/rRomAddr_4_s1
Launch Clk	pll0/u_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	pll0/u_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll0/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
2.221	2.221	tCL	RR	102	PLL_B	pll0/u_pll/PLLA_inst/CLKOUT0
3.028	0.806	tNET	RR	1	R35C33[1][A]	pll1/u_pll_init/rRomAddr_4_s1/CLK
3.169	0.141	tC2Q	RF	3	R35C33[1][A]	pll1/u_pll_init/rRomAddr_4_s1/Q
3.175	0.006	tNET	FF	1	R35C33[1][A]	pll1/u_pll_init/n3945_s0/I1
3.328	0.153	tINS	FF	1	R35C33[1][A]	pll1/u_pll_init/n3945_s0/F
3.328	0.000	tNET	FF	1	R35C33[1][A]	pll1/u_pll_init/rRomAddr_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll0/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
2.221	2.221	tCL	RR	102	PLL_B	pll0/u_pll/PLLA_inst/CLKOUT0
3.028	0.806	tNET	RR	1	R35C33[1][A]	pll1/u_pll_init/rRomAddr_4_s1/CLK
3.053	0.025	tHld		1	R35C33[1][A]	pll1/u_pll_init/rRomAddr_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.806, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.806, 100.000%

Path19

Path Summary:

Slack	0.275
Data Arrival Time	2.173
Data Required Time	1.898
From	pll0/u_pll_init/rReqCnt_0_s0
To	pll0/u_pll_init/rReqCnt_0_s0
Launch Clk	clk_50:[R]
Latch Clk	clk_50:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_50
0.000	0.000	tCL	RR	1	IOB29[A]	CLK_IN_ibuf/I
1.046	1.046	tINS	RR	103	IOB29[A]	CLK_IN_ibuf/O
1.873	0.827	tNET	RR	1	R5C7[0][A]	pll0/u_pll_init/rReqCnt_0_s0/CLK
2.014	0.141	tC2Q	RF	3	R5C7[0][A]	pll0/u_pll_init/rReqCnt_0_s0/Q
2.020	0.006	tNET	FF	1	R5C7[0][A]	pll0/u_pll_init/n3973_s2/I0
2.173	0.153	tINS	FF	1	R5C7[0][A]	pll0/u_pll_init/n3973_s2/F
2.173	0.000	tNET	FF	1	R5C7[0][A]	pll0/u_pll_init/rReqCnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_50
0.000	0.000	tCL	RR	1	IOB29[A]	CLK_IN_ibuf/I
1.046	1.046	tINS	RR	103	IOB29[A]	CLK_IN_ibuf/O
1.873	0.827	tNET	RR	1	R5C7[0][A]	pll0/u_pll_init/rReqCnt_0_s0/CLK
1.898	0.025	tHld		1	R5C7[0][A]	pll0/u_pll_init/rReqCnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.046, 55.831%; route: 0.827, 44.169%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 1.046, 55.831%; route: 0.827, 44.169%

Path20

Path Summary:

Slack	0.275
Data Arrival Time	1.134
Data Required Time	0.859
From	u_usb_uart_config/test_tx_count_3_s1
To	u_usb_uart_config/test_tx_count_3_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.834	0.834	tNET	RR	1	R2C49[1][A]	u_usb_uart_config/test_tx_count_3_s1/CLK
0.975	0.141	tC2Q	RF	2	R2C49[1][A]	u_usb_uart_config/test_tx_count_3_s1/Q
0.981	0.006	tNET	FF	1	R2C49[1][A]	u_usb_uart_config/n1841_s2/I2
1.134	0.153	tINS	FF	1	R2C49[1][A]	u_usb_uart_config/n1841_s2/F
1.134	0.000	tNET	FF	1	R2C49[1][A]	u_usb_uart_config/test_tx_count_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.834	0.834	tNET	RR	1	R2C49[1][A]	u_usb_uart_config/test_tx_count_3_s1/CLK
0.859	0.025	tHld		1	R2C49[1][A]	u_usb_uart_config/test_tx_count_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.834, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.834, 100.000%

Path21

Path Summary:

Slack	0.275
Data Arrival Time	1.100
Data Required Time	0.825
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_1_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.800	0.800	tNET	RR	1	R31C53[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_1_s0/CLK
0.941	0.141	tC2Q	RF	7	R31C53[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_1_s0/Q
0.947	0.006	tNET	FF	1	R31C53[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n623_s1/I1
1.100	0.153	tINS	FF	1	R31C53[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n623_s1/F
1.100	0.000	tNET	FF	1	R31C53[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.800	0.800	tNET	RR	1	R31C53[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_1_s0/CLK
0.825	0.025	tHld		1	R31C53[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.800, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.800, 100.000%

Path22

Path Summary:

Slack	0.275
Data Arrival Time	1.127
Data Required Time	0.852
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_5_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_5_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.827	0.827	tNET	RR	1	R24C51[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_5_s0/CLK
0.968	0.141	tC2Q	RF	4	R24C51[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_5_s0/Q
0.974	0.006	tNET	FF	1	R24C51[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n619_s1/I3
1.127	0.153	tINS	FF	1	R24C51[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n619_s1/F
1.127	0.000	tNET	FF	1	R24C51[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.827	0.827	tNET	RR	1	R24C51[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_5_s0/CLK
0.852	0.025	tHld		1	R24C51[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.827, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.827, 100.000%

Path23

Path Summary:

Slack	0.275
Data Arrival Time	1.125
Data Required Time	0.850
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_8_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_8_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.825	0.825	tNET	RR	1	R25C51[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_8_s0/CLK
0.966	0.141	tC2Q	RF	5	R25C51[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_8_s0/Q
0.972	0.006	tNET	FF	1	R25C51[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n616_s1/I1
1.125	0.153	tINS	FF	1	R25C51[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/n616_s1/F
1.125	0.000	tNET	FF	1	R25C51[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.825	0.825	tNET	RR	1	R25C51[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_8_s0/CLK
0.850	0.025	tHld		1	R25C51[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb_fs_phy/u_usb_phy_rt/state_q_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.825, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.825, 100.000%

Path24

Path Summary:

Slack	0.275
Data Arrival Time	1.130
Data Required Time	0.855
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_1_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_1_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R22C41[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_1_s0/CLK
0.971	0.141	tC2Q	RF	2	R22C41[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_1_s0/Q
0.977	0.006	tNET	FF	1	R22C41[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1880_s17/I0
1.130	0.153	tINS	FF	1	R22C41[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1880_s17/F
1.130	0.000	tNET	FF	1	R22C41[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R22C41[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_1_s0/CLK
0.855	0.025	tHld		1	R22C41[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_sendbyte_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%

Path25

Path Summary:

Slack	0.275
Data Arrival Time	1.136
Data Required Time	0.861
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/wait_count_3_s2
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/wait_count_3_s2
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.836	0.836	tNET	RR	1	R21C46[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/wait_count_3_s2/CLK
0.977	0.141	tC2Q	RF	2	R21C46[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/wait_count_3_s2/Q
0.983	0.006	tNET	FF	1	R21C46[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/n1160_s18/I3
1.136	0.153	tINS	FF	1	R21C46[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/n1160_s18/F
1.136	0.000	tNET	FF	1	R21C46[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/wait_count_3_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.836	0.836	tNET	RR	1	R21C46[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/wait_count_3_s2/CLK
0.861	0.025	tHld		1	R21C46[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/wait_count_3_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.836, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.836, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	2.160
Data Arrival Time	7.432
Data Required Time	9.592
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_2_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.432	1.383	tNET	FF	1	R31C44[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.870	1.536	tNET	RR	1	R31C44[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_2_s0/CLK
9.592	-0.278	tSu		1	R31C44[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_2_s0

Path Statistics:

Clock Skew	0.009
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.383, 79.623%; tC2Q: 0.354, 20.377%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.536, 100.000%

Path2

Path Summary:

Slack	2.160
Data Arrival Time	7.432
Data Required Time	9.592
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_0_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.432	1.383	tNET	FF	1	R31C44[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.870	1.536	tNET	RR	1	R31C44[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_0_s0/CLK
9.592	-0.278	tSu		1	R31C44[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_0_s0

Path Statistics:

Clock Skew	0.009
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.383, 79.623%; tC2Q: 0.354, 20.377%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.536, 100.000%

Path3

Path Summary:

Slack	2.160
Data Arrival Time	7.432
Data Required Time	9.592
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_1_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.432	1.383	tNET	FF	1	R31C44[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.870	1.536	tNET	RR	1	R31C44[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_1_s0/CLK
9.592	-0.278	tSu		1	R31C44[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_1_s0

Path Statistics:

Clock Skew	0.009
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.383, 79.623%; tC2Q: 0.354, 20.377%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.536, 100.000%

Path4

Path Summary:

Slack	2.160
Data Arrival Time	7.432
Data Required Time	9.592
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_5_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.432	1.383	tNET	FF	1	R31C44[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.870	1.536	tNET	RR	1	R31C44[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_5_s0/CLK
9.592	-0.278	tSu		1	R31C44[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_5_s0

Path Statistics:

Clock Skew	0.009
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.383, 79.623%; tC2Q: 0.354, 20.377%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.536, 100.000%

Path5

Path Summary:

Slack	2.160
Data Arrival Time	7.437
Data Required Time	9.596
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Full_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.437	1.388	tNET	FF	1	R32C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Full_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.874	1.541	tNET	RR	1	R32C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Full_s0/CLK
9.596	-0.278	tSu		1	R32C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Full_s0

Path Statistics:

Clock Skew	0.013
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.388, 79.679%; tC2Q: 0.354, 20.321%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.541, 100.000%

Path6

Path Summary:

Slack	2.160
Data Arrival Time	7.437
Data Required Time	9.596
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_2_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.437	1.388	tNET	FF	1	R32C44[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.874	1.541	tNET	RR	1	R32C44[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_2_s0/CLK
9.596	-0.278	tSu		1	R32C44[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_2_s0

Path Statistics:

Clock Skew	0.013
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.388, 79.679%; tC2Q: 0.354, 20.321%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.541, 100.000%

Path7

Path Summary:

Slack	2.160
Data Arrival Time	7.437
Data Required Time	9.596
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_3_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.437	1.388	tNET	FF	1	R32C44[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.874	1.541	tNET	RR	1	R32C44[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_3_s0/CLK
9.596	-0.278	tSu		1	R32C44[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_3_s0

Path Statistics:

Clock Skew	0.013
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.388, 79.679%; tC2Q: 0.354, 20.321%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.541, 100.000%

Path8

Path Summary:

Slack	2.160
Data Arrival Time	7.437
Data Required Time	9.596
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_4_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.437	1.388	tNET	FF	1	R32C44[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.874	1.541	tNET	RR	1	R32C44[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_4_s0/CLK
9.596	-0.278	tSu		1	R32C44[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_4_s0

Path Statistics:

Clock Skew	0.013
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.388, 79.679%; tC2Q: 0.354, 20.321%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.541, 100.000%

Path9

Path Summary:

Slack	2.160
Data Arrival Time	7.437
Data Required Time	9.596
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_5_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.437	1.388	tNET	FF	1	R32C44[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.874	1.541	tNET	RR	1	R32C44[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_5_s0/CLK
9.596	-0.278	tSu		1	R32C44[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq2_rptr_5_s0

Path Statistics:

Clock Skew	0.013
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.388, 79.679%; tC2Q: 0.354, 20.321%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.541, 100.000%

Path10

Path Summary:

Slack	2.160
Data Arrival Time	7.437
Data Required Time	9.596
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_3_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.437	1.388	tNET	FF	1	R32C44[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.874	1.541	tNET	RR	1	R32C44[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_3_s0/CLK
9.596	-0.278	tSu		1	R32C44[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_3_s0

Path Statistics:

Clock Skew	0.013
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.388, 79.679%; tC2Q: 0.354, 20.321%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.541, 100.000%

Path11

Path Summary:

Slack	2.160
Data Arrival Time	7.437
Data Required Time	9.596
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_4_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.437	1.388	tNET	FF	1	R32C44[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.874	1.541	tNET	RR	1	R32C44[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_4_s0/CLK
9.596	-0.278	tSu		1	R32C44[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_4_s0

Path Statistics:

Clock Skew	0.013
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.388, 79.679%; tC2Q: 0.354, 20.321%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.541, 100.000%

Path12

Path Summary:

Slack	2.160
Data Arrival Time	7.419
Data Required Time	9.579
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_0_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.419	1.370	tNET	FF	1	R30C43[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.857	1.524	tNET	RR	1	R30C43[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_0_s0/CLK
9.579	-0.278	tSu		1	R30C43[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_0_s0

Path Statistics:

Clock Skew	-0.003
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.370, 79.472%; tC2Q: 0.354, 20.528%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.524, 100.000%

Path13

Path Summary:

Slack	2.160
Data Arrival Time	7.419
Data Required Time	9.579
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_2_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.419	1.370	tNET	FF	1	R30C43[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.857	1.524	tNET	RR	1	R30C43[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_2_s0/CLK
9.579	-0.278	tSu		1	R30C43[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_2_s0

Path Statistics:

Clock Skew	-0.003
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.370, 79.472%; tC2Q: 0.354, 20.528%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.524, 100.000%

Path14

Path Summary:

Slack	2.160
Data Arrival Time	7.424
Data Required Time	9.584
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_1_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.424	1.375	tNET	FF	1	R31C43[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.862	1.529	tNET	RR	1	R31C43[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_1_s0/CLK
9.584	-0.278	tSu		1	R31C43[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wq1_rptr_1_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.375, 79.529%; tC2Q: 0.354, 20.471%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.529, 100.000%

Path15

Path Summary:

Slack	2.167
Data Arrival Time	7.434
Data Required Time	9.601
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_4_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.434	1.386	tNET	FF	1	R33C44[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.879	1.546	tNET	RR	1	R33C44[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_4_s0/CLK
9.601	-0.278	tSu		1	R33C44[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_4_s0

Path Statistics:

Clock Skew	0.018
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.386, 79.649%; tC2Q: 0.354, 20.351%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.546, 100.000%

Path16

Path Summary:

Slack	2.167
Data Arrival Time	7.434
Data Required Time	9.601
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_4_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.434	1.386	tNET	FF	1	R33C44[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.879	1.546	tNET	RR	1	R33C44[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_4_s0/CLK
9.601	-0.278	tSu		1	R33C44[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_4_s0

Path Statistics:

Clock Skew	0.018
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.386, 79.649%; tC2Q: 0.354, 20.351%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.546, 100.000%

Path17

Path Summary:

Slack	2.167
Data Arrival Time	7.434
Data Required Time	9.601
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_5_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.434	1.386	tNET	FF	1	R33C44[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.879	1.546	tNET	RR	1	R33C44[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_5_s0/CLK
9.601	-0.278	tSu		1	R33C44[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_5_s0

Path Statistics:

Clock Skew	0.018
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.386, 79.649%; tC2Q: 0.354, 20.351%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.546, 100.000%

Path18

Path Summary:

Slack	2.168
Data Arrival Time	7.419
Data Required Time	9.587
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_2_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.419	1.370	tNET	FF	1	R30C44[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.865	1.532	tNET	RR	1	R30C44[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_2_s0/CLK
9.587	-0.278	tSu		1	R30C44[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_2_s0

Path Statistics:

Clock Skew	0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.370, 79.472%; tC2Q: 0.354, 20.528%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.532, 100.000%

Path19

Path Summary:

Slack	2.168
Data Arrival Time	7.419
Data Required Time	9.587
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_3_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.419	1.370	tNET	FF	1	R30C44[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.865	1.532	tNET	RR	1	R30C44[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_3_s0/CLK
9.587	-0.278	tSu		1	R30C44[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_3_s0

Path Statistics:

Clock Skew	0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.370, 79.472%; tC2Q: 0.354, 20.528%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.532, 100.000%

Path20

Path Summary:

Slack	2.171
Data Arrival Time	7.432
Data Required Time	9.602
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_3_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.432	1.383	tNET	FF	1	R34C44[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.880	1.547	tNET	RR	1	R34C44[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_3_s0/CLK
9.602	-0.278	tSu		1	R34C44[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_3_s0

Path Statistics:

Clock Skew	0.020
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.383, 79.620%; tC2Q: 0.354, 20.380%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.547, 100.000%

Path21

Path Summary:

Slack	2.175
Data Arrival Time	7.419
Data Required Time	9.594
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_0_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.419	1.370	tNET	FF	1	R30C45[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.872	1.539	tNET	RR	1	R30C45[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_0_s0/CLK
9.594	-0.278	tSu		1	R30C45[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_0_s0

Path Statistics:

Clock Skew	0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.370, 79.472%; tC2Q: 0.354, 20.528%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.539, 100.000%

Path22

Path Summary:

Slack	2.175
Data Arrival Time	7.419
Data Required Time	9.594
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_1_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.419	1.370	tNET	FF	1	R30C45[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.872	1.539	tNET	RR	1	R30C45[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_1_s0/CLK
9.594	-0.278	tSu		1	R30C45[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wptr_1_s0

Path Statistics:

Clock Skew	0.011
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.370, 79.472%; tC2Q: 0.354, 20.528%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.539, 100.000%

Path23

Path Summary:

Slack	2.175
Data Arrival Time	7.424
Data Required Time	9.599
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_1_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.424	1.375	tNET	FF	1	R31C45[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.877	1.544	tNET	RR	1	R31C45[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_1_s0/CLK
9.599	-0.278	tSu		1	R31C45[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.wbin_1_s0

Path Statistics:

Clock Skew	0.016
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.375, 79.529%; tC2Q: 0.354, 20.471%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.544, 100.000%

Path24

Path Summary:

Slack	2.177
Data Arrival Time	7.443
Data Required Time	9.619
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_0_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.443	1.394	tNET	FF	1	R27C47[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.897	1.564	tNET	RR	1	R27C47[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_0_s0/CLK
9.619	-0.278	tSu		1	R27C47[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_0_s0

Path Statistics:

Clock Skew	0.036
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.394, 79.745%; tC2Q: 0.354, 20.255%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.564, 100.000%

Path25

Path Summary:

Slack	2.177
Data Arrival Time	7.443
Data Required Time	9.619
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_1_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.695	1.528	tNET	FF	1	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/CLK
6.049	0.354	tC2Q	FF	46	R30C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/reset_w_1_s0/Q
7.443	1.394	tNET	FF	1	R27C47[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	199	BOTTOMSIDE[1]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.897	1.564	tNET	RR	1	R27C47[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_1_s0/CLK
9.619	-0.278	tSu		1	R27C47[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_1_s0

Path Statistics:

Clock Skew	0.036
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.528, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.394, 79.745%; tC2Q: 0.354, 20.255%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.564, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.224
Data Arrival Time	2.027
Data Required Time	0.803
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.027	1.053	tNET	RR	4	BSRAM_R10[8]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.814	0.814	tNET	RR	1	BSRAM_R10[8]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKB
0.803	-0.011	tHld		1	BSRAM_R10[8]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0

Path Statistics:

Clock Skew	-0.016
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.053, 87.970%; tC2Q: 0.144, 12.030%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.814, 100.000%

Path2

Path Summary:

Slack	1.224
Data Arrival Time	2.027
Data Required Time	0.803
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_0_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.027	1.053	tNET	RR	4	BSRAM_R28[0]	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_0_s/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.814	0.814	tNET	RR	1	BSRAM_R28[0]	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_0_s/CLKB
0.803	-0.011	tHld		1	BSRAM_R28[0]	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_0_s

Path Statistics:

Clock Skew	-0.016
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.053, 87.970%; tC2Q: 0.144, 12.030%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.814, 100.000%

Path3

Path Summary:

Slack	1.224
Data Arrival Time	2.027
Data Required Time	0.803
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.027	1.053	tNET	RR	4	BSRAM_R28[8]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.814	0.814	tNET	RR	1	BSRAM_R28[8]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKB
0.803	-0.011	tHld		1	BSRAM_R28[8]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s0

Path Statistics:

Clock Skew	-0.016
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.053, 87.970%; tC2Q: 0.144, 12.030%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.814, 100.000%

Path4

Path Summary:

Slack	1.228
Data Arrival Time	2.027
Data Required Time	0.799
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_1_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.027	1.053	tNET	RR	4	BSRAM_R28[1]	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_1_s/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.810	0.810	tNET	RR	1	BSRAM_R28[1]	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_1_s/CLKB
0.799	-0.011	tHld		1	BSRAM_R28[1]	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_1_s

Path Statistics:

Clock Skew	-0.020
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.053, 87.970%; tC2Q: 0.144, 12.030%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.810, 100.000%

Path5

Path Summary:

Slack	1.228
Data Arrival Time	2.027
Data Required Time	0.799
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.027	1.053	tNET	RR	4	BSRAM_R10[1]	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.810	0.810	tNET	RR	1	BSRAM_R10[1]	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s/CLKB
0.799	-0.011	tHld		1	BSRAM_R10[1]	usb_fifo/usb_rx_buf_ep3/sync_rx_pkt_fifo/RAM_RAM_0_0_s

Path Statistics:

Clock Skew	-0.020
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.053, 87.970%; tC2Q: 0.144, 12.030%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.810, 100.000%

Path6

Path Summary:

Slack	1.228
Data Arrival Time	2.027
Data Required Time	0.799
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.027	1.053	tNET	RR	4	BSRAM_R10[7]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.810	0.810	tNET	RR	1	BSRAM_R10[7]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/CLKB
0.799	-0.011	tHld		1	BSRAM_R10[7]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0

Path Statistics:

Clock Skew	-0.020
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.053, 87.970%; tC2Q: 0.144, 12.030%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.810, 100.000%

Path7

Path Summary:

Slack	1.228
Data Arrival Time	2.027
Data Required Time	0.799
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.027	1.053	tNET	RR	4	BSRAM_R10[9]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.810	0.810	tNET	RR	1	BSRAM_R10[9]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s/CLKB
0.799	-0.011	tHld		1	BSRAM_R10[9]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s

Path Statistics:

Clock Skew	-0.020
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.053, 87.970%; tC2Q: 0.144, 12.030%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.810, 100.000%

Path8

Path Summary:

Slack	1.228
Data Arrival Time	2.027
Data Required Time	0.799
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.027	1.053	tNET	RR	4	BSRAM_R28[7]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.810	0.810	tNET	RR	1	BSRAM_R28[7]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/CLKB
0.799	-0.011	tHld		1	BSRAM_R28[7]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s0

Path Statistics:

Clock Skew	-0.020
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.053, 87.970%; tC2Q: 0.144, 12.030%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.810, 100.000%

Path9

Path Summary:

Slack	1.228
Data Arrival Time	2.027
Data Required Time	0.799
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.027	1.053	tNET	RR	4	BSRAM_R28[9]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.810	0.810	tNET	RR	1	BSRAM_R28[9]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s/CLKB
0.799	-0.011	tHld		1	BSRAM_R28[9]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s

Path Statistics:

Clock Skew	-0.020
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.053, 87.970%; tC2Q: 0.144, 12.030%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.810, 100.000%

Path10

Path Summary:

Slack	1.232
Data Arrival Time	2.027
Data Required Time	0.795
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.027	1.053	tNET	RR	4	BSRAM_R10[6]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.806	0.806	tNET	RR	1	BSRAM_R10[6]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/CLKB
0.795	-0.011	tHld		1	BSRAM_R10[6]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s

Path Statistics:

Clock Skew	-0.024
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.053, 87.970%; tC2Q: 0.144, 12.030%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.806, 100.000%

Path11

Path Summary:

Slack	1.232
Data Arrival Time	2.027
Data Required Time	0.795
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_1_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.027	1.053	tNET	RR	4	BSRAM_R28[2]	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_1_s/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.806	0.806	tNET	RR	1	BSRAM_R28[2]	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_1_s/CLKB
0.795	-0.011	tHld		1	BSRAM_R28[2]	usb_fifo/usb_rx_buf_ep2/sync_rx_pkt_fifo/RAM_RAM_0_1_s

Path Statistics:

Clock Skew	-0.024
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.053, 87.970%; tC2Q: 0.144, 12.030%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.806, 100.000%

Path12

Path Summary:

Slack	1.232
Data Arrival Time	2.027
Data Required Time	0.795
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.027	1.053	tNET	RR	4	BSRAM_R28[6]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.806	0.806	tNET	RR	1	BSRAM_R28[6]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s/CLKB
0.795	-0.011	tHld		1	BSRAM_R28[6]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_0_s

Path Statistics:

Clock Skew	-0.024
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.053, 87.970%; tC2Q: 0.144, 12.030%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.806, 100.000%

Path13

Path Summary:

Slack	1.262
Data Arrival Time	2.018
Data Required Time	0.756
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_0_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.018	1.044	tNET	RR	1	R11C34[3][A]	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.809	0.809	tNET	RR	1	R11C34[3][A]	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_0_s0/CLK
0.756	-0.053	tHld		1	R11C34[3][A]	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_0_s0

Path Statistics:

Clock Skew	-0.021
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.044, 87.879%; tC2Q: 0.144, 12.121%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.809, 100.000%

Path14

Path Summary:

Slack	1.262
Data Arrival Time	2.018
Data Required Time	0.756
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_1_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.018	1.044	tNET	RR	1	R11C18[0][B]	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.809	0.809	tNET	RR	1	R11C18[0][B]	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_1_s0/CLK
0.756	-0.053	tHld		1	R11C18[0][B]	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_1_s0

Path Statistics:

Clock Skew	-0.021
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.044, 87.879%; tC2Q: 0.144, 12.121%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.809, 100.000%

Path15

Path Summary:

Slack	1.262
Data Arrival Time	2.018
Data Required Time	0.756
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/rbin_4_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.018	1.044	tNET	RR	1	R29C30[3][A]	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/rbin_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.809	0.809	tNET	RR	1	R29C30[3][A]	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/rbin_4_s0/CLK
0.756	-0.053	tHld		1	R29C30[3][A]	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/rbin_4_s0

Path Statistics:

Clock Skew	-0.021
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.044, 87.879%; tC2Q: 0.144, 12.121%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.809, 100.000%

Path16

Path Summary:

Slack	1.262
Data Arrival Time	2.018
Data Required Time	0.756
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_tx_buf_ep2/pkt_fifo_wr_num_d0_2_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.018	1.044	tNET	RR	1	R11C18[0][A]	usb_fifo/usb_tx_buf_ep2/pkt_fifo_wr_num_d0_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.809	0.809	tNET	RR	1	R11C18[0][A]	usb_fifo/usb_tx_buf_ep2/pkt_fifo_wr_num_d0_2_s0/CLK
0.756	-0.053	tHld		1	R11C18[0][A]	usb_fifo/usb_tx_buf_ep2/pkt_fifo_wr_num_d0_2_s0

Path Statistics:

Clock Skew	-0.021
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.044, 87.879%; tC2Q: 0.144, 12.121%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.809, 100.000%

Path17

Path Summary:

Slack	1.266
Data Arrival Time	2.018
Data Required Time	0.752
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/test_rd_addr_0_s2
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.018	1.044	tNET	RR	1	R11C49[2][A]	u_usb_uart_config/test_rd_addr_0_s2/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.805	0.805	tNET	RR	1	R11C49[2][A]	u_usb_uart_config/test_rd_addr_0_s2/CLK
0.752	-0.053	tHld		1	R11C49[2][A]	u_usb_uart_config/test_rd_addr_0_s2

Path Statistics:

Clock Skew	-0.025
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.044, 87.879%; tC2Q: 0.144, 12.121%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.805, 100.000%

Path18

Path Summary:

Slack	1.266
Data Arrival Time	2.018
Data Required Time	0.752
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/test_rd_addr_3_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.018	1.044	tNET	RR	1	R11C49[1][B]	u_usb_uart_config/test_rd_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.805	0.805	tNET	RR	1	R11C49[1][B]	u_usb_uart_config/test_rd_addr_3_s1/CLK
0.752	-0.053	tHld		1	R11C49[1][B]	u_usb_uart_config/test_rd_addr_3_s1

Path Statistics:

Clock Skew	-0.025
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.044, 87.879%; tC2Q: 0.144, 12.121%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.805, 100.000%

Path19

Path Summary:

Slack	1.266
Data Arrival Time	2.037
Data Required Time	0.771
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/s_set_len_14_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.037	1.063	tNET	RR	1	R8C50[3][A]	u_usb_uart_config/s_set_len_14_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.824	0.824	tNET	RR	1	R8C50[3][A]	u_usb_uart_config/s_set_len_14_s0/CLK
0.771	-0.053	tHld		1	R8C50[3][A]	u_usb_uart_config/s_set_len_14_s0

Path Statistics:

Clock Skew	-0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.063, 88.070%; tC2Q: 0.144, 11.930%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.824, 100.000%

Path20

Path Summary:

Slack	1.266
Data Arrival Time	2.037
Data Required Time	0.771
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/s_set_len_15_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.037	1.063	tNET	RR	1	R8C50[2][A]	u_usb_uart_config/s_set_len_15_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.824	0.824	tNET	RR	1	R8C50[2][A]	u_usb_uart_config/s_set_len_15_s0/CLK
0.771	-0.053	tHld		1	R8C50[2][A]	u_usb_uart_config/s_set_len_15_s0

Path Statistics:

Clock Skew	-0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.063, 88.070%; tC2Q: 0.144, 11.930%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.824, 100.000%

Path21

Path Summary:

Slack	1.266
Data Arrival Time	2.037
Data Required Time	0.771
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_5_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.037	1.063	tNET	RR	1	R8C54[1][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.824	0.824	tNET	RR	1	R8C54[1][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_5_s0/CLK
0.771	-0.053	tHld		1	R8C54[1][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin_5_s0

Path Statistics:

Clock Skew	-0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.063, 88.070%; tC2Q: 0.144, 11.930%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.824, 100.000%

Path22

Path Summary:

Slack	1.266
Data Arrival Time	2.018
Data Required Time	0.752
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_3_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.018	1.044	tNET	RR	1	R11C17[2][B]	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.805	0.805	tNET	RR	1	R11C17[2][B]	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_3_s0/CLK
0.752	-0.053	tHld		1	R11C17[2][B]	usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_3_s0

Path Statistics:

Clock Skew	-0.025
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.044, 87.879%; tC2Q: 0.144, 12.121%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.805, 100.000%

Path23

Path Summary:

Slack	1.266
Data Arrival Time	2.037
Data Required Time	0.771
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/rbin_1_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.037	1.063	tNET	RR	1	R26C30[1][A]	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/rbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.824	0.824	tNET	RR	1	R26C30[1][A]	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/rbin_1_s0/CLK
0.771	-0.053	tHld		1	R26C30[1][A]	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/rbin_1_s0

Path Statistics:

Clock Skew	-0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.063, 88.070%; tC2Q: 0.144, 11.930%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.824, 100.000%

Path24

Path Summary:

Slack	1.266
Data Arrival Time	2.018
Data Required Time	0.752
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/usb_tx_buf_ep2/pkt_fifo_wr_num_d0_3_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.018	1.044	tNET	RR	1	R11C17[3][A]	usb_fifo/usb_tx_buf_ep2/pkt_fifo_wr_num_d0_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.805	0.805	tNET	RR	1	R11C17[3][A]	usb_fifo/usb_tx_buf_ep2/pkt_fifo_wr_num_d0_3_s0/CLK
0.752	-0.053	tHld		1	R11C17[3][A]	usb_fifo/usb_tx_buf_ep2/pkt_fifo_wr_num_d0_3_s0

Path Statistics:

Clock Skew	-0.025
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.044, 87.879%; tC2Q: 0.144, 12.121%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.805, 100.000%

Path25

Path Summary:

Slack	1.266
Data Arrival Time	2.018
Data Required Time	0.752
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	usb_fifo/s_usb_txlen_6_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.830	0.830	tNET	RR	1	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
0.974	0.144	tC2Q	RR	888	R4C31[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
2.018	1.044	tNET	RR	1	R11C17[1][B]	usb_fifo/s_usb_txlen_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	3491	PLL_L[1]	pll1/u_pll/PLLA_inst/CLKOUT0
0.805	0.805	tNET	RR	1	R11C17[1][B]	usb_fifo/s_usb_txlen_6_s1/CLK
0.752	-0.053	tHld		1	R11C17[1][B]	usb_fifo/s_usb_txlen_6_s1

Path Statistics:

Clock Skew	-0.025
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.830, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.044, 87.879%; tC2Q: 0.144, 12.121%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.805, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	2.570
Actual Width:	3.432
Required Width:	0.862
Type:	Low Pulse Width
Clock:	clk_120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk_120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.715	1.548	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk_120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.147	0.814	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/CLKA

MPW2

MPW Summary:

Slack:	2.570
Actual Width:	3.432
Required Width:	0.862
Type:	Low Pulse Width
Clock:	clk_120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk_120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.715	1.548	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk_120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.147	0.814	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/CLKB

MPW3

MPW Summary:

Slack:	2.573
Actual Width:	3.435
Required Width:	0.862
Type:	High Pulse Width
Clock:	clk_120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk_120
0.000	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.551	1.551	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk_120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.986	0.819	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx_pkt/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/CLKA

MPW4

MPW Summary:

Slack:	2.573
Actual Width:	3.435
Required Width:	0.862
Type:	High Pulse Width
Clock:	clk_120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk_120
0.000	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.551	1.551	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk_120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
4.986	0.819	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/CLKB

MPW5

MPW Summary:

Slack:	3.223
Actual Width:	3.423
Required Width:	0.200
Type:	Low Pulse Width
Clock:	clk_120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk_120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.741	1.574	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk_120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.164	0.831	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_0_s0/CLK

MPW6

MPW Summary:

Slack:	3.223
Actual Width:	3.423
Required Width:	0.200
Type:	Low Pulse Width
Clock:	clk_120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk_120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.741	1.574	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk_120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.164	0.831	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_0_s0/CLK

MPW7

MPW Summary:

Slack:	3.223
Actual Width:	3.423
Required Width:	0.200
Type:	Low Pulse Width
Clock:	clk_120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk_120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.741	1.574	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk_120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.164	0.831	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_3_s0/CLK

MPW8

MPW Summary:

Slack:	3.223
Actual Width:	3.423
Required Width:	0.200
Type:	Low Pulse Width
Clock:	clk_120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk_120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.741	1.574	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk_120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.164	0.831	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_2_s0/CLK

MPW9

MPW Summary:

Slack:	3.224
Actual Width:	3.424
Required Width:	0.200
Type:	Low Pulse Width
Clock:	clk_120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_4_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk_120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.735	1.569	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_4_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk_120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.159	0.826	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_4_s0/CLK

MPW10

MPW Summary:

Slack:	3.224
Actual Width:	3.424
Required Width:	0.200
Type:	Low Pulse Width
Clock:	clk_120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_4_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk_120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
5.735	1.569	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_4_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk_120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
9.159	0.826	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_4_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
3491	PHY_CLKOUT	4.429	1.578
888	usb_busreset	10.386	2.045
406	RESET	4.429	1.441
260	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin[5]	12.154	2.349
260	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/rbin[5]	13.551	1.380
260	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/rbin[5]	13.437	1.510
260	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/rbin[5]	11.932	1.975
199	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/sclk	2.681	1.577
133	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/rbin[4]	13.177	1.813
130	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/rbin[4]	13.413	1.500

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C7	100.00%
R2C27	100.00%
R2C35	100.00%
R2C39	100.00%
R2C41	100.00%
R3C14	100.00%
R3C15	100.00%
R4C53	100.00%
R13C44	100.00%
R25C23	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk_50 -period 20 -waveform {0 10} [get_ports {CLK_IN}]
TC_CLOCK	Actived	create_clock -name clk_120 -period 8.333 -waveform {0 4.167} [get_nets {u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/sclk}]
TC_CLOCK	Actived	create_clock -name clk_60 -period 16.667 -waveform {0 8.334} [get_nets {PHY_CLKOUT}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk_120}] -to [get_clocks {clk_60}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk_60}] -to [get_clocks {clk_120}]
TC_OPERATING_CONDITIONS	Actived	set_operating_conditions -grade c -model slow -speed 2 -setup -hold