Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj25k_usb2_loopback_speed\prj25k_usb2_loopback_speed_single_lvds\project\src\TOP.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj25k_usb2_loopback_speed\prj25k_usb2_loopback_speed_single_lvds\project\src\fixed_point_divider\fixed_point_divider.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj25k_usb2_loopback_speed\prj25k_usb2_loopback_speed_single_lvds\project\src\gowin_pll_gen24\gowin_pll_gen24.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj25k_usb2_loopback_speed\prj25k_usb2_loopback_speed_single_lvds\project\src\gowin_pll_gen24\gowin_pll_gen24_mod.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj25k_usb2_loopback_speed\prj25k_usb2_loopback_speed_single_lvds\project\src\gowin_pll_usb\gowin_pll_usb.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj25k_usb2_loopback_speed\prj25k_usb2_loopback_speed_single_lvds\project\src\gowin_pll_usb\gowin_pll_usb_mod.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj25k_usb2_loopback_speed\prj25k_usb2_loopback_speed_single_lvds\project\src\pll_init.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj25k_usb2_loopback_speed\prj25k_usb2_loopback_speed_single_lvds\project\src\sync_fifo\sync_rx_pkt_fifo.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj25k_usb2_loopback_speed\prj25k_usb2_loopback_speed_single_lvds\project\src\sync_fifo\sync_tx_pkt_fifo.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj25k_usb2_loopback_speed\prj25k_usb2_loopback_speed_single_lvds\project\src\sync_fifo\usb_fifo.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj25k_usb2_loopback_speed\prj25k_usb2_loopback_speed_single_lvds\project\src\uart\uart.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj25k_usb2_loopback_speed\prj25k_usb2_loopback_speed_single_lvds\project\src\uart\usb_uart_config.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj25k_usb2_loopback_speed\prj25k_usb2_loopback_speed_single_lvds\project\src\usb2_0_softphy\usb2_0_softphy.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj25k_usb2_loopback_speed\prj25k_usb2_loopback_speed_single_lvds\project\src\usb_descriptor.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj25k_usb2_loopback_speed\prj25k_usb2_loopback_speed_single_lvds\project\src\usb_device_controller\usb_device_controller.v D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj25k_usb2_loopback_speed\prj25k_usb2_loopback_speed_single_lvds\project\src\uart\uart_rx.vhd D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj25k_usb2_loopback_speed\prj25k_usb2_loopback_speed_single_lvds\project\src\uart\uart_tx.vhd |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12 (64-bit) |
| Part Number | GW5A-LV25UG324C1/I0 |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Wed Nov 5 09:24:08 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.875s, Elapsed time = 0h 0m 1s, Peak memory usage = 780.297MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.718s, Elapsed time = 0h 0m 0.698s, Peak memory usage = 780.297MB Optimizing Phase 1: CPU time = 0h 0m 0.578s, Elapsed time = 0h 0m 0.36s, Peak memory usage = 780.297MB Optimizing Phase 2: CPU time = 0h 0m 0.812s, Elapsed time = 0h 0m 0.559s, Peak memory usage = 780.297MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.593s, Elapsed time = 0h 0m 0.441s, Peak memory usage = 780.297MB Inferring Phase 1: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.176s, Peak memory usage = 780.297MB Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.053s, Peak memory usage = 780.297MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 780.297MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.687s, Elapsed time = 0h 0m 0.553s, Peak memory usage = 780.297MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.141s, Peak memory usage = 780.297MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 780.297MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 780.297MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.543s, Peak memory usage = 780.297MB Generate output files: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.443s, Peak memory usage = 780.297MB |
| Total Time and Memory Usage | CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 780.297MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 10 |
| I/O Buf | 8 |
| IBUF | 3 |
| OBUF | 1 |
| TBUF | 1 |
| IOBUF | 2 |
| ELVDS_IOBUF | 1 |
| Register | 3857 |
| DFFSE | 40 |
| DFFRE | 2681 |
| DFFPE | 48 |
| DFFCE | 1088 |
| LUT | 4855 |
| LUT2 | 488 |
| LUT3 | 2177 |
| LUT4 | 2190 |
| ALU | 527 |
| ALU | 527 |
| INV | 58 |
| INV | 58 |
| IOLOGIC | 4 |
| IDES8 | 2 |
| IDES16 | 1 |
| OSER16 | 1 |
| BSRAM | 16 |
| SDPB | 14 |
| pROM | 2 |
| CLOCK | 4 |
| CLKDIV | 1 |
| DHCE | 1 |
| PLLA | 2 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 5440(4913 LUT, 527 ALU) / 23040 | 24% |
| Register | 3857 / 23685 | 17% |
| --Register as Latch | 0 / 23685 | 0% |
| --Register as FF | 3857 / 23685 | 17% |
| BSRAM | 16 / 56 | 29% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | CLK_IN | Base | 20.000 | 50.000 | 0.000 | 10.000 | CLK_IN_ibuf/I | ||
| 2 | pll0/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 41.667 | 24.000 | 0.000 | 20.833 | CLK_IN_ibuf/I | CLK_IN | pll0/u_pll/PLLA_inst/CLKOUT0 |
| 3 | pll1/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 16.667 | 60.000 | 0.000 | 8.333 | pll0/u_pll/PLLA_inst/CLKOUT0 | pll0/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | pll1/u_pll/PLLA_inst/CLKOUT0 |
| 4 | pll1/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | Generated | 1.042 | 960.000 | 0.000 | 0.521 | pll0/u_pll/PLLA_inst/CLKOUT0 | pll0/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | pll1/u_pll/PLLA_inst/CLKOUT1 |
| 5 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk | Generated | 8.333 | 120.000 | 0.000 | 4.167 | pll1/u_pll/PLLA_inst/CLKOUT1 | pll1/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | CLK_IN | 50.000(MHz) | 168.492(MHz) | 7 | TOP |
| 2 | pll0/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | 24.000(MHz) | 162.767(MHz) | 7 | TOP |
| 3 | pll1/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | 60.000(MHz) | 87.127(MHz) | 12 | TOP |
| 4 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk | 120.000(MHz) | 124.572(MHz) | 8 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -0.479 |
| Data Arrival Time | 1.695 |
| Data Required Time | 1.217 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/u_oser_rst/reset_stop_s2 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/dhcen_inst |
| Launch Clk | pll1/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[F] |
| Latch Clk | pll1/u_pll/PLLA_inst/CLKOUT1.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | pll1/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 0.563 | 0.563 | tCL | RR | 3491 | pll1/u_pll/PLLA_inst/CLKOUT0 |
| 0.938 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/u_oser_rst/reset_stop_s2/CLK |
| 1.320 | 0.382 | tC2Q | RR | 2 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/u_oser_rst/reset_stop_s2/Q |
| 1.695 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/dhcen_inst/CEN |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.521 | 0.000 | pll1/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | |||
| 1.084 | 0.563 | tCL | FF | 1 | pll1/u_pll/PLLA_inst/CLKOUT1 |
| 1.434 | 0.350 | tNET | FF | 3 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/dhcen_inst/CLKIN |
| 1.399 | -0.035 | tUnc | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/dhcen_inst | ||
| 1.217 | -0.182 | tSu | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/dhcen_inst |
| Clock Skew: | -0.025 |
| Setup Relationship: | 0.521 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.375, 49.505%; tC2Q: 0.382, 50.495% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:| Slack | -0.285 |
| Data Arrival Time | 9.009 |
| Data Required Time | 8.725 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_6_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_0_s1 |
| Launch Clk | pll1/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | pll1/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 0.563 | 0.563 | tCL | RR | 3491 | pll1/u_pll/PLLA_inst/CLKOUT0 |
| 0.938 | 0.375 | tNET | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_6_s0/CLK |
| 1.320 | 0.382 | tC2Q | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_6_s0/Q |
| 1.695 | 0.375 | tNET | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n127_s6/I0 |
| 2.222 | 0.526 | tINS | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n127_s6/F |
| 2.597 | 0.375 | tNET | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n127_s4/I3 |
| 2.859 | 0.262 | tINS | RR | 4 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n127_s4/F |
| 3.234 | 0.375 | tNET | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I2 |
| 3.695 | 0.461 | tINS | RR | 5 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F |
| 4.070 | 0.375 | tNET | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s0/I2 |
| 4.532 | 0.461 | tINS | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s0/F |
| 4.907 | 0.375 | tNET | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2 |
| 5.368 | 0.461 | tINS | RR | 10 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F |
| 5.743 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n24_s3/I1 |
| 6.259 | 0.516 | tINS | RR | 6 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n24_s3/F |
| 6.634 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n3096_s3/I2 |
| 7.095 | 0.461 | tINS | RR | 2 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n3096_s3/F |
| 7.470 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_0_s4/I0 |
| 7.997 | 0.526 | tINS | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_0_s4/F |
| 8.372 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_0_s3/I3 |
| 8.634 | 0.262 | tINS | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_0_s3/F |
| 9.009 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_0_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 8.333 | 0.000 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 8.696 | 0.362 | tCL | RR | 199 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 9.071 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_0_s1/CLK |
| 9.036 | -0.035 | tUnc | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_0_s1 | ||
| 8.725 | -0.311 | tSu | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_state_0_s1 |
| Clock Skew: | -0.201 |
| Setup Relationship: | 8.333 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 3.939, 48.800%; route: 3.750, 46.461%; tC2Q: 0.382, 4.739% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:| Slack | 0.306 |
| Data Arrival Time | 8.701 |
| Data Required Time | 9.007 |
| From | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_0_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_0_s0 |
| Launch Clk | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 0.362 | 0.362 | tCL | RR | 199 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 0.737 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_0_s0/CLK |
| 1.120 | 0.382 | tC2Q | RR | 20 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_0_s0/Q |
| 1.495 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2164_s3/I0 |
| 2.021 | 0.526 | tINS | RR | 10 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2164_s3/F |
| 2.396 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2495_s8/I2 |
| 2.857 | 0.461 | tINS | RR | 2 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2495_s8/F |
| 3.232 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1650_s6/I0 |
| 3.759 | 0.526 | tINS | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1650_s6/F |
| 4.134 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1650_s5/I0 |
| 4.660 | 0.526 | tINS | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1650_s5/F |
| 5.035 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1650_s4/I0 |
| 5.561 | 0.526 | tINS | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1650_s4/F |
| 5.936 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1650_s7/I1 |
| 6.452 | 0.516 | tINS | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n1650_s7/F |
| 6.827 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2770_s12/I0 |
| 7.354 | 0.526 | tINS | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2770_s12/F |
| 7.729 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2770_s9/I0 |
| 7.865 | 0.136 | tINS | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2770_s9/O |
| 8.240 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2770_s7/I1 |
| 8.326 | 0.086 | tINS | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n2770_s7/O |
| 8.701 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 8.333 | 0.000 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 8.696 | 0.362 | tCL | RR | 199 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 9.071 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_0_s0/CLK |
| 9.007 | -0.064 | tSu | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_data_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 8.333 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 3.831, 48.109%; route: 3.750, 47.088%; tC2Q: 0.382, 4.803% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:| Slack | 0.552 |
| Data Arrival Time | 8.173 |
| Data Required Time | 8.725 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_6_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_act_s1 |
| Launch Clk | pll1/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | pll1/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 0.563 | 0.563 | tCL | RR | 3491 | pll1/u_pll/PLLA_inst/CLKOUT0 |
| 0.938 | 0.375 | tNET | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_6_s0/CLK |
| 1.320 | 0.382 | tC2Q | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_6_s0/Q |
| 1.695 | 0.375 | tNET | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n127_s6/I0 |
| 2.222 | 0.526 | tINS | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n127_s6/F |
| 2.597 | 0.375 | tNET | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n127_s4/I3 |
| 2.859 | 0.262 | tINS | RR | 4 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n127_s4/F |
| 3.234 | 0.375 | tNET | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I2 |
| 3.695 | 0.461 | tINS | RR | 5 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F |
| 4.070 | 0.375 | tNET | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s0/I2 |
| 4.532 | 0.461 | tINS | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s0/F |
| 4.907 | 0.375 | tNET | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2 |
| 5.368 | 0.461 | tINS | RR | 10 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F |
| 5.743 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n3086_s10/I1 |
| 6.259 | 0.516 | tINS | RR | 4 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n3086_s10/F |
| 6.634 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n742_s4/I0 |
| 7.160 | 0.526 | tINS | RR | 3 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n742_s4/F |
| 7.535 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_act_s4/I3 |
| 7.798 | 0.262 | tINS | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_act_s4/F |
| 8.173 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_act_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 8.333 | 0.000 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 8.696 | 0.362 | tCL | RR | 199 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 9.071 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_act_s1/CLK |
| 9.036 | -0.035 | tUnc | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_act_s1 | ||
| 8.725 | -0.311 | tSu | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/bit_align_wr_act_s1 |
| Clock Skew: | -0.201 |
| Setup Relationship: | 8.333 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 3.477, 48.065%; route: 3.375, 46.648%; tC2Q: 0.382, 5.287% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:| Slack | 0.552 |
| Data Arrival Time | 8.173 |
| Data Required Time | 8.725 |
| From | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_6_s0 |
| To | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0 |
| Launch Clk | pll1/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | pll1/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 0.563 | 0.563 | tCL | RR | 3491 | pll1/u_pll/PLLA_inst/CLKOUT0 |
| 0.938 | 0.375 | tNET | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_6_s0/CLK |
| 1.320 | 0.382 | tC2Q | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_testmode_6_s0/Q |
| 1.695 | 0.375 | tNET | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n127_s6/I0 |
| 2.222 | 0.526 | tINS | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n127_s6/F |
| 2.597 | 0.375 | tNET | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n127_s4/I3 |
| 2.859 | 0.262 | tINS | RR | 4 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/test_packet_inst/n127_s4/F |
| 3.234 | 0.375 | tNET | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/I2 |
| 3.695 | 0.461 | tINS | RR | 5 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_dataout_o_d_7_s3/F |
| 4.070 | 0.375 | tNET | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s0/I2 |
| 4.532 | 0.461 | tINS | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s0/F |
| 4.907 | 0.375 | tNET | RR | 1 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/I2 |
| 5.368 | 0.461 | tINS | RR | 10 | u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/utmi_txvalid_o_d_s/F |
| 5.743 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n3086_s10/I1 |
| 6.259 | 0.516 | tINS | RR | 4 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/n3086_s10/F |
| 6.634 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_1_s4/I0 |
| 7.160 | 0.526 | tINS | RR | 14 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_1_s4/F |
| 7.535 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s5/I3 |
| 7.798 | 0.262 | tINS | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s5/F |
| 8.173 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 8.333 | 0.000 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 8.696 | 0.362 | tCL | RR | 199 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
| 9.071 | 0.375 | tNET | RR | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0/CLK |
| 9.036 | -0.035 | tUnc | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0 | ||
| 8.725 | -0.311 | tSu | 1 | u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/hs_rx_sel_2_s0 |
| Clock Skew: | -0.201 |
| Setup Relationship: | 8.333 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 3.477, 48.065%; route: 3.375, 46.648%; tC2Q: 0.382, 5.287% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |