Timing Messages

Report Title	Timing Analysis Report
Design File	D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj18k_usb2_loopback_speed\prj18k_usb2_loopback_speed_single_lvds\project\impl\gwsynthesis\gowin_usb_refdesign.vg
Physical Constraints File	D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj18k_usb2_loopback_speed\prj18k_usb2_loopback_speed_single_lvds\project\src\usb_ref.cst
Timing Constraint File	D:\Gowin\GowinUSB\USBTestDemoScipt\USBTestDemoScipt\USB20TestDemoScipt\prj18k_usb2_loopback_speed\prj18k_usb2_loopback_speed_single_lvds\project\src\usb_ref.sdc
Tool Version	V1.9.12 (64-bit)
Part Number	GW2AR-LV18QN88PFC7/I6
Device	GW2AR-18
Device Version	C
Created Time	Wed Nov 5 09:20:22 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C C7/I6
Hold Delay Model	Fast 1.05V 0C C7/I6
Numbers of Paths Analyzed	5116
Numbers of Endpoints Analyzed	4957
Numbers of Falling Endpoints	4
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Fall	Source	Master	Objects
1	clk_50	Base	20.000	50.000	10.000			CLK_IN
2	clk_120	Base	8.333	120.005	4.167			u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/sclk
3	clk_60	Base	16.667	59.999	8.334			PHY_CLKOUT
4	u_pll/rpll_inst/CLKOUT.default_gen_clk	Generated	0.500	2000.000	0.250	CLK_IN_ibuf/I	clk_50	u_pll/rpll_inst/CLKOUT
5	u_pll/rpll_inst/CLKOUTP.default_gen_clk	Generated	0.500	2000.000	0.250	CLK_IN_ibuf/I	clk_50	u_pll/rpll_inst/CLKOUTP
6	u_pll/rpll_inst/CLKOUTD3.default_gen_clk	Generated	1.500	666.667	0.750	CLK_IN_ibuf/I	clk_50	u_pll/rpll_inst/CLKOUTD3

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk_120	120.005(MHz)	122.268(MHz)	7	TOP
2	clk_60	59.999(MHz)	60.797(MHz)	17	TOP

No timing paths to get frequency of clk_50!

No timing paths to get frequency of u_pll/rpll_inst/CLKOUT.default_gen_clk!

No timing paths to get frequency of u_pll/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of u_pll/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk_50	Setup	0.000	0
clk_50	Hold	0.000	0
clk_120	Setup	0.000	0
clk_120	Hold	0.000	0
clk_60	Setup	0.000	0
clk_60	Hold	0.000	0
u_pll/rpll_inst/CLKOUT.default_gen_clk	Setup	0.000	0
u_pll/rpll_inst/CLKOUT.default_gen_clk	Hold	0.000	0
u_pll/rpll_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
u_pll/rpll_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
u_pll/rpll_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
u_pll/rpll_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Data Delay
1	0.154	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/Q3	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s1/CE	clk_120:[R]	clk_120:[R]	8.333	8.135
2	0.219	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_15_s1/D	clk_60:[R]	clk_60:[R]	16.667	16.404
3	0.252	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/Q3	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s1/D	clk_120:[R]	clk_120:[R]	8.333	8.038
4	0.277	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s1/D	clk_60:[R]	clk_60:[R]	16.667	16.346
5	0.378	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/Q6	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1/D	clk_120:[R]	clk_120:[R]	8.333	7.911
6	0.384	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/Q3	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1/CE	clk_120:[R]	clk_120:[R]	8.333	7.905
7	0.472	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_16_s1/D	clk_60:[R]	clk_60:[R]	16.667	16.151
8	0.563	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/Q3	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/dru_locked_s2/D	clk_120:[R]	clk_120:[R]	8.333	7.726
9	0.765	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_2_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_9_s2/D	clk_60:[R]	clk_60:[R]	16.667	15.858
10	0.807	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_3_s1/D	clk_60:[R]	clk_60:[R]	16.667	15.817
11	0.819	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_endpt_2_s0/Q	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_12_s1/D	clk_60:[R]	clk_60:[R]	16.667	15.804
12	0.942	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_8_s1/D	clk_60:[R]	clk_60:[R]	16.667	15.682
13	0.967	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_10_s1/D	clk_60:[R]	clk_60:[R]	16.667	15.656
14	0.975	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_endpt_2_s0/Q	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_10_s1/D	clk_60:[R]	clk_60:[R]	16.667	15.648
15	0.975	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_endpt_2_s0/Q	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_11_s1/D	clk_60:[R]	clk_60:[R]	16.667	15.648
16	0.987	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_14_s1/D	clk_60:[R]	clk_60:[R]	16.667	15.636
17	0.994	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_0_s1/D	clk_60:[R]	clk_60:[R]	16.667	15.629
18	1.054	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_11_s1/D	clk_60:[R]	clk_60:[R]	16.667	15.569
19	1.091	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_endpt_2_s0/Q	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_10_s1/D	clk_60:[R]	clk_60:[R]	16.667	15.532
20	1.095	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_1_s1/D	clk_60:[R]	clk_60:[R]	16.667	15.528
21	1.095	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_2_s1/D	clk_60:[R]	clk_60:[R]	16.667	15.528
22	1.100	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_13_s1/D	clk_60:[R]	clk_60:[R]	16.667	15.523
23	1.106	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_4_s1/D	clk_60:[R]	clk_60:[R]	16.667	15.517
24	1.133	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_endpt_2_s0/Q	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_9_s1/D	clk_60:[R]	clk_60:[R]	16.667	15.491
25	1.142	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_2_s0/Q	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_8_s4/D	clk_60:[R]	clk_60:[R]	16.667	15.482

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Data Delay
1	0.099	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_0_s0/Q	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/DI[0]	clk_60:[R]	clk_60:[R]	0.410
2	0.262	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_4_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/ADA[7]	clk_120:[R]	clk_120:[R]	0.410
3	0.264	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/ADA[4]	clk_120:[R]	clk_120:[R]	0.411
4	0.266	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/wp_1_s0/Q	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s/ADA[3]	clk_60:[R]	clk_60:[R]	0.413
5	0.270	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_1_s0/Q	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/DI[1]	clk_60:[R]	clk_60:[R]	0.582
6	0.278	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_2_s1/Q	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s/ADB[4]	clk_60:[R]	clk_60:[R]	0.426
7	0.284	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_4_s1/Q	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s/ADB[6]	clk_60:[R]	clk_60:[R]	0.431
8	0.397	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/wbin_1_s0/Q	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/mem_mem_1_1_s/WAD[1]	clk_60:[R]	clk_60:[R]	0.410
9	0.398	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/Q_7_s0/Q	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/mem_mem_3_1_s/DI[3]	clk_60:[R]	clk_60:[R]	0.410
10	0.402	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_2_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/mem_mem_3_1_s/WAD[2]	clk_60:[R]	clk_60:[R]	0.415
11	0.402	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/wbin_0_s0/Q	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/mem_mem_0_0_s/WAD[0]	clk_60:[R]	clk_60:[R]	0.415
12	0.404	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_7_s0/Q	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DI[3]	clk_60:[R]	clk_60:[R]	0.715
13	0.404	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_4_s0/Q	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DI[0]	clk_60:[R]	clk_60:[R]	0.715
14	0.406	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_1_s0/Q	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/mem_mem_3_1_s/WAD[1]	clk_60:[R]	clk_60:[R]	0.419
15	0.407	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_3_s1/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/DI[4]	clk_120:[R]	clk_120:[R]	0.718
16	0.409	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/wbin_1_s0/Q	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/mem_mem_0_1_s/WAD[1]	clk_60:[R]	clk_60:[R]	0.422
17	0.416	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_8_s1/Q	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s/ADB[10]	clk_60:[R]	clk_60:[R]	0.564
18	0.418	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/wp_5_s0/Q	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/ADA[7]	clk_60:[R]	clk_60:[R]	0.565
19	0.419	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_6_s0/Q	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DI[2]	clk_60:[R]	clk_60:[R]	0.730
20	0.420	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_2_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/ADA[5]	clk_120:[R]	clk_120:[R]	0.567
21	0.421	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_4_s1/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/DI[3]	clk_120:[R]	clk_120:[R]	0.732
22	0.421	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_5_s0/Q	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DI[1]	clk_60:[R]	clk_60:[R]	0.732
23	0.421	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_0_s1/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/DI[7]	clk_120:[R]	clk_120:[R]	0.732
24	0.421	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_1_s1/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/DI[6]	clk_120:[R]	clk_120:[R]	0.732
25	0.421	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_2_s1/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/DI[5]	clk_120:[R]	clk_120:[R]	0.732

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.635	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/RESETB	clk_120:[F]	clk_120:[R]	4.166	0.004	2.980
2	0.747	reset_cnt_0_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_r_1_s0/PRESET	clk_60:[R]	clk_60:[F]	8.334	-0.004	7.547
3	0.747	reset_cnt_0_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_r_0_s0/PRESET	clk_60:[R]	clk_60:[F]	8.334	-0.004	7.547
4	1.119	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_1_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.004	3.000
5	1.119	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_2_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.004	3.000
6	1.119	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_4_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.004	3.000
7	1.119	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Full_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.004	3.000
8	1.119	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_4_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.004	3.000
9	1.119	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_5_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.004	3.000
10	1.119	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_0_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.004	3.000
11	1.129	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_2_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.004	2.990
12	1.129	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_0_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.004	2.990
13	1.129	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_3_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.004	2.990
14	1.129	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_0_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.004	2.990
15	1.129	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_3_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.004	2.990
16	1.129	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_4_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.004	2.990
17	1.129	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_1_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.004	2.990
18	1.129	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_2_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.004	2.990
19	1.129	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_4_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.004	2.990
20	1.129	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_5_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.004	2.990
21	1.129	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_0_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.004	2.990
22	1.129	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_1_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.004	2.990
23	1.129	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_2_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.004	2.990
24	1.129	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_0_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.004	2.990
25	1.129	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_1_s0/CLEAR	clk_120:[F]	clk_120:[R]	4.166	0.004	2.990

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Data Delay
1	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/stage_0_s3/CLEAR	clk_60:[R]	clk_60:[R]	1.729
2	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/stage_3_s4/CLEAR	clk_60:[R]	clk_60:[R]	1.729
3	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/endpt0_txcork_s1/CLEAR	clk_60:[R]	clk_60:[R]	1.729
4	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/endpt0_rxrdy_s1/PRESET	clk_60:[R]	clk_60:[R]	1.729
5	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/endpt0_dat_0_s1/CLEAR	clk_60:[R]	clk_60:[R]	1.729
6	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/endpt0_dat_1_s1/CLEAR	clk_60:[R]	clk_60:[R]	1.729
7	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/endpt0_dat_2_s1/CLEAR	clk_60:[R]	clk_60:[R]	1.729
8	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/endpt0_dat_3_s1/CLEAR	clk_60:[R]	clk_60:[R]	1.729
9	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/endpt0_dat_4_s1/CLEAR	clk_60:[R]	clk_60:[R]	1.729
10	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/endpt0_dat_5_s1/CLEAR	clk_60:[R]	clk_60:[R]	1.729
11	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/endpt0_dat_6_s1/CLEAR	clk_60:[R]	clk_60:[R]	1.729
12	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/endpt0_dat_7_s1/CLEAR	clk_60:[R]	clk_60:[R]	1.729
13	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/endpt0_send_s1/CLEAR	clk_60:[R]	clk_60:[R]	1.729
14	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/sub_stage_0_s1/CLEAR	clk_60:[R]	clk_60:[R]	1.729
15	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/sub_stage_1_s1/CLEAR	clk_60:[R]	clk_60:[R]	1.729
16	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/sub_stage_2_s1/CLEAR	clk_60:[R]	clk_60:[R]	1.729
17	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/sub_stage_3_s1/CLEAR	clk_60:[R]	clk_60:[R]	1.729
18	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/sub_stage_4_s1/CLEAR	clk_60:[R]	clk_60:[R]	1.729
19	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/sub_stage_5_s1/CLEAR	clk_60:[R]	clk_60:[R]	1.729
20	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/sub_stage_6_s1/CLEAR	clk_60:[R]	clk_60:[R]	1.729
21	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/sub_stage_7_s1/CLEAR	clk_60:[R]	clk_60:[R]	1.729
22	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/test_tx_count_0_s1/CLEAR	clk_60:[R]	clk_60:[R]	1.729
23	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/test_tx_count_1_s1/CLEAR	clk_60:[R]	clk_60:[R]	1.729
24	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/test_tx_count_2_s1/CLEAR	clk_60:[R]	clk_60:[R]	1.729
25	1.716	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q	u_usb_uart_config/test_tx_count_3_s1/CLEAR	clk_60:[R]	clk_60:[R]	1.729

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	2.032	3.282	1.250	Low Pulse Width	clk_120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_2_s0
2	2.032	3.282	1.250	Low Pulse Width	clk_120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_1_s0
3	2.032	3.282	1.250	Low Pulse Width	clk_120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_0_s0
4	2.032	3.282	1.250	Low Pulse Width	clk_120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_2_s0
5	2.032	3.282	1.250	Low Pulse Width	clk_120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_1_s0
6	2.032	3.282	1.250	Low Pulse Width	clk_120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_1_s0
7	2.032	3.282	1.250	Low Pulse Width	clk_120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_0_s0
8	2.032	3.282	1.250	Low Pulse Width	clk_120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
9	2.032	3.282	1.250	Low Pulse Width	clk_120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_0_s0
10	2.032	3.282	1.250	Low Pulse Width	clk_120	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_3_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.154
Data Arrival Time	10.757
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s1
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
2.622	2.622	tNET	RR	8	IOT40[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/PCLK
3.297	0.675	tC2Q	RF	5	IOT40[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/Q3
5.573	2.276	tNET	FF	1	R12C36[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s29/I2
6.259	0.686	tINS	FR	1	R12C36[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s29/F
6.261	0.002	tNET	RR	1	R12C36[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s23/I0
6.947	0.686	tINS	RR	1	R12C36[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s23/F
6.949	0.002	tNET	RR	1	R12C36[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s14/I2
7.526	0.577	tINS	RR	1	R12C36[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s14/F
7.742	0.216	tNET	RR	1	R12C35[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s5/I1
8.436	0.694	tINS	RF	5	R12C35[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s5/F
8.945	0.509	tNET	FF	1	R14C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s9/I1
9.657	0.712	tINS	FR	2	R14C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s9/F
9.661	0.003	tNET	RR	1	R14C35[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s13/I2
10.347	0.686	tINS	RR	1	R14C35[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s13/F
10.757	0.410	tNET	RR	1	R13C35[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R13C35[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s1/CLK
10.911	-0.044	tSu		1	R13C35[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 4.043, 49.693%; route: 3.417, 42.009%; tC2Q: 0.675, 8.298%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path2

Path Summary:

Slack	0.219
Data Arrival Time	19.026
Data Required Time	19.245
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_15_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
2.622	2.622	tNET	RR	1	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/CLK
2.912	0.290	tC2Q	RF	46	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q
4.131	1.219	tNET	FF	1	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I0
4.777	0.646	tINS	FF	5	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
5.624	0.847	tNET	FF	1	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
6.318	0.694	tINS	FF	7	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
6.847	0.529	tNET	FF	1	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
7.311	0.464	tINS	FF	4	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
7.327	0.016	tNET	FF	1	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
7.791	0.464	tINS	FF	5	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
8.032	0.241	tNET	FF	1	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
8.718	0.686	tINS	FR	2	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
8.722	0.003	tNET	RR	1	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
9.368	0.646	tINS	RF	10	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
9.697	0.329	tNET	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
10.390	0.694	tINS	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
10.699	0.309	tNET	FF	2	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
11.163	0.464	tINS	FF	1	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
11.163	0.000	tNET	FF	2	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
11.207	0.044	tINS	FF	1	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
11.207	0.000	tNET	FF	2	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
11.251	0.044	tINS	FF	1	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
11.251	0.000	tNET	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
11.838	0.587	tINS	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
12.057	0.219	tNET	FF	1	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
12.751	0.694	tINS	FF	9	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
13.003	0.252	tNET	FF	1	R21C38[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s6/I0
13.697	0.694	tINS	FF	19	R21C38[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s6/F
14.538	0.841	tNET	FF	1	R18C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s10/I3
15.104	0.566	tINS	FF	18	R18C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s10/F
16.446	1.341	tNET	FF	1	R22C37[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1114_s5/I1
17.158	0.712	tINS	FR	1	R22C37[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1114_s5/F
17.160	0.002	tNET	RR	1	R22C37[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1114_s4/I0
17.846	0.686	tINS	RR	1	R22C37[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1114_s4/F
17.848	0.002	tNET	RR	1	R22C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1114_s2/I1
18.560	0.712	tINS	RR	1	R22C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1114_s2/F
18.562	0.002	tNET	RR	1	R22C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1114_s1/I0
19.026	0.464	tINS	RF	1	R22C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1114_s1/F
19.026	0.000	tNET	FF	1	R22C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_15_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_60
16.667	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
19.289	2.622	tNET	RR	1	R22C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_15_s1/CLK
19.245	-0.044	tSu		1	R22C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_15_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	17
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 9.962, 60.727%; route: 6.152, 37.505%; tC2Q: 0.290, 1.768%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path3

Path Summary:

Slack	0.252
Data Arrival Time	10.659
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s1
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
2.622	2.622	tNET	RR	8	IOT40[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/PCLK
3.297	0.675	tC2Q	RF	5	IOT40[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/Q3
5.573	2.276	tNET	FF	1	R12C36[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s29/I2
6.259	0.686	tINS	FR	1	R12C36[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s29/F
6.261	0.002	tNET	RR	1	R12C36[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s23/I0
6.947	0.686	tINS	RR	1	R12C36[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s23/F
6.949	0.002	tNET	RR	1	R12C36[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s14/I2
7.526	0.577	tINS	RR	1	R12C36[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s14/F
7.742	0.216	tNET	RR	1	R12C35[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s5/I1
8.455	0.712	tINS	RR	5	R12C35[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s5/F
8.680	0.225	tNET	RR	1	R13C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s11/I1
9.366	0.686	tINS	RR	1	R13C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s11/F
9.368	0.002	tNET	RR	1	R13C35[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s10/I2
10.080	0.712	tINS	RR	1	R13C35[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s10/F
10.082	0.002	tNET	RR	1	R13C35[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s9/I0
10.659	0.577	tINS	RR	1	R13C35[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s9/F
10.659	0.000	tNET	RR	1	R13C35[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R13C35[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s1/CLK
10.911	-0.044	tSu		1	R13C35[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 4.639, 57.712%; route: 2.724, 33.890%; tC2Q: 0.675, 8.398%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path4

Path Summary:

Slack	0.277
Data Arrival Time	18.968
Data Required Time	19.245
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
2.622	2.622	tNET	RR	1	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/CLK
2.912	0.290	tC2Q	RF	46	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q
4.131	1.219	tNET	FF	1	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I0
4.777	0.646	tINS	FF	5	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
5.624	0.847	tNET	FF	1	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
6.318	0.694	tINS	FF	7	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
6.847	0.529	tNET	FF	1	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
7.311	0.464	tINS	FF	4	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
7.327	0.016	tNET	FF	1	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
7.791	0.464	tINS	FF	5	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
8.032	0.241	tNET	FF	1	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
8.718	0.686	tINS	FR	2	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
8.722	0.003	tNET	RR	1	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
9.368	0.646	tINS	RF	10	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
9.697	0.329	tNET	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
10.390	0.694	tINS	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
10.699	0.309	tNET	FF	2	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
11.163	0.464	tINS	FF	1	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
11.163	0.000	tNET	FF	2	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
11.207	0.044	tINS	FF	1	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
11.207	0.000	tNET	FF	2	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
11.251	0.044	tINS	FF	1	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
11.251	0.000	tNET	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
11.838	0.587	tINS	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
12.057	0.219	tNET	FF	1	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
12.751	0.694	tINS	FF	9	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
13.003	0.252	tNET	FF	1	R21C38[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s6/I0
13.697	0.694	tINS	FF	19	R21C38[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s6/F
14.538	0.841	tNET	FF	1	R18C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s10/I3
15.104	0.566	tINS	FF	18	R18C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s10/F
15.955	0.851	tNET	FF	1	R22C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1112_s6/I1
16.533	0.577	tINS	FR	1	R22C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1112_s6/F
16.748	0.216	tNET	RR	1	R22C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1112_s4/I1
17.461	0.712	tINS	RR	1	R22C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1112_s4/F
17.676	0.216	tNET	RR	1	R21C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1112_s2/I0
18.254	0.577	tINS	RR	1	R21C37[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1112_s2/F
18.256	0.002	tNET	RR	1	R21C37[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1112_s1/I1
18.968	0.712	tINS	RR	1	R21C37[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1112_s1/F
18.968	0.000	tNET	RR	1	R21C37[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_60
16.667	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
19.289	2.622	tNET	RR	1	R21C37[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s1/CLK
19.245	-0.044	tSu		1	R21C37[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	17
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 9.967, 60.972%; route: 6.090, 37.254%; tC2Q: 0.290, 1.774%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path5

Path Summary:

Slack	0.378
Data Arrival Time	10.532
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
2.622	2.622	tNET	RR	8	IOT40[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/PCLK
3.415	0.794	tC2Q	RF	4	IOT40[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/Q6
5.445	2.030	tNET	FF	1	R12C35[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s26/I3
6.022	0.577	tINS	FR	1	R12C35[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s26/F
6.024	0.002	tNET	RR	1	R12C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s20/I0
6.670	0.646	tINS	RF	1	R12C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s20/F
7.167	0.496	tNET	FF	1	R13C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s11/I2
7.879	0.712	tINS	FR	1	R13C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s11/F
7.881	0.002	tNET	RR	1	R13C35[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s4/I0
8.567	0.686	tINS	RR	6	R13C35[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s4/F
8.798	0.231	tNET	RR	1	R14C35[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s11/I1
9.484	0.686	tINS	RR	1	R14C35[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s11/F
9.486	0.002	tNET	RR	1	R14C35[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s10/I2
9.949	0.464	tINS	RF	1	R14C35[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s10/F
9.955	0.005	tNET	FF	1	R14C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s9/I0
10.532	0.577	tINS	FR	1	R14C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s9/F
10.532	0.000	tNET	RR	1	R14C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R14C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1/CLK
10.911	-0.044	tSu		1	R14C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 4.350, 54.988%; route: 2.767, 34.978%; tC2Q: 0.794, 10.034%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path6

Path Summary:

Slack	0.384
Data Arrival Time	10.527
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
2.622	2.622	tNET	RR	8	IOT40[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/PCLK
3.297	0.675	tC2Q	RF	5	IOT40[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/Q3
5.573	2.276	tNET	FF	1	R12C36[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s29/I2
6.259	0.686	tINS	FR	1	R12C36[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s29/F
6.261	0.002	tNET	RR	1	R12C36[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s23/I0
6.947	0.686	tINS	RR	1	R12C36[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s23/F
6.949	0.002	tNET	RR	1	R12C36[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s14/I2
7.526	0.577	tINS	RR	1	R12C36[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s14/F
7.742	0.216	tNET	RR	1	R12C35[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s5/I1
8.436	0.694	tINS	RF	5	R12C35[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s5/F
8.945	0.509	tNET	FF	1	R14C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s9/I1
9.657	0.712	tINS	FR	2	R14C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_1_s9/F
9.661	0.003	tNET	RR	1	R14C35[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s10/I2
10.347	0.686	tINS	RR	1	R14C35[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s10/F
10.527	0.180	tNET	RR	1	R14C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R14C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1/CLK
10.911	-0.044	tSu		1	R14C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 4.043, 51.136%; route: 3.188, 40.325%; tC2Q: 0.675, 8.539%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path7

Path Summary:

Slack	0.472
Data Arrival Time	18.772
Data Required Time	19.245
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_16_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
2.622	2.622	tNET	RR	1	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/CLK
2.912	0.290	tC2Q	RF	46	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q
4.131	1.219	tNET	FF	1	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I0
4.777	0.646	tINS	FF	5	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
5.624	0.847	tNET	FF	1	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
6.318	0.694	tINS	FF	7	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
6.847	0.529	tNET	FF	1	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
7.311	0.464	tINS	FF	4	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
7.327	0.016	tNET	FF	1	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
7.791	0.464	tINS	FF	5	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
8.032	0.241	tNET	FF	1	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
8.718	0.686	tINS	FR	2	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
8.722	0.003	tNET	RR	1	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
9.368	0.646	tINS	RF	10	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
9.697	0.329	tNET	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
10.390	0.694	tINS	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
10.699	0.309	tNET	FF	2	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
11.163	0.464	tINS	FF	1	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
11.163	0.000	tNET	FF	2	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
11.207	0.044	tINS	FF	1	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
11.207	0.000	tNET	FF	2	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
11.251	0.044	tINS	FF	1	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
11.251	0.000	tNET	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
11.838	0.587	tINS	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
12.057	0.219	tNET	FF	1	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
12.751	0.694	tINS	FF	9	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
13.003	0.252	tNET	FF	1	R21C38[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s6/I0
13.697	0.694	tINS	FF	19	R21C38[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s6/F
14.538	0.841	tNET	FF	1	R18C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s10/I3
15.104	0.566	tINS	FF	18	R18C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s10/F
15.955	0.851	tNET	FF	1	R22C38[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1113_s5/I1
16.419	0.464	tINS	FF	1	R22C38[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1113_s5/F
16.424	0.005	tNET	FF	1	R22C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1113_s4/I0
17.002	0.577	tINS	FR	1	R22C38[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1113_s4/F
17.004	0.002	tNET	RR	1	R22C38[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1113_s2/I1
17.570	0.566	tINS	RF	1	R22C38[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1113_s2/F
18.086	0.516	tNET	FF	1	R21C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1113_s1/I0
18.772	0.686	tINS	FR	1	R21C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1113_s1/F
18.772	0.000	tNET	RR	1	R21C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_16_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_60
16.667	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
19.289	2.622	tNET	RR	1	R21C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_16_s1/CLK
19.245	-0.044	tSu		1	R21C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_16_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	17
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 9.680, 59.938%; route: 6.180, 38.266%; tC2Q: 0.290, 1.796%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path8

Path Summary:

Slack	0.563
Data Arrival Time	10.347
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/dru_locked_s2
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
2.622	2.622	tNET	RR	8	IOT40[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/PCLK
3.297	0.675	tC2Q	RF	5	IOT40[A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_a/Q3
5.573	2.276	tNET	FF	1	R12C36[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s29/I2
6.259	0.686	tINS	FR	1	R12C36[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s29/F
6.261	0.002	tNET	RR	1	R12C36[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s23/I0
6.947	0.686	tINS	RR	1	R12C36[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s23/F
6.949	0.002	tNET	RR	1	R12C36[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s14/I2
7.526	0.577	tINS	RR	1	R12C36[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s14/F
7.742	0.216	tNET	RR	1	R12C35[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s5/I1
8.455	0.712	tINS	RR	5	R12C35[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s5/F
8.680	0.225	tNET	RR	1	R13C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s1/I3
9.326	0.646	tINS	RF	1	R13C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s1/F
9.635	0.309	tNET	FF	1	R11C35[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n352_s3/I0
10.347	0.712	tINS	FR	1	R11C35[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n352_s3/F
10.347	0.000	tNET	RR	1	R11C35[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/dru_locked_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R11C35[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/dru_locked_s2/CLK
10.911	-0.044	tSu		1	R11C35[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/dru_locked_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.333
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 4.021, 52.050%; route: 3.030, 39.213%; tC2Q: 0.675, 8.737%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path9

Path Summary:

Slack	0.765
Data Arrival Time	18.480
Data Required Time	19.245
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_2_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_9_s2
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
2.622	2.622	tNET	RR	1	R26C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_2_s0/CLK
2.912	0.290	tC2Q	RF	13	R26C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_2_s0/Q
5.686	2.775	tNET	FF	1	R22C20[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_15_s13/I1
6.150	0.464	tINS	FF	20	R22C20[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_15_s13/F
8.929	2.779	tNET	FF	1	R31C18[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_7_s13/I1
9.616	0.686	tINS	FR	1	R31C18[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_7_s13/F
9.831	0.216	tNET	RR	1	R32C18[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_7_s9/I2
10.544	0.712	tINS	RR	1	R32C18[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_7_s9/F
10.759	0.216	tNET	RR	1	R32C17[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_7_s8/I0
11.453	0.694	tINS	RF	2	R32C17[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_7_s8/F
12.260	0.807	tNET	FF	2	R30C19[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1416_s0/I1
12.972	0.712	tINS	FR	1	R30C19[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1416_s0/COUT
12.972	0.000	tNET	RR	2	R30C19[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1417_s0/CIN
13.016	0.044	tINS	RF	1	R30C19[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1417_s0/COUT
13.016	0.000	tNET	FF	2	R30C19[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1418_s0/CIN
13.060	0.044	tINS	FF	1	R30C19[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1418_s0/COUT
13.060	0.000	tNET	FF	2	R30C19[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1419_s0/CIN
13.104	0.044	tINS	FF	1	R30C19[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1419_s0/COUT
13.104	0.000	tNET	FF	2	R30C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1420_s0/CIN
13.148	0.044	tINS	FF	1	R30C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1420_s0/COUT
13.148	0.000	tNET	FF	2	R30C20[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1421_s0/CIN
13.192	0.044	tINS	FF	1	R30C20[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1421_s0/COUT
13.192	0.000	tNET	FF	2	R30C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1422_s0/CIN
13.236	0.044	tINS	FF	1	R30C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1422_s0/COUT
13.236	0.000	tNET	FF	2	R30C20[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1423_s0/CIN
13.280	0.044	tINS	FF	1	R30C20[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1423_s0/COUT
13.280	0.000	tNET	FF	2	R30C20[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1424_s0/CIN
13.324	0.044	tINS	FF	3	R30C20[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1424_s0/COUT
14.974	1.650	tNET	FF	1	R30C12[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1688_s39/I2
15.541	0.566	tINS	FF	3	R30C12[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1688_s39/F
16.373	0.833	tNET	FF	1	R29C15[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1686_s44/I0
17.059	0.686	tINS	FR	1	R29C15[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1686_s44/F
17.061	0.002	tNET	RR	1	R29C15[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1686_s40/I0
17.707	0.646	tINS	RF	1	R29C15[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1686_s40/F
18.016	0.309	tNET	FF	1	R31C15[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1686_s37/I2
18.480	0.464	tINS	FF	1	R31C15[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1686_s37/F
18.480	0.000	tNET	FF	1	R31C15[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_9_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_60
16.667	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
19.289	2.622	tNET	RR	1	R31C15[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_9_s2/CLK
19.245	-0.044	tSu		1	R31C15[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_9_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	12
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 5.983, 37.729%; route: 9.585, 60.442%; tC2Q: 0.290, 1.829%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path10

Path Summary:

Slack	0.807
Data Arrival Time	18.438
Data Required Time	19.245
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_3_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
2.622	2.622	tNET	RR	1	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/CLK
2.912	0.290	tC2Q	RF	46	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q
4.131	1.219	tNET	FF	1	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I0
4.777	0.646	tINS	FF	5	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
5.624	0.847	tNET	FF	1	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
6.318	0.694	tINS	FF	7	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
6.847	0.529	tNET	FF	1	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
7.311	0.464	tINS	FF	4	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
7.327	0.016	tNET	FF	1	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
7.791	0.464	tINS	FF	5	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
8.032	0.241	tNET	FF	1	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
8.718	0.686	tINS	FR	2	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
8.722	0.003	tNET	RR	1	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
9.368	0.646	tINS	RF	10	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
9.697	0.329	tNET	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
10.390	0.694	tINS	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
10.699	0.309	tNET	FF	2	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
11.163	0.464	tINS	FF	1	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
11.163	0.000	tNET	FF	2	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
11.207	0.044	tINS	FF	1	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
11.207	0.000	tNET	FF	2	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
11.251	0.044	tINS	FF	1	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
11.251	0.000	tNET	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
11.838	0.587	tINS	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
12.057	0.219	tNET	FF	1	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
12.751	0.694	tINS	FF	9	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
13.511	0.760	tNET	FF	1	R21C40[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/I0
14.077	0.566	tINS	FF	22	R21C40[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/F
14.950	0.872	tNET	FF	1	R18C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/I3
15.516	0.566	tINS	FF	15	R18C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/F
16.388	0.872	tNET	FF	1	R16C37[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1050_s13/I2
17.100	0.712	tINS	FR	1	R16C37[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1050_s13/F
17.100	0.000	tNET	RR	1	R16C37[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1050_s9/I0
17.231	0.131	tINS	RR	1	R16C37[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1050_s9/O
17.231	0.000	tNET	RR	1	R16C37[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1050_s5/I0
17.363	0.131	tINS	RR	1	R16C37[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1050_s5/O
17.586	0.223	tNET	RR	1	R16C37[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1126_s7/I0
18.298	0.712	tINS	RR	1	R16C37[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1126_s7/F
18.298	0.000	tNET	RR	1	R16C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1126_s4/I1
18.429	0.131	tINS	RR	1	R16C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1126_s4/O
18.438	0.009	tNET	RR	1	R16C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_60
16.667	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
19.289	2.622	tNET	RR	1	R16C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_3_s1/CLK
19.245	-0.044	tSu		1	R16C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 9.078, 57.395%; route: 6.449, 40.771%; tC2Q: 0.290, 1.834%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path11

Path Summary:

Slack	0.819
Data Arrival Time	18.426
Data Required Time	19.245
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_endpt_2_s0
To	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_12_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
2.622	2.622	tNET	RR	1	R16C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_endpt_2_s0/CLK
2.912	0.290	tC2Q	RF	32	R16C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_endpt_2_s0/Q
5.480	2.568	tNET	FF	1	R23C19[3][A]	usb_rxrdy_s1/I2
6.166	0.686	tINS	FR	28	R23C19[3][A]	usb_rxrdy_s1/F
6.387	0.221	tNET	RR	1	R24C19[3][B]	n394_s0/I1
7.033	0.646	tINS	RF	10	R24C19[3][B]	n394_s0/F
8.866	1.833	tNET	FF	1	R17C14[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s3/I0
9.330	0.464	tINS	FF	2	R17C14[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s3/F
9.948	0.618	tNET	FF	1	R17C18[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s/I1
10.411	0.464	tINS	FF	18	R17C18[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s/F
13.803	3.392	tNET	FF	1	R26C38[0][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n85_s0/I0
14.267	0.464	tINS	FF	5	R26C38[0][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n85_s0/F
14.806	0.539	tNET	FF	1	R27C39[3][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n122_s2/I3
15.270	0.464	tINS	FF	6	R27C39[3][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n122_s2/F
15.505	0.235	tNET	FF	1	R27C38[2][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n113_s3/I3
16.199	0.694	tINS	FF	3	R27C38[2][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n113_s3/F
17.026	0.827	tNET	FF	1	R29C37[1][B]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n113_s2/I2
17.712	0.686	tINS	FR	1	R29C37[1][B]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n113_s2/F
17.714	0.002	tNET	RR	1	R29C37[0][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n113_s0/I1
18.426	0.712	tINS	RR	1	R29C37[0][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n113_s0/F
18.426	0.000	tNET	RR	1	R29C37[0][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_12_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_60
16.667	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
19.289	2.622	tNET	RR	1	R29C37[0][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_12_s1/CLK
19.245	-0.044	tSu		1	R29C37[0][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_12_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 5.280, 33.409%; route: 10.234, 64.757%; tC2Q: 0.290, 1.835%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path12

Path Summary:

Slack	0.942
Data Arrival Time	18.303
Data Required Time	19.245
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_8_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
2.622	2.622	tNET	RR	1	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/CLK
2.912	0.290	tC2Q	RF	46	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q
4.131	1.219	tNET	FF	1	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I0
4.777	0.646	tINS	FF	5	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
5.624	0.847	tNET	FF	1	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
6.318	0.694	tINS	FF	7	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
6.847	0.529	tNET	FF	1	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
7.311	0.464	tINS	FF	4	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
7.327	0.016	tNET	FF	1	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
7.791	0.464	tINS	FF	5	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
8.032	0.241	tNET	FF	1	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
8.718	0.686	tINS	FR	2	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
8.722	0.003	tNET	RR	1	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
9.368	0.646	tINS	RF	10	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
9.697	0.329	tNET	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
10.390	0.694	tINS	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
10.699	0.309	tNET	FF	2	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
11.163	0.464	tINS	FF	1	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
11.163	0.000	tNET	FF	2	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
11.207	0.044	tINS	FF	1	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
11.207	0.000	tNET	FF	2	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
11.251	0.044	tINS	FF	1	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
11.251	0.000	tNET	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
11.838	0.587	tINS	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
12.057	0.219	tNET	FF	1	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
12.751	0.694	tINS	FF	9	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
13.511	0.760	tNET	FF	1	R21C40[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/I0
14.077	0.566	tINS	FF	22	R21C40[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/F
14.950	0.872	tNET	FF	1	R18C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/I3
15.516	0.566	tINS	FF	15	R18C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/F
16.388	0.872	tNET	FF	1	R20C41[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1045_s13/I2
17.100	0.712	tINS	FR	1	R20C41[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1045_s13/F
17.100	0.000	tNET	RR	1	R20C41[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1045_s9/I0
17.231	0.131	tINS	RR	1	R20C41[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1045_s9/O
17.231	0.000	tNET	RR	1	R20C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1045_s5/I0
17.363	0.131	tINS	RR	1	R20C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1045_s5/O
17.586	0.223	tNET	RR	1	R20C40[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1121_s7/I0
18.163	0.577	tINS	RR	1	R20C40[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1121_s7/F
18.163	0.000	tNET	RR	1	R20C40[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1121_s4/I1
18.294	0.131	tINS	RR	1	R20C40[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1121_s4/O
18.303	0.009	tNET	RR	1	R20C40[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_60
16.667	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
19.289	2.622	tNET	RR	1	R20C40[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_8_s1/CLK
19.245	-0.044	tSu		1	R20C40[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_8_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 8.943, 57.029%; route: 6.449, 41.122%; tC2Q: 0.290, 1.849%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path13

Path Summary:

Slack	0.967
Data Arrival Time	18.278
Data Required Time	19.245
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_10_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
2.622	2.622	tNET	RR	1	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/CLK
2.912	0.290	tC2Q	RF	46	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q
4.131	1.219	tNET	FF	1	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I0
4.777	0.646	tINS	FF	5	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
5.624	0.847	tNET	FF	1	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
6.318	0.694	tINS	FF	7	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
6.847	0.529	tNET	FF	1	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
7.311	0.464	tINS	FF	4	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
7.327	0.016	tNET	FF	1	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
7.791	0.464	tINS	FF	5	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
8.032	0.241	tNET	FF	1	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
8.718	0.686	tINS	FR	2	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
8.722	0.003	tNET	RR	1	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
9.368	0.646	tINS	RF	10	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
9.697	0.329	tNET	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
10.390	0.694	tINS	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
10.699	0.309	tNET	FF	2	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
11.163	0.464	tINS	FF	1	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
11.163	0.000	tNET	FF	2	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
11.207	0.044	tINS	FF	1	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
11.207	0.000	tNET	FF	2	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
11.251	0.044	tINS	FF	1	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
11.251	0.000	tNET	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
11.838	0.587	tINS	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
12.057	0.219	tNET	FF	1	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
12.751	0.694	tINS	FF	9	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
13.511	0.760	tNET	FF	1	R21C40[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/I0
14.077	0.566	tINS	FF	22	R21C40[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/F
14.950	0.872	tNET	FF	1	R18C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/I3
15.516	0.566	tINS	FF	15	R18C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/F
16.245	0.729	tNET	FF	1	R18C41[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1043_s13/I2
16.891	0.646	tINS	FF	1	R18C41[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1043_s13/F
16.891	0.000	tNET	FF	1	R18C41[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1043_s9/I0
17.020	0.129	tINS	FF	1	R18C41[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1043_s9/O
17.020	0.000	tNET	FF	1	R18C41[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1043_s5/I0
17.149	0.129	tINS	FF	1	R18C41[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1043_s5/O
17.672	0.524	tNET	FF	1	R18C38[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1119_s7/I0
18.136	0.464	tINS	FF	1	R18C38[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1119_s7/F
18.136	0.000	tNET	FF	1	R18C38[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1119_s4/I1
18.265	0.129	tINS	FF	1	R18C38[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1119_s4/O
18.278	0.013	tNET	FF	1	R18C38[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_10_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_60
16.667	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
19.289	2.622	tNET	RR	1	R18C38[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_10_s1/CLK
19.245	-0.044	tSu		1	R18C38[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_10_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 8.755, 55.925%; route: 6.610, 42.223%; tC2Q: 0.290, 1.852%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path14

Path Summary:

Slack	0.975
Data Arrival Time	18.269
Data Required Time	19.245
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_endpt_2_s0
To	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_10_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
2.622	2.622	tNET	RR	1	R16C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_endpt_2_s0/CLK
2.912	0.290	tC2Q	RF	32	R16C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_endpt_2_s0/Q
5.480	2.568	tNET	FF	1	R23C19[3][A]	usb_rxrdy_s1/I2
6.166	0.686	tINS	FR	28	R23C19[3][A]	usb_rxrdy_s1/F
6.387	0.221	tNET	RR	1	R24C19[3][B]	n394_s0/I1
7.033	0.646	tINS	RF	10	R24C19[3][B]	n394_s0/F
8.866	1.833	tNET	FF	1	R17C14[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s3/I0
9.330	0.464	tINS	FF	2	R17C14[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s3/F
9.948	0.618	tNET	FF	1	R17C18[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s/I1
10.411	0.464	tINS	FF	18	R17C18[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s/F
13.803	3.392	tNET	FF	1	R26C38[0][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n85_s0/I0
14.267	0.464	tINS	FF	5	R26C38[0][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n85_s0/F
14.806	0.539	tNET	FF	1	R27C39[3][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n122_s2/I3
15.270	0.464	tINS	FF	6	R27C39[3][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n122_s2/F
15.505	0.235	tNET	FF	1	R27C38[2][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n113_s3/I3
16.199	0.694	tINS	FF	3	R27C38[2][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n113_s3/F
17.223	1.024	tNET	FF	1	R29C37[2][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n115_s1/I1
17.686	0.464	tINS	FF	1	R29C37[2][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n115_s1/F
17.692	0.005	tNET	FF	1	R29C37[0][B]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n115_s0/I0
18.269	0.577	tINS	FR	1	R29C37[0][B]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n115_s0/F
18.269	0.000	tNET	RR	1	R29C37[0][B]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_10_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_60
16.667	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
19.289	2.622	tNET	RR	1	R29C37[0][B]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_10_s1/CLK
19.245	-0.044	tSu		1	R29C37[0][B]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_10_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 4.922, 31.458%; route: 10.435, 66.689%; tC2Q: 0.290, 1.853%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path15

Path Summary:

Slack	0.975
Data Arrival Time	18.269
Data Required Time	19.245
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_endpt_2_s0
To	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_11_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
2.622	2.622	tNET	RR	1	R16C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_endpt_2_s0/CLK
2.912	0.290	tC2Q	RF	32	R16C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_endpt_2_s0/Q
5.480	2.568	tNET	FF	1	R23C19[3][A]	usb_rxrdy_s1/I2
6.166	0.686	tINS	FR	28	R23C19[3][A]	usb_rxrdy_s1/F
6.387	0.221	tNET	RR	1	R24C19[3][B]	n394_s0/I1
7.033	0.646	tINS	RF	10	R24C19[3][B]	n394_s0/F
8.866	1.833	tNET	FF	1	R17C14[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s3/I0
9.330	0.464	tINS	FF	2	R17C14[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s3/F
9.948	0.618	tNET	FF	1	R17C18[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s/I1
10.411	0.464	tINS	FF	18	R17C18[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s/F
13.803	3.392	tNET	FF	1	R26C38[0][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n85_s0/I0
14.267	0.464	tINS	FF	5	R26C38[0][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n85_s0/F
14.806	0.539	tNET	FF	1	R27C39[3][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n122_s2/I3
15.270	0.464	tINS	FF	6	R27C39[3][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n122_s2/F
15.505	0.235	tNET	FF	1	R27C38[2][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n113_s3/I3
16.199	0.694	tINS	FF	3	R27C38[2][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n113_s3/F
17.223	1.024	tNET	FF	1	R29C37[3][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n114_s2/I1
17.686	0.464	tINS	FF	1	R29C37[3][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n114_s2/F
17.692	0.005	tNET	FF	1	R29C37[1][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n114_s0/I1
18.269	0.577	tINS	FR	1	R29C37[1][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n114_s0/F
18.269	0.000	tNET	RR	1	R29C37[1][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_11_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_60
16.667	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
19.289	2.622	tNET	RR	1	R29C37[1][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_11_s1/CLK
19.245	-0.044	tSu		1	R29C37[1][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_11_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 4.922, 31.458%; route: 10.435, 66.689%; tC2Q: 0.290, 1.853%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path16

Path Summary:

Slack	0.987
Data Arrival Time	18.257
Data Required Time	19.245
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_14_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
2.622	2.622	tNET	RR	1	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/CLK
2.912	0.290	tC2Q	RF	46	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q
4.131	1.219	tNET	FF	1	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I0
4.777	0.646	tINS	FF	5	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
5.624	0.847	tNET	FF	1	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
6.318	0.694	tINS	FF	7	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
6.847	0.529	tNET	FF	1	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
7.311	0.464	tINS	FF	4	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
7.327	0.016	tNET	FF	1	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
7.791	0.464	tINS	FF	5	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
8.032	0.241	tNET	FF	1	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
8.718	0.686	tINS	FR	2	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
8.722	0.003	tNET	RR	1	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
9.368	0.646	tINS	RF	10	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
9.697	0.329	tNET	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
10.390	0.694	tINS	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
10.699	0.309	tNET	FF	2	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
11.163	0.464	tINS	FF	1	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
11.163	0.000	tNET	FF	2	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
11.207	0.044	tINS	FF	1	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
11.207	0.000	tNET	FF	2	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
11.251	0.044	tINS	FF	1	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
11.251	0.000	tNET	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
11.838	0.587	tINS	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
12.057	0.219	tNET	FF	1	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
12.751	0.694	tINS	FF	9	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
13.511	0.760	tNET	FF	1	R21C40[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/I0
14.077	0.566	tINS	FF	22	R21C40[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/F
14.950	0.872	tNET	FF	1	R18C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/I3
15.516	0.566	tINS	FF	15	R18C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/F
16.368	0.852	tNET	FF	1	R18C42[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s18/I2
17.054	0.686	tINS	FR	1	R18C42[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s18/F
17.054	0.000	tNET	RR	1	R18C42[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s14/I0
17.186	0.131	tINS	RR	1	R18C42[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s14/O
17.186	0.000	tNET	RR	1	R18C42[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s5/I0
17.317	0.131	tINS	RR	1	R18C42[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s5/O
17.540	0.223	tNET	RR	1	R18C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1115_s10/I0
18.117	0.577	tINS	RR	1	R18C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1115_s10/F
18.117	0.000	tNET	RR	1	R18C41[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1115_s4/I1
18.249	0.131	tINS	RR	1	R18C41[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1115_s4/O
18.257	0.009	tNET	RR	1	R18C41[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_14_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_60
16.667	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
19.289	2.622	tNET	RR	1	R18C41[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_14_s1/CLK
19.245	-0.044	tSu		1	R18C41[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_14_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 8.917, 57.028%; route: 6.429, 41.117%; tC2Q: 0.290, 1.855%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path17

Path Summary:

Slack	0.994
Data Arrival Time	18.251
Data Required Time	19.245
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_0_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
2.622	2.622	tNET	RR	1	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/CLK
2.912	0.290	tC2Q	RF	46	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q
4.131	1.219	tNET	FF	1	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I0
4.777	0.646	tINS	FF	5	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
5.624	0.847	tNET	FF	1	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
6.318	0.694	tINS	FF	7	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
6.847	0.529	tNET	FF	1	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
7.311	0.464	tINS	FF	4	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
7.327	0.016	tNET	FF	1	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
7.791	0.464	tINS	FF	5	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
8.032	0.241	tNET	FF	1	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
8.718	0.686	tINS	FR	2	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
8.722	0.003	tNET	RR	1	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
9.368	0.646	tINS	RF	10	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
9.697	0.329	tNET	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
10.390	0.694	tINS	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
10.699	0.309	tNET	FF	2	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
11.163	0.464	tINS	FF	1	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
11.163	0.000	tNET	FF	2	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
11.207	0.044	tINS	FF	1	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
11.207	0.000	tNET	FF	2	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
11.251	0.044	tINS	FF	1	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
11.251	0.000	tNET	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
11.838	0.587	tINS	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
12.057	0.219	tNET	FF	1	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
12.751	0.694	tINS	FF	9	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
13.511	0.760	tNET	FF	1	R21C40[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/I0
14.077	0.566	tINS	FF	22	R21C40[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/F
14.950	0.872	tNET	FF	1	R18C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/I3
15.516	0.566	tINS	FF	15	R18C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/F
16.361	0.845	tNET	FF	1	R17C41[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1053_s14/I2
16.825	0.464	tINS	FF	1	R17C41[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1053_s14/F
16.825	0.000	tNET	FF	1	R17C41[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1053_s10/I0
16.953	0.129	tINS	FF	1	R17C41[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1053_s10/O
16.953	0.000	tNET	FF	1	R17C41[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1053_s5/I0
17.082	0.129	tINS	FF	1	R17C41[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1053_s5/O
17.398	0.316	tNET	FF	1	R17C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1129_s7/I0
18.111	0.712	tINS	FR	1	R17C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1129_s7/F
18.111	0.000	tNET	RR	1	R17C41[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1129_s4/I1
18.242	0.131	tINS	RR	1	R17C41[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1129_s4/O
18.251	0.009	tNET	RR	1	R17C41[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_60
16.667	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
19.289	2.622	tNET	RR	1	R17C41[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_0_s1/CLK
19.245	-0.044	tSu		1	R17C41[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 8.824, 56.459%; route: 6.515, 41.685%; tC2Q: 0.290, 1.855%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path18

Path Summary:

Slack	1.054
Data Arrival Time	18.191
Data Required Time	19.245
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_11_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
2.622	2.622	tNET	RR	1	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/CLK
2.912	0.290	tC2Q	RF	46	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q
4.131	1.219	tNET	FF	1	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I0
4.777	0.646	tINS	FF	5	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
5.624	0.847	tNET	FF	1	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
6.318	0.694	tINS	FF	7	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
6.847	0.529	tNET	FF	1	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
7.311	0.464	tINS	FF	4	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
7.327	0.016	tNET	FF	1	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
7.791	0.464	tINS	FF	5	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
8.032	0.241	tNET	FF	1	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
8.718	0.686	tINS	FR	2	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
8.722	0.003	tNET	RR	1	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
9.368	0.646	tINS	RF	10	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
9.697	0.329	tNET	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
10.390	0.694	tINS	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
10.699	0.309	tNET	FF	2	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
11.163	0.464	tINS	FF	1	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
11.163	0.000	tNET	FF	2	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
11.207	0.044	tINS	FF	1	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
11.207	0.000	tNET	FF	2	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
11.251	0.044	tINS	FF	1	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
11.251	0.000	tNET	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
11.838	0.587	tINS	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
12.057	0.219	tNET	FF	1	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
12.751	0.694	tINS	FF	9	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
13.511	0.760	tNET	FF	1	R21C40[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/I0
14.077	0.566	tINS	FF	22	R21C40[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/F
14.950	0.872	tNET	FF	1	R18C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/I3
15.516	0.566	tINS	FF	15	R18C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/F
16.388	0.872	tNET	FF	1	R20C41[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1042_s13/I2
17.100	0.712	tINS	FR	1	R20C41[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1042_s13/F
17.100	0.000	tNET	RR	1	R20C41[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1042_s9/I0
17.231	0.131	tINS	RR	1	R20C41[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1042_s9/O
17.231	0.000	tNET	RR	1	R20C41[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1042_s5/I0
17.363	0.131	tINS	RR	1	R20C41[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1042_s5/O
17.586	0.223	tNET	RR	1	R20C40[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1118_s7/I0
18.049	0.464	tINS	RF	1	R20C40[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1118_s7/F
18.049	0.000	tNET	FF	1	R20C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1118_s4/I1
18.178	0.129	tINS	FF	1	R20C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1118_s4/O
18.191	0.013	tNET	FF	1	R20C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_11_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_60
16.667	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
19.289	2.622	tNET	RR	1	R20C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_11_s1/CLK
19.245	-0.044	tSu		1	R20C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_11_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 8.827, 56.694%; route: 6.452, 41.444%; tC2Q: 0.290, 1.863%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path19

Path Summary:

Slack	1.091
Data Arrival Time	18.154
Data Required Time	19.245
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_endpt_2_s0
To	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_10_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
2.622	2.622	tNET	RR	1	R16C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_endpt_2_s0/CLK
2.912	0.290	tC2Q	RF	32	R16C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_endpt_2_s0/Q
5.480	2.568	tNET	FF	1	R23C19[3][A]	usb_rxrdy_s1/I2
6.166	0.686	tINS	FR	28	R23C19[3][A]	usb_rxrdy_s1/F
6.387	0.221	tNET	RR	1	R24C19[3][B]	n394_s0/I1
7.033	0.646	tINS	RF	10	R24C19[3][B]	n394_s0/F
8.866	1.833	tNET	FF	1	R17C14[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s3/I0
9.330	0.464	tINS	FF	2	R17C14[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s3/F
9.948	0.618	tNET	FF	1	R17C18[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s/I1
10.411	0.464	tINS	FF	18	R17C18[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s/F
12.878	2.467	tNET	FF	1	R26C33[3][A]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n85_s0/I0
13.572	0.694	tINS	FF	5	R26C33[3][A]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n85_s0/F
14.311	0.739	tNET	FF	1	R27C32[3][B]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n122_s2/I3
15.005	0.694	tINS	FF	4	R27C32[3][B]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n122_s2/F
15.332	0.327	tNET	FF	1	R26C32[3][B]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n119_s2/I3
16.026	0.694	tINS	FF	7	R26C32[3][B]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n119_s2/F
16.780	0.754	tNET	FF	1	R27C31[2][B]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n115_s1/I1
17.466	0.686	tINS	FR	1	R27C31[2][B]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n115_s1/F
17.468	0.002	tNET	RR	1	R27C31[1][A]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n115_s0/I0
18.154	0.686	tINS	RR	1	R27C31[1][A]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n115_s0/F
18.154	0.000	tNET	RR	1	R27C31[1][A]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_10_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_60
16.667	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
19.289	2.622	tNET	RR	1	R27C31[1][A]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_10_s1/CLK
19.245	-0.044	tSu		1	R27C31[1][A]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_10_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 5.714, 36.786%; route: 9.529, 61.347%; tC2Q: 0.290, 1.867%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path20

Path Summary:

Slack	1.095
Data Arrival Time	18.150
Data Required Time	19.245
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_1_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
2.622	2.622	tNET	RR	1	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/CLK
2.912	0.290	tC2Q	RF	46	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q
4.131	1.219	tNET	FF	1	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I0
4.777	0.646	tINS	FF	5	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
5.624	0.847	tNET	FF	1	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
6.318	0.694	tINS	FF	7	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
6.847	0.529	tNET	FF	1	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
7.311	0.464	tINS	FF	4	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
7.327	0.016	tNET	FF	1	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
7.791	0.464	tINS	FF	5	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
8.032	0.241	tNET	FF	1	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
8.718	0.686	tINS	FR	2	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
8.722	0.003	tNET	RR	1	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
9.368	0.646	tINS	RF	10	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
9.697	0.329	tNET	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
10.390	0.694	tINS	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
10.699	0.309	tNET	FF	2	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
11.163	0.464	tINS	FF	1	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
11.163	0.000	tNET	FF	2	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
11.207	0.044	tINS	FF	1	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
11.207	0.000	tNET	FF	2	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
11.251	0.044	tINS	FF	1	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
11.251	0.000	tNET	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
11.838	0.587	tINS	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
12.057	0.219	tNET	FF	1	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
12.751	0.694	tINS	FF	9	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
13.511	0.760	tNET	FF	1	R21C40[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/I0
14.077	0.566	tINS	FF	22	R21C40[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/F
14.950	0.872	tNET	FF	1	R18C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/I3
15.516	0.566	tINS	FF	15	R18C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/F
16.077	0.561	tNET	FF	1	R16C39[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1052_s13/I2
16.723	0.646	tINS	FF	1	R16C39[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1052_s13/F
16.723	0.000	tNET	FF	1	R16C39[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1052_s9/I0
16.852	0.129	tINS	FF	1	R16C39[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1052_s9/O
16.852	0.000	tNET	FF	1	R16C39[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1052_s5/I0
16.981	0.129	tINS	FF	1	R16C39[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1052_s5/O
17.297	0.316	tNET	FF	1	R16C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1128_s7/I0
18.010	0.712	tINS	FR	1	R16C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1128_s7/F
18.010	0.000	tNET	RR	1	R16C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1128_s4/I1
18.141	0.131	tINS	RR	1	R16C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1128_s4/O
18.150	0.009	tNET	RR	1	R16C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_60
16.667	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
19.289	2.622	tNET	RR	1	R16C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_1_s1/CLK
19.245	-0.044	tSu		1	R16C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 9.007, 58.003%; route: 6.231, 40.129%; tC2Q: 0.290, 1.868%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path21

Path Summary:

Slack	1.095
Data Arrival Time	18.150
Data Required Time	19.245
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_2_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
2.622	2.622	tNET	RR	1	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/CLK
2.912	0.290	tC2Q	RF	46	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q
4.131	1.219	tNET	FF	1	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I0
4.777	0.646	tINS	FF	5	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
5.624	0.847	tNET	FF	1	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
6.318	0.694	tINS	FF	7	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
6.847	0.529	tNET	FF	1	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
7.311	0.464	tINS	FF	4	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
7.327	0.016	tNET	FF	1	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
7.791	0.464	tINS	FF	5	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
8.032	0.241	tNET	FF	1	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
8.718	0.686	tINS	FR	2	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
8.722	0.003	tNET	RR	1	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
9.368	0.646	tINS	RF	10	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
9.697	0.329	tNET	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
10.390	0.694	tINS	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
10.699	0.309	tNET	FF	2	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
11.163	0.464	tINS	FF	1	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
11.163	0.000	tNET	FF	2	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
11.207	0.044	tINS	FF	1	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
11.207	0.000	tNET	FF	2	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
11.251	0.044	tINS	FF	1	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
11.251	0.000	tNET	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
11.838	0.587	tINS	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
12.057	0.219	tNET	FF	1	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
12.751	0.694	tINS	FF	9	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
13.511	0.760	tNET	FF	1	R21C40[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/I0
14.077	0.566	tINS	FF	22	R21C40[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/F
14.950	0.872	tNET	FF	1	R18C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/I3
15.516	0.566	tINS	FF	15	R18C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/F
16.077	0.561	tNET	FF	1	R17C40[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1051_s13/I2
16.723	0.646	tINS	FF	1	R17C40[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1051_s13/F
16.723	0.000	tNET	FF	1	R17C40[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1051_s9/I0
16.852	0.129	tINS	FF	1	R17C40[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1051_s9/O
16.852	0.000	tNET	FF	1	R17C40[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1051_s5/I0
16.981	0.129	tINS	FF	1	R17C40[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1051_s5/O
17.297	0.316	tNET	FF	1	R17C40[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1127_s7/I0
18.010	0.712	tINS	FR	1	R17C40[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1127_s7/F
18.010	0.000	tNET	RR	1	R17C40[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1127_s4/I1
18.141	0.131	tINS	RR	1	R17C40[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1127_s4/O
18.150	0.009	tNET	RR	1	R17C40[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_60
16.667	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
19.289	2.622	tNET	RR	1	R17C40[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_2_s1/CLK
19.245	-0.044	tSu		1	R17C40[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 9.007, 58.003%; route: 6.231, 40.129%; tC2Q: 0.290, 1.868%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path22

Path Summary:

Slack	1.100
Data Arrival Time	18.145
Data Required Time	19.245
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_13_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
2.622	2.622	tNET	RR	1	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/CLK
2.912	0.290	tC2Q	RF	46	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q
4.131	1.219	tNET	FF	1	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I0
4.777	0.646	tINS	FF	5	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
5.624	0.847	tNET	FF	1	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
6.318	0.694	tINS	FF	7	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
6.847	0.529	tNET	FF	1	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
7.311	0.464	tINS	FF	4	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
7.327	0.016	tNET	FF	1	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
7.791	0.464	tINS	FF	5	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
8.032	0.241	tNET	FF	1	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
8.718	0.686	tINS	FR	2	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
8.722	0.003	tNET	RR	1	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
9.368	0.646	tINS	RF	10	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
9.697	0.329	tNET	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
10.390	0.694	tINS	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
10.699	0.309	tNET	FF	2	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
11.163	0.464	tINS	FF	1	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
11.163	0.000	tNET	FF	2	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
11.207	0.044	tINS	FF	1	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
11.207	0.000	tNET	FF	2	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
11.251	0.044	tINS	FF	1	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/COUT
11.251	0.000	tNET	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/CIN
11.838	0.587	tINS	FF	2	R20C39[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n614_s/SUM
12.057	0.219	tNET	FF	1	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/I0
12.751	0.694	tINS	FF	9	R20C38[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s5/F
13.511	0.760	tNET	FF	1	R21C40[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/I0
14.077	0.566	tINS	FF	22	R21C40[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s9/F
14.950	0.872	tNET	FF	1	R18C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/I3
15.516	0.566	tINS	FF	15	R18C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1039_s13/F
16.368	0.852	tNET	FF	1	R18C42[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1040_s13/I2
17.054	0.686	tINS	FR	1	R18C42[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1040_s13/F
17.054	0.000	tNET	RR	1	R18C42[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1040_s9/I0
17.186	0.131	tINS	RR	1	R18C42[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1040_s9/O
17.186	0.000	tNET	RR	1	R18C42[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1040_s5/I0
17.317	0.131	tINS	RR	1	R18C42[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1040_s5/O
17.540	0.223	tNET	RR	1	R18C41[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1116_s7/I0
18.004	0.464	tINS	RF	1	R18C41[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1116_s7/F
18.004	0.000	tNET	FF	1	R18C41[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1116_s4/I1
18.132	0.129	tINS	FF	1	R18C41[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1116_s4/O
18.145	0.013	tNET	FF	1	R18C41[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_13_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_60
16.667	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
19.289	2.622	tNET	RR	1	R18C41[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_13_s1/CLK
19.245	-0.044	tSu		1	R18C41[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_13_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 8.800, 56.692%; route: 6.433, 41.440%; tC2Q: 0.290, 1.868%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path23

Path Summary:

Slack	1.106
Data Arrival Time	18.139
Data Required Time	19.245
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_4_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
2.622	2.622	tNET	RR	1	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/CLK
2.912	0.290	tC2Q	RF	46	R22C40[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/state_1_s3/Q
4.131	1.219	tNET	FF	1	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/I0
4.777	0.646	tINS	FF	5	R20C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s7/F
5.624	0.847	tNET	FF	1	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/I3
6.318	0.694	tINS	FF	7	R18C35[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1205_s4/F
6.847	0.529	tNET	FF	1	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/I2
7.311	0.464	tINS	FF	4	R20C36[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n752_s2/F
7.327	0.016	tNET	FF	1	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/I2
7.791	0.464	tINS	FF	5	R20C36[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n716_s6/F
8.032	0.241	tNET	FF	1	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/I0
8.718	0.686	tINS	FR	2	R20C35[3][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s3/F
8.722	0.003	tNET	RR	1	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/I3
9.368	0.646	tINS	RF	10	R20C35[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s0/F
9.697	0.329	tNET	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/I0
10.390	0.694	tINS	FF	1	R20C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s6/F
10.699	0.309	tNET	FF	2	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/I1
11.163	0.464	tINS	FF	1	R20C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n617_s/COUT
11.163	0.000	tNET	FF	2	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/CIN
11.207	0.044	tINS	FF	1	R20C39[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n616_s/COUT
11.207	0.000	tNET	FF	2	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/CIN
11.794	0.587	tINS	FF	2	R20C39[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n615_s/SUM
12.019	0.224	tNET	FF	1	R21C39[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s9/I1
12.585	0.566	tINS	FF	6	R21C39[3][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n963_s9/F
12.601	0.016	tNET	FF	1	R21C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s6/I3
13.168	0.566	tINS	FF	4	R21C39[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_17_s6/F
13.712	0.545	tNET	FF	1	R22C40[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n925_s2/I1
14.359	0.646	tINS	FF	18	R22C40[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n925_s2/F
16.114	1.756	tNET	FF	1	R17C37[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1049_s12/I2
16.800	0.686	tINS	FR	1	R17C37[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1049_s12/F
16.800	0.000	tNET	RR	1	R17C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1049_s10/I1
16.932	0.131	tINS	RR	1	R17C37[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1049_s10/O
16.932	0.000	tNET	RR	1	R17C37[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1049_s5/I1
17.063	0.131	tINS	RR	1	R17C37[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1049_s5/O
17.286	0.223	tNET	RR	1	R17C37[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1125_s7/I0
17.998	0.712	tINS	RR	1	R17C37[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1125_s7/F
17.998	0.000	tNET	RR	1	R17C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1125_s4/I1
18.130	0.131	tINS	RR	1	R17C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1125_s4/O
18.139	0.009	tNET	RR	1	R17C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_60
16.667	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
19.289	2.622	tNET	RR	1	R17C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_4_s1/CLK
19.245	-0.044	tSu		1	R17C37[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_4_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 8.960, 57.745%; route: 6.267, 40.386%; tC2Q: 0.290, 1.869%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path24

Path Summary:

Slack	1.133
Data Arrival Time	18.112
Data Required Time	19.245
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_endpt_2_s0
To	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_9_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
2.622	2.622	tNET	RR	1	R16C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_endpt_2_s0/CLK
2.912	0.290	tC2Q	RF	32	R16C15[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/s_endpt_2_s0/Q
5.480	2.568	tNET	FF	1	R23C19[3][A]	usb_rxrdy_s1/I2
6.166	0.686	tINS	FR	28	R23C19[3][A]	usb_rxrdy_s1/F
6.387	0.221	tNET	RR	1	R24C19[3][B]	n394_s0/I1
7.033	0.646	tINS	RF	10	R24C19[3][B]	n394_s0/F
8.866	1.833	tNET	FF	1	R17C14[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s3/I0
9.330	0.464	tINS	FF	2	R17C14[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s3/F
9.948	0.618	tNET	FF	1	R17C18[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s/I1
10.411	0.464	tINS	FF	18	R17C18[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_transact_inst/txpop_o_d_s/F
13.803	3.392	tNET	FF	1	R26C38[0][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n85_s0/I0
14.267	0.464	tINS	FF	5	R26C38[0][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n85_s0/F
14.806	0.539	tNET	FF	1	R27C39[3][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n122_s2/I3
15.270	0.464	tINS	FF	6	R27C39[3][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n122_s2/F
16.013	0.743	tNET	FF	1	R29C38[3][B]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n121_s2/I1
16.476	0.464	tINS	FF	3	R29C38[3][B]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n121_s2/F
16.712	0.236	tNET	FF	1	R29C39[3][B]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n116_s2/I3
17.424	0.712	tINS	FR	1	R29C39[3][B]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n116_s2/F
17.426	0.002	tNET	RR	1	R29C39[1][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n116_s0/I2
18.112	0.686	tINS	RR	1	R29C39[1][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n116_s0/F
18.112	0.000	tNET	RR	1	R29C39[1][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_60
16.667	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
19.289	2.622	tNET	RR	1	R29C39[1][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_9_s1/CLK
19.245	-0.044	tSu		1	R29C39[1][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_9_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 5.050, 32.600%; route: 10.151, 65.528%; tC2Q: 0.290, 1.872%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path25

Path Summary:

Slack	1.142
Data Arrival Time	18.103
Data Required Time	19.245
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_2_s0
To	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_8_s4
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
2.622	2.622	tNET	RR	1	R26C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_2_s0/CLK
2.912	0.290	tC2Q	RF	13	R26C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_desctyp_2_s0/Q
5.686	2.775	tNET	FF	1	R22C20[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_15_s13/I1
6.150	0.464	tINS	FF	20	R22C20[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_15_s13/F
8.929	2.779	tNET	FF	1	R31C18[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_7_s13/I1
9.616	0.686	tINS	FR	1	R31C18[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_7_s13/F
9.831	0.216	tNET	RR	1	R32C18[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_7_s9/I2
10.544	0.712	tINS	RR	1	R32C18[3][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_7_s9/F
10.759	0.216	tNET	RR	1	R32C17[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_7_s8/I0
11.453	0.694	tINS	RF	2	R32C17[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_7_s8/F
12.260	0.807	tNET	FF	2	R30C19[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1416_s0/I1
12.972	0.712	tINS	FR	1	R30C19[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1416_s0/COUT
12.972	0.000	tNET	RR	2	R30C19[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1417_s0/CIN
13.016	0.044	tINS	RF	1	R30C19[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1417_s0/COUT
13.016	0.000	tNET	FF	2	R30C19[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1418_s0/CIN
13.060	0.044	tINS	FF	1	R30C19[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1418_s0/COUT
13.060	0.000	tNET	FF	2	R30C19[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1419_s0/CIN
13.104	0.044	tINS	FF	1	R30C19[2][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1419_s0/COUT
13.104	0.000	tNET	FF	2	R30C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1420_s0/CIN
13.148	0.044	tINS	FF	1	R30C20[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1420_s0/COUT
13.148	0.000	tNET	FF	2	R30C20[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1421_s0/CIN
13.192	0.044	tINS	FF	1	R30C20[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1421_s0/COUT
13.192	0.000	tNET	FF	2	R30C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1422_s0/CIN
13.236	0.044	tINS	FF	1	R30C20[1][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1422_s0/COUT
13.236	0.000	tNET	FF	2	R30C20[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1423_s0/CIN
13.280	0.044	tINS	FF	1	R30C20[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1423_s0/COUT
13.280	0.000	tNET	FF	2	R30C20[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1424_s0/CIN
13.324	0.044	tINS	FF	3	R30C20[2][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1424_s0/COUT
14.974	1.650	tNET	FF	1	R30C12[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1688_s39/I2
15.541	0.566	tINS	FF	3	R30C12[3][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1688_s39/F
16.677	1.136	tNET	FF	1	R31C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1688_s36/I0
17.389	0.712	tINS	FR	1	R31C16[0][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1688_s36/F
17.391	0.002	tNET	RR	1	R31C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1688_s35/I2
18.103	0.712	tINS	RR	1	R31C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1688_s35/F
18.103	0.000	tNET	RR	1	R31C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_8_s4/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_60
16.667	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
19.289	2.622	tNET	RR	1	R31C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_8_s4/CLK
19.245	-0.044	tSu		1	R31C16[0][A]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_8_s4

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	11
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 5.612, 36.249%; route: 9.580, 61.877%; tC2Q: 0.290, 1.873%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.099
Data Arrival Time	2.152
Data Required Time	2.053
From	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_0_s0
To	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R26C44[0][A]	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_0_s0/CLK
1.994	0.252	tC2Q	RR	2	R26C44[0][A]	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_0_s0/Q
2.152	0.158	tNET	RR	1	BSRAM_R28[12]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	BSRAM_R28[12]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/CLKA
2.053	0.311	tHld		1	BSRAM_R28[12]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.158, 38.456%; tC2Q: 0.252, 61.544%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path2

Path Summary:

Slack	0.262
Data Arrival Time	2.151
Data Required Time	1.889
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_4_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.742	1.742	tNET	RR	1	R12C44[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_4_s0/CLK
1.994	0.252	tC2Q	RR	4	R12C44[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_4_s0/Q
2.151	0.157	tNET	RR	1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/ADA[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.742	1.742	tNET	RR	1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/CLKA
1.889	0.148	tHld		1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.157, 38.352%; tC2Q: 0.252, 61.648%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path3

Path Summary:

Slack	0.264
Data Arrival Time	2.153
Data Required Time	1.889
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.742	1.742	tNET	RR	1	R12C45[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_1_s0/CLK
1.994	0.252	tC2Q	RR	6	R12C45[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_1_s0/Q
2.153	0.159	tNET	RR	1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/ADA[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.742	1.742	tNET	RR	1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/CLKA
1.889	0.148	tHld		1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.159, 38.581%; tC2Q: 0.252, 61.419%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path4

Path Summary:

Slack	0.266
Data Arrival Time	2.155
Data Required Time	1.889
From	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/wp_1_s0
To	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R30C42[0][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/wp_1_s0/CLK
1.994	0.252	tC2Q	RR	10	R30C42[0][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/wp_1_s0/Q
2.155	0.161	tNET	RR	1	BSRAM_R28[11]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s/ADA[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	BSRAM_R28[11]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s/CLKA
1.889	0.148	tHld		1	BSRAM_R28[11]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.161, 38.911%; tC2Q: 0.252, 61.089%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path5

Path Summary:

Slack	0.270
Data Arrival Time	2.323
Data Required Time	2.053
From	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_1_s0
To	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R25C44[0][A]	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_1_s0/CLK
1.994	0.252	tC2Q	RR	2	R25C44[0][A]	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_1_s0/Q
2.323	0.329	tNET	RR	1	BSRAM_R28[12]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	BSRAM_R28[12]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/CLKA
2.053	0.311	tHld		1	BSRAM_R28[12]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.329, 56.595%; tC2Q: 0.252, 43.405%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path6

Path Summary:

Slack	0.278
Data Arrival Time	2.167
Data Required Time	1.889
From	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_2_s1
To	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R27C33[0][B]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_2_s1/CLK
1.993	0.251	tC2Q	RF	7	R27C33[0][B]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_2_s1/Q
2.167	0.175	tNET	FF	1	BSRAM_R28[8]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s/ADB[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	BSRAM_R28[8]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s/CLKB
1.889	0.148	tHld		1	BSRAM_R28[8]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.175, 41.002%; tC2Q: 0.251, 58.998%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path7

Path Summary:

Slack	0.284
Data Arrival Time	2.173
Data Required Time	1.889
From	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_4_s1
To	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R27C32[1][B]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_4_s1/CLK
1.993	0.251	tC2Q	RF	8	R27C32[1][B]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_4_s1/Q
2.173	0.180	tNET	FF	1	BSRAM_R28[8]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s/ADB[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	BSRAM_R28[8]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s/CLKB
1.889	0.148	tHld		1	BSRAM_R28[8]	usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/RAM_RAM_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.180, 41.723%; tC2Q: 0.251, 58.277%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path8

Path Summary:

Slack	0.397
Data Arrival Time	2.151
Data Required Time	1.754
From	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/wbin_1_s0
To	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/mem_mem_1_1_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R24C26[1][B]	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/wbin_1_s0/CLK
1.994	0.252	tC2Q	RR	10	R24C26[1][B]	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/wbin_1_s0/Q
2.151	0.157	tNET	RR	1	R24C28	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/mem_mem_1_1_s/WAD[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R24C28	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/mem_mem_1_1_s/CLK
1.754	0.012	tHld		1	R24C28	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/mem_mem_1_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.157, 38.352%; tC2Q: 0.252, 61.648%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path9

Path Summary:

Slack	0.398
Data Arrival Time	2.152
Data Required Time	1.754
From	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/Q_7_s0
To	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/mem_mem_3_1_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R34C30[2][A]	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/Q_7_s0/CLK
1.994	0.252	tC2Q	RR	4	R34C30[2][A]	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/Q_7_s0/Q
2.152	0.158	tNET	RR	1	R32C30	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/mem_mem_3_1_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R32C30	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/mem_mem_3_1_s/CLK
1.754	0.012	tHld		1	R32C30	usb_fifo/usb_tx_buf_ep2/clk_cross_fifo/mem_mem_3_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.158, 38.456%; tC2Q: 0.252, 61.544%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path10

Path Summary:

Slack	0.402
Data Arrival Time	2.156
Data Required Time	1.754
From	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_2_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/mem_mem_3_1_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R33C44[1][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_2_s0/CLK
1.993	0.251	tC2Q	RF	10	R33C44[1][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_2_s0/Q
2.156	0.163	tNET	FF	1	R33C43	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/mem_mem_3_1_s/WAD[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R33C43	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/mem_mem_3_1_s/CLK
1.754	0.012	tHld		1	R33C43	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/mem_mem_3_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.163, 39.420%; tC2Q: 0.251, 60.580%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path11

Path Summary:

Slack	0.402
Data Arrival Time	2.156
Data Required Time	1.754
From	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/wbin_0_s0
To	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/mem_mem_0_0_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R34C25[0][B]	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/wbin_0_s0/CLK
1.993	0.251	tC2Q	RF	13	R34C25[0][B]	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/wbin_0_s0/Q
2.156	0.163	tNET	FF	1	R33C25	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/mem_mem_0_0_s/WAD[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R33C25	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/mem_mem_0_0_s/CLK
1.754	0.012	tHld		1	R33C25	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.163, 39.420%; tC2Q: 0.251, 60.580%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path12

Path Summary:

Slack	0.404
Data Arrival Time	2.457
Data Required Time	2.053
From	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_7_s0
To	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R25C45[0][A]	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_7_s0/CLK
1.994	0.252	tC2Q	RR	2	R25C45[0][A]	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_7_s0/Q
2.457	0.463	tNET	RR	1	BSRAM_R28[13]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	BSRAM_R28[13]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKA
2.053	0.311	tHld		1	BSRAM_R28[13]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.463, 64.699%; tC2Q: 0.252, 35.301%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path13

Path Summary:

Slack	0.404
Data Arrival Time	2.457
Data Required Time	2.053
From	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_4_s0
To	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R25C45[1][A]	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_4_s0/CLK
1.994	0.252	tC2Q	RR	2	R25C45[1][A]	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_4_s0/Q
2.457	0.463	tNET	RR	1	BSRAM_R28[13]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	BSRAM_R28[13]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKA
2.053	0.311	tHld		1	BSRAM_R28[13]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.463, 64.699%; tC2Q: 0.252, 35.301%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path14

Path Summary:

Slack	0.406
Data Arrival Time	2.160
Data Required Time	1.754
From	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_1_s0
To	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/mem_mem_3_1_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R33C44[0][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_1_s0/CLK
1.993	0.251	tC2Q	RF	11	R33C44[0][B]	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/wbin_1_s0/Q
2.160	0.168	tNET	FF	1	R33C43	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/mem_mem_3_1_s/WAD[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R33C43	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/mem_mem_3_1_s/CLK
1.754	0.012	tHld		1	R33C43	usb_fifo/usb_rx_buf_ep3/clk_cross_fifo/mem_mem_3_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.168, 40.013%; tC2Q: 0.251, 59.987%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path15

Path Summary:

Slack	0.407
Data Arrival Time	2.460
Data Required Time	2.053
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_3_s1
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.742	1.742	tNET	RR	1	R12C42[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_3_s1/CLK
1.994	0.252	tC2Q	RR	2	R12C42[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_3_s1/Q
2.460	0.466	tNET	RR	1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.742	1.742	tNET	RR	1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/CLKA
2.053	0.311	tHld		1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.466, 64.834%; tC2Q: 0.252, 35.166%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path16

Path Summary:

Slack	0.409
Data Arrival Time	2.163
Data Required Time	1.754
From	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/wbin_1_s0
To	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/mem_mem_0_1_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R34C26[1][A]	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/wbin_1_s0/CLK
1.993	0.251	tC2Q	RF	11	R34C26[1][A]	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/wbin_1_s0/Q
2.163	0.171	tNET	FF	1	R33C26	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/mem_mem_0_1_s/WAD[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R33C26	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/mem_mem_0_1_s/CLK
1.754	0.012	tHld		1	R33C26	usb_fifo/usb_rx_buf_ep2/clk_cross_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.171, 40.429%; tC2Q: 0.251, 59.571%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path17

Path Summary:

Slack	0.416
Data Arrival Time	2.305
Data Required Time	1.889
From	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_8_s1
To	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R29C39[1][B]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_8_s1/CLK
1.994	0.252	tC2Q	RR	7	R29C39[1][B]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_8_s1/Q
2.305	0.311	tNET	RR	1	BSRAM_R28[11]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s/ADB[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	BSRAM_R28[11]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s/CLKB
1.889	0.148	tHld		1	BSRAM_R28[11]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.311, 55.200%; tC2Q: 0.252, 44.800%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path18

Path Summary:

Slack	0.418
Data Arrival Time	2.307
Data Required Time	1.889
From	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/wp_5_s0
To	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R30C42[2][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/wp_5_s0/CLK
1.994	0.252	tC2Q	RR	10	R30C42[2][A]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/wp_5_s0/Q
2.307	0.313	tNET	RR	1	BSRAM_R28[12]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/ADA[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	BSRAM_R28[12]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/CLKA
1.889	0.148	tHld		1	BSRAM_R28[12]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.313, 55.321%; tC2Q: 0.252, 44.679%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path19

Path Summary:

Slack	0.419
Data Arrival Time	2.472
Data Required Time	2.053
From	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_6_s0
To	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R25C46[2][A]	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_6_s0/CLK
1.994	0.252	tC2Q	RR	2	R25C46[2][A]	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_6_s0/Q
2.472	0.478	tNET	RR	1	BSRAM_R28[13]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	BSRAM_R28[13]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKA
2.053	0.311	tHld		1	BSRAM_R28[13]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.478, 65.434%; tC2Q: 0.252, 34.566%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path20

Path Summary:

Slack	0.420
Data Arrival Time	2.309
Data Required Time	1.889
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_2_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.742	1.742	tNET	RR	1	R12C45[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_2_s0/CLK
1.994	0.252	tC2Q	RR	7	R12C45[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_2_s0/Q
2.309	0.315	tNET	RR	1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/ADA[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.742	1.742	tNET	RR	1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/CLKA
1.889	0.148	tHld		1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.315, 55.471%; tC2Q: 0.252, 44.529%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path21

Path Summary:

Slack	0.421
Data Arrival Time	2.474
Data Required Time	2.053
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_4_s1
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.742	1.742	tNET	RR	1	R12C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_4_s1/CLK
1.994	0.252	tC2Q	RR	2	R12C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_4_s1/Q
2.474	0.479	tNET	RR	1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.742	1.742	tNET	RR	1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/CLKA
2.053	0.311	tHld		1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.479, 65.503%; tC2Q: 0.252, 34.497%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path22

Path Summary:

Slack	0.421
Data Arrival Time	2.474
Data Required Time	2.053
From	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_5_s0
To	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R25C45[2][A]	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_5_s0/CLK
1.994	0.252	tC2Q	RR	2	R25C45[2][A]	usb_fifo/usb_tx_buf_ep3/clk_cross_fifo/Q_5_s0/Q
2.474	0.479	tNET	RR	1	BSRAM_R28[13]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	BSRAM_R28[13]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0/CLKA
2.053	0.311	tHld		1	BSRAM_R28[13]	usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.479, 65.503%; tC2Q: 0.252, 34.497%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path23

Path Summary:

Slack	0.421
Data Arrival Time	2.474
Data Required Time	2.053
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_0_s1
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.742	1.742	tNET	RR	1	R11C40[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_0_s1/CLK
1.994	0.252	tC2Q	RR	2	R11C40[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_0_s1/Q
2.474	0.480	tNET	RR	1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/DI[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.742	1.742	tNET	RR	1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/CLKA
2.053	0.311	tHld		1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.480, 65.506%; tC2Q: 0.252, 34.494%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path24

Path Summary:

Slack	0.421
Data Arrival Time	2.474
Data Required Time	2.053
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_1_s1
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.742	1.742	tNET	RR	1	R11C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_1_s1/CLK
1.994	0.252	tC2Q	RR	2	R11C41[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_1_s1/Q
2.474	0.480	tNET	RR	1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/DI[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.742	1.742	tNET	RR	1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/CLKA
2.053	0.311	tHld		1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.480, 65.506%; tC2Q: 0.252, 34.494%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path25

Path Summary:

Slack	0.421
Data Arrival Time	2.474
Data Required Time	2.053
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_2_s1
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s
Launch Clk	clk_120:[R]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.742	1.742	tNET	RR	1	R11C41[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_2_s1/CLK
1.994	0.252	tC2Q	RR	2	R11C41[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_wr_data_2_s1/Q
2.474	0.480	tNET	RR	1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/DI[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_120
0.000	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
1.742	1.742	tNET	RR	1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s/CLKA
2.053	0.311	tHld		1	BSRAM_R10[13]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.mem_Equal.mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.480, 65.506%; tC2Q: 0.252, 34.494%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.635
Data Arrival Time	9.773
Data Required Time	10.407
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	1	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
7.082	0.290	tC2Q	FF	46	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
9.773	2.690	tNET	FF	8	BSRAM_R10[8]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/RESETB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	BSRAM_R10[8]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/CLKB
10.407	-0.548	tSu		1	BSRAM_R10[8]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.690, 90.269%; tC2Q: 0.290, 9.731%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path2

Path Summary:

Slack	0.747
Data Arrival Time	10.168
Data Required Time	10.916
From	reset_cnt_0_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_r_1_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
2.622	2.622	tNET	RR	1	R22C29[0][A]	reset_cnt_0_s0/CLK
2.912	0.290	tC2Q	RF	3	R22C29[0][A]	reset_cnt_0_s0/Q
3.746	0.834	tNET	FF	1	R23C26[3][B]	n116_s106/I3
4.323	0.577	tINS	FR	1	R23C26[3][B]	n116_s106/F
4.325	0.002	tNET	RR	1	R23C26[3][A]	n116_s105/I1
5.011	0.686	tINS	RR	1	R23C26[3][A]	n116_s105/F
5.227	0.216	tNET	RR	1	R23C27[3][A]	n116_s100/I2
5.939	0.712	tINS	RR	1	R23C27[3][A]	n116_s100/F
5.941	0.002	tNET	RR	1	R23C27[3][B]	n116_s97/I0
6.518	0.577	tINS	RR	1	R23C27[3][B]	n116_s97/F
6.734	0.216	tNET	RR	1	R23C28[3][A]	n116_s96/I1
7.300	0.566	tINS	RF	33	R23C28[3][A]	n116_s96/F
7.861	0.561	tNET	FF	1	R23C31[1][A]	RESET_s0/I0
8.508	0.646	tINS	FF	472	R23C31[1][A]	RESET_s0/F
10.168	1.661	tNET	FF	1	R12C44[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_r_1_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.334	8.334					active clock edge time
8.334	0.000					clk_60
8.334	0.000	tCL	FF	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
10.959	2.625	tNET	FF	1	R12C44[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_r_1_s0/CLK
10.916	-0.044	tSu		1	R12C44[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_r_1_s0

Path Statistics:

Clock Skew	0.004
Setup Relationship	8.334
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 3.766, 49.905%; route: 3.491, 46.252%; tC2Q: 0.290, 3.843%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%

Path3

Path Summary:

Slack	0.747
Data Arrival Time	10.168
Data Required Time	10.916
From	reset_cnt_0_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_r_0_s0
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
2.622	2.622	tNET	RR	1	R22C29[0][A]	reset_cnt_0_s0/CLK
2.912	0.290	tC2Q	RF	3	R22C29[0][A]	reset_cnt_0_s0/Q
3.746	0.834	tNET	FF	1	R23C26[3][B]	n116_s106/I3
4.323	0.577	tINS	FR	1	R23C26[3][B]	n116_s106/F
4.325	0.002	tNET	RR	1	R23C26[3][A]	n116_s105/I1
5.011	0.686	tINS	RR	1	R23C26[3][A]	n116_s105/F
5.227	0.216	tNET	RR	1	R23C27[3][A]	n116_s100/I2
5.939	0.712	tINS	RR	1	R23C27[3][A]	n116_s100/F
5.941	0.002	tNET	RR	1	R23C27[3][B]	n116_s97/I0
6.518	0.577	tINS	RR	1	R23C27[3][B]	n116_s97/F
6.734	0.216	tNET	RR	1	R23C28[3][A]	n116_s96/I1
7.300	0.566	tINS	RF	33	R23C28[3][A]	n116_s96/F
7.861	0.561	tNET	FF	1	R23C31[1][A]	RESET_s0/I0
8.508	0.646	tINS	FF	472	R23C31[1][A]	RESET_s0/F
10.168	1.661	tNET	FF	1	R12C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_r_0_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.334	8.334					active clock edge time
8.334	0.000					clk_60
8.334	0.000	tCL	FF	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
10.959	2.625	tNET	FF	1	R12C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_r_0_s0/CLK
10.916	-0.044	tSu		1	R12C44[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_r_0_s0

Path Statistics:

Clock Skew	0.004
Setup Relationship	8.334
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%
Arrival Data Path Delay	cell: 3.766, 49.905%; route: 3.491, 46.252%; tC2Q: 0.290, 3.843%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%

Path4

Path Summary:

Slack	1.119
Data Arrival Time	9.792
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_1_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	1	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
7.082	0.290	tC2Q	FF	46	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
9.792	2.710	tNET	FF	1	R11C29[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R11C29[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_1_s0/CLK
10.911	-0.044	tSu		1	R11C29[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_1_s0

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.710, 90.332%; tC2Q: 0.290, 9.668%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path5

Path Summary:

Slack	1.119
Data Arrival Time	9.792
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_2_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	1	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
7.082	0.290	tC2Q	FF	46	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
9.792	2.710	tNET	FF	1	R11C29[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R11C29[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_2_s0/CLK
10.911	-0.044	tSu		1	R11C29[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_2_s0

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.710, 90.332%; tC2Q: 0.290, 9.668%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path6

Path Summary:

Slack	1.119
Data Arrival Time	9.792
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_4_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	1	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
7.082	0.290	tC2Q	FF	46	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
9.792	2.710	tNET	FF	1	R11C29[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R11C29[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_4_s0/CLK
10.911	-0.044	tSu		1	R11C29[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_4_s0

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.710, 90.332%; tC2Q: 0.290, 9.668%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path7

Path Summary:

Slack	1.119
Data Arrival Time	9.792
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Full_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	1	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
7.082	0.290	tC2Q	FF	46	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
9.792	2.710	tNET	FF	1	R14C43[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Full_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R14C43[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Full_s0/CLK
10.911	-0.044	tSu		1	R14C43[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Full_s0

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.710, 90.332%; tC2Q: 0.290, 9.668%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path8

Path Summary:

Slack	1.119
Data Arrival Time	9.792
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_4_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	1	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
7.082	0.290	tC2Q	FF	46	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
9.792	2.710	tNET	FF	1	R14C43[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R14C43[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_4_s0/CLK
10.911	-0.044	tSu		1	R14C43[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_4_s0

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.710, 90.332%; tC2Q: 0.290, 9.668%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path9

Path Summary:

Slack	1.119
Data Arrival Time	9.792
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_5_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	1	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
7.082	0.290	tC2Q	FF	46	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
9.792	2.710	tNET	FF	1	R14C43[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R14C43[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_5_s0/CLK
10.911	-0.044	tSu		1	R14C43[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_5_s0

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.710, 90.332%; tC2Q: 0.290, 9.668%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path10

Path Summary:

Slack	1.119
Data Arrival Time	9.792
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_0_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	1	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
7.082	0.290	tC2Q	FF	46	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
9.792	2.710	tNET	FF	1	R14C43[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R14C43[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_0_s0/CLK
10.911	-0.044	tSu		1	R14C43[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_0_s0

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.710, 90.332%; tC2Q: 0.290, 9.668%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path11

Path Summary:

Slack	1.129
Data Arrival Time	9.782
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_2_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	1	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
7.082	0.290	tC2Q	FF	46	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
9.782	2.700	tNET	FF	1	R12C32[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R12C32[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_2_s0/CLK
10.911	-0.044	tSu		1	R12C32[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_2_s0

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.700, 90.301%; tC2Q: 0.290, 9.699%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path12

Path Summary:

Slack	1.129
Data Arrival Time	9.782
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_0_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	1	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
7.082	0.290	tC2Q	FF	46	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
9.782	2.700	tNET	FF	1	R12C29[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R12C29[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_0_s0/CLK
10.911	-0.044	tSu		1	R12C29[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_0_s0

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.700, 90.301%; tC2Q: 0.290, 9.699%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path13

Path Summary:

Slack	1.129
Data Arrival Time	9.782
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_3_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	1	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
7.082	0.290	tC2Q	FF	46	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
9.782	2.700	tNET	FF	1	R12C29[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R12C29[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_3_s0/CLK
10.911	-0.044	tSu		1	R12C29[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_3_s0

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.700, 90.301%; tC2Q: 0.290, 9.699%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path14

Path Summary:

Slack	1.129
Data Arrival Time	9.782
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_0_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	1	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
7.082	0.290	tC2Q	FF	46	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
9.782	2.700	tNET	FF	1	R11C28[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R11C28[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_0_s0/CLK
10.911	-0.044	tSu		1	R11C28[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_0_s0

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.700, 90.301%; tC2Q: 0.290, 9.699%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path15

Path Summary:

Slack	1.129
Data Arrival Time	9.782
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_3_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	1	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
7.082	0.290	tC2Q	FF	46	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
9.782	2.700	tNET	FF	1	R11C28[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R11C28[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_3_s0/CLK
10.911	-0.044	tSu		1	R11C28[1][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_3_s0

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.700, 90.301%; tC2Q: 0.290, 9.699%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path16

Path Summary:

Slack	1.129
Data Arrival Time	9.782
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_4_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	1	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
7.082	0.290	tC2Q	FF	46	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
9.782	2.700	tNET	FF	1	R11C28[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R11C28[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_4_s0/CLK
10.911	-0.044	tSu		1	R11C28[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_4_s0

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.700, 90.301%; tC2Q: 0.290, 9.699%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path17

Path Summary:

Slack	1.129
Data Arrival Time	9.782
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_1_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	1	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
7.082	0.290	tC2Q	FF	46	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
9.782	2.700	tNET	FF	1	R12C32[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R12C32[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_1_s0/CLK
10.911	-0.044	tSu		1	R12C32[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_1_s0

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.700, 90.301%; tC2Q: 0.290, 9.699%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path18

Path Summary:

Slack	1.129
Data Arrival Time	9.782
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_2_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	1	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
7.082	0.290	tC2Q	FF	46	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
9.782	2.700	tNET	FF	1	R13C31[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R13C31[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_2_s0/CLK
10.911	-0.044	tSu		1	R13C31[1][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_2_s0

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.700, 90.301%; tC2Q: 0.290, 9.699%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path19

Path Summary:

Slack	1.129
Data Arrival Time	9.782
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_4_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	1	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
7.082	0.290	tC2Q	FF	46	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
9.782	2.700	tNET	FF	1	R13C31[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R13C31[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_4_s0/CLK
10.911	-0.044	tSu		1	R13C31[0][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_4_s0

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.700, 90.301%; tC2Q: 0.290, 9.699%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path20

Path Summary:

Slack	1.129
Data Arrival Time	9.782
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_5_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	1	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
7.082	0.290	tC2Q	FF	46	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
9.782	2.700	tNET	FF	1	R13C31[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R13C31[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_5_s0/CLK
10.911	-0.044	tSu		1	R13C31[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_5_s0

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.700, 90.301%; tC2Q: 0.290, 9.699%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path21

Path Summary:

Slack	1.129
Data Arrival Time	9.782
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_0_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	1	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
7.082	0.290	tC2Q	FF	46	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
9.782	2.700	tNET	FF	1	R14C44[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R14C44[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_0_s0/CLK
10.911	-0.044	tSu		1	R14C44[2][B]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_0_s0

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.700, 90.301%; tC2Q: 0.290, 9.699%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path22

Path Summary:

Slack	1.129
Data Arrival Time	9.782
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_1_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	1	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
7.082	0.290	tC2Q	FF	46	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
9.782	2.700	tNET	FF	1	R12C45[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R12C45[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_1_s0/CLK
10.911	-0.044	tSu		1	R12C45[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_1_s0

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.700, 90.301%; tC2Q: 0.290, 9.699%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path23

Path Summary:

Slack	1.129
Data Arrival Time	9.782
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_2_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	1	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
7.082	0.290	tC2Q	FF	46	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
9.782	2.700	tNET	FF	1	R12C45[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R12C45[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_2_s0/CLK
10.911	-0.044	tSu		1	R12C45[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_2_s0

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.700, 90.301%; tC2Q: 0.290, 9.699%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path24

Path Summary:

Slack	1.129
Data Arrival Time	9.782
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_0_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	1	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
7.082	0.290	tC2Q	FF	46	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
9.782	2.700	tNET	FF	1	R15C43[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R15C43[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_0_s0/CLK
10.911	-0.044	tSu		1	R15C43[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_0_s0

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.700, 90.301%; tC2Q: 0.290, 9.699%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Path25

Path Summary:

Slack	1.129
Data Arrival Time	9.782
Data Required Time	10.911
From	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0
To	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_1_s0
Launch Clk	clk_120:[F]
Latch Clk	clk_120:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.167	4.167					active clock edge time
4.167	0.000					clk_120
4.167	0.000	tCL	FF	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	1	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK
7.082	0.290	tC2Q	FF	46	R12C43[2][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/Q
9.782	2.700	tNET	FF	1	R13C43[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_120
8.333	0.000	tCL	RR	159	TOPSIDE[0]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.955	2.622	tNET	RR	1	R13C43[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_1_s0/CLK
10.911	-0.044	tSu		1	R13C43[0][A]	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_1_s0

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.166
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.625, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.700, 90.301%; tC2Q: 0.290, 9.699%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.622, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/stage_0_s3
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R34C21[0][B]	u_usb_uart_config/stage_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R34C21[0][B]	u_usb_uart_config/stage_0_s3/CLK
1.755	0.014	tHld		1	R34C21[0][B]	u_usb_uart_config/stage_0_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path2

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/stage_3_s4
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R34C24[2][A]	u_usb_uart_config/stage_3_s4/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R34C24[2][A]	u_usb_uart_config/stage_3_s4/CLK
1.755	0.014	tHld		1	R34C24[2][A]	u_usb_uart_config/stage_3_s4

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path3

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/endpt0_txcork_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R36C17[0][A]	u_usb_uart_config/endpt0_txcork_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R36C17[0][A]	u_usb_uart_config/endpt0_txcork_s1/CLK
1.755	0.014	tHld		1	R36C17[0][A]	u_usb_uart_config/endpt0_txcork_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path4

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/endpt0_rxrdy_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R36C18[0][A]	u_usb_uart_config/endpt0_rxrdy_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R36C18[0][A]	u_usb_uart_config/endpt0_rxrdy_s1/CLK
1.755	0.014	tHld		1	R36C18[0][A]	u_usb_uart_config/endpt0_rxrdy_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path5

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/endpt0_dat_0_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R33C14[0][A]	u_usb_uart_config/endpt0_dat_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R33C14[0][A]	u_usb_uart_config/endpt0_dat_0_s1/CLK
1.755	0.014	tHld		1	R33C14[0][A]	u_usb_uart_config/endpt0_dat_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path6

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/endpt0_dat_1_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R33C14[0][B]	u_usb_uart_config/endpt0_dat_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R33C14[0][B]	u_usb_uart_config/endpt0_dat_1_s1/CLK
1.755	0.014	tHld		1	R33C14[0][B]	u_usb_uart_config/endpt0_dat_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path7

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/endpt0_dat_2_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R33C14[1][A]	u_usb_uart_config/endpt0_dat_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R33C14[1][A]	u_usb_uart_config/endpt0_dat_2_s1/CLK
1.755	0.014	tHld		1	R33C14[1][A]	u_usb_uart_config/endpt0_dat_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path8

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/endpt0_dat_3_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R33C14[1][B]	u_usb_uart_config/endpt0_dat_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R33C14[1][B]	u_usb_uart_config/endpt0_dat_3_s1/CLK
1.755	0.014	tHld		1	R33C14[1][B]	u_usb_uart_config/endpt0_dat_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path9

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/endpt0_dat_4_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R33C14[2][A]	u_usb_uart_config/endpt0_dat_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R33C14[2][A]	u_usb_uart_config/endpt0_dat_4_s1/CLK
1.755	0.014	tHld		1	R33C14[2][A]	u_usb_uart_config/endpt0_dat_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path10

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/endpt0_dat_5_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R33C16[2][A]	u_usb_uart_config/endpt0_dat_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R33C16[2][A]	u_usb_uart_config/endpt0_dat_5_s1/CLK
1.755	0.014	tHld		1	R33C16[2][A]	u_usb_uart_config/endpt0_dat_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path11

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/endpt0_dat_6_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R33C16[1][A]	u_usb_uart_config/endpt0_dat_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R33C16[1][A]	u_usb_uart_config/endpt0_dat_6_s1/CLK
1.755	0.014	tHld		1	R33C16[1][A]	u_usb_uart_config/endpt0_dat_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path12

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/endpt0_dat_7_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R33C16[1][B]	u_usb_uart_config/endpt0_dat_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R33C16[1][B]	u_usb_uart_config/endpt0_dat_7_s1/CLK
1.755	0.014	tHld		1	R33C16[1][B]	u_usb_uart_config/endpt0_dat_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path13

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/endpt0_send_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R33C21[0][A]	u_usb_uart_config/endpt0_send_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R33C21[0][A]	u_usb_uart_config/endpt0_send_s1/CLK
1.755	0.014	tHld		1	R33C21[0][A]	u_usb_uart_config/endpt0_send_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path14

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/sub_stage_0_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R34C16[1][B]	u_usb_uart_config/sub_stage_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R34C16[1][B]	u_usb_uart_config/sub_stage_0_s1/CLK
1.755	0.014	tHld		1	R34C16[1][B]	u_usb_uart_config/sub_stage_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path15

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/sub_stage_1_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R33C16[0][A]	u_usb_uart_config/sub_stage_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R33C16[0][A]	u_usb_uart_config/sub_stage_1_s1/CLK
1.755	0.014	tHld		1	R33C16[0][A]	u_usb_uart_config/sub_stage_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path16

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/sub_stage_2_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R33C16[0][B]	u_usb_uart_config/sub_stage_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R33C16[0][B]	u_usb_uart_config/sub_stage_2_s1/CLK
1.755	0.014	tHld		1	R33C16[0][B]	u_usb_uart_config/sub_stage_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path17

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/sub_stage_3_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R34C16[0][B]	u_usb_uart_config/sub_stage_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R34C16[0][B]	u_usb_uart_config/sub_stage_3_s1/CLK
1.755	0.014	tHld		1	R34C16[0][B]	u_usb_uart_config/sub_stage_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path18

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/sub_stage_4_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R34C16[1][A]	u_usb_uart_config/sub_stage_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R34C16[1][A]	u_usb_uart_config/sub_stage_4_s1/CLK
1.755	0.014	tHld		1	R34C16[1][A]	u_usb_uart_config/sub_stage_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path19

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/sub_stage_5_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R33C17[0][A]	u_usb_uart_config/sub_stage_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R33C17[0][A]	u_usb_uart_config/sub_stage_5_s1/CLK
1.755	0.014	tHld		1	R33C17[0][A]	u_usb_uart_config/sub_stage_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path20

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/sub_stage_6_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R33C17[0][B]	u_usb_uart_config/sub_stage_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R33C17[0][B]	u_usb_uart_config/sub_stage_6_s1/CLK
1.755	0.014	tHld		1	R33C17[0][B]	u_usb_uart_config/sub_stage_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path21

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/sub_stage_7_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R35C17[0][A]	u_usb_uart_config/sub_stage_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R35C17[0][A]	u_usb_uart_config/sub_stage_7_s1/CLK
1.755	0.014	tHld		1	R35C17[0][A]	u_usb_uart_config/sub_stage_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path22

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/test_tx_count_0_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R36C25[1][B]	u_usb_uart_config/test_tx_count_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R36C25[1][B]	u_usb_uart_config/test_tx_count_0_s1/CLK
1.755	0.014	tHld		1	R36C25[1][B]	u_usb_uart_config/test_tx_count_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path23

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/test_tx_count_1_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R36C25[1][A]	u_usb_uart_config/test_tx_count_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R36C25[1][A]	u_usb_uart_config/test_tx_count_1_s1/CLK
1.755	0.014	tHld		1	R36C25[1][A]	u_usb_uart_config/test_tx_count_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path24

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/test_tx_count_2_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R36C25[0][A]	u_usb_uart_config/test_tx_count_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R36C25[0][A]	u_usb_uart_config/test_tx_count_2_s1/CLK
1.755	0.014	tHld		1	R36C25[0][A]	u_usb_uart_config/test_tx_count_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Path25

Path Summary:

Slack	1.716
Data Arrival Time	3.471
Data Required Time	1.755
From	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0
To	u_usb_uart_config/test_tx_count_3_s1
Launch Clk	clk_60:[R]
Latch Clk	clk_60:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/CLK
1.994	0.252	tC2Q	RR	894	R11C11[1][B]	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/u_usb_init/s_reset_s0/Q
3.471	1.477	tNET	RR	1	R36C23[2][B]	u_usb_uart_config/test_tx_count_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_60
0.000	0.000	tCL	RR	1583	PLL_L[1]	u_pll/rpll_inst/CLKOUTD
1.742	1.742	tNET	RR	1	R36C23[2][B]	u_usb_uart_config/test_tx_count_3_s1/CLK
1.755	0.014	tHld		1	R36C23[2][B]	u_usb_uart_config/test_tx_count_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.477, 85.399%; tC2Q: 0.252, 14.601%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.742, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	2.032
Actual Width:	3.282
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk_120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk_120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.075	1.742	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_2_s0/CLK

MPW2

MPW Summary:

Slack:	2.032
Actual Width:	3.282
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk_120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk_120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.075	1.742	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_1_s0/CLK

MPW3

MPW Summary:

Slack:	2.032
Actual Width:	3.282
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk_120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk_120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.075	1.742	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_0_s0/CLK

MPW4

MPW Summary:

Slack:	2.032
Actual Width:	3.282
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk_120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk_120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.075	1.742	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_2_s0/CLK

MPW5

MPW Summary:

Slack:	2.032
Actual Width:	3.282
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk_120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk_120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.075	1.742	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_1_s0/CLK

MPW6

MPW Summary:

Slack:	2.032
Actual Width:	3.282
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk_120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk_120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.075	1.742	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_1_s0/CLK

MPW7

MPW Summary:

Slack:	2.032
Actual Width:	3.282
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk_120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk_120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.075	1.742	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_0_s0/CLK

MPW8

MPW Summary:

Slack:	2.032
Actual Width:	3.282
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk_120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk_120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.075	1.742	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_1_s0/CLK

MPW9

MPW Summary:

Slack:	2.032
Actual Width:	3.282
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk_120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk_120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.075	1.742	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_0_s0/CLK

MPW10

MPW Summary:

Slack:	2.032
Actual Width:	3.282
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_120
Objects:	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.167	0.000			active clock edge time
4.167	0.000			clk_120
4.167	0.000	tCL	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
6.792	2.625	tNET	FF	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.333	0.000			active clock edge time
8.333	0.000			clk_120
8.333	0.000	tCL	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT
10.075	1.742	tNET	RR	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_3_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
1583	PHY_CLKOUT	0.219	2.625
894	usb_busreset	9.093	2.884
472	RESET	0.747	2.151
159	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/sclk	0.154	2.625
77	u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/state_0[2]	0.233	1.772
65	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1619_4	7.103	2.682
64	endpt_sel[0]	2.504	2.320
64	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1619_11	7.103	1.998
58	setup_active	6.916	2.952
48	u_usb_device_controller_top/u_usb_device_controller/u_usb_device_controller_utmi/DESC_INDEX[0]	2.381	2.570

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C2	100.00%
R2C8	100.00%
R2C12	100.00%
R2C14	100.00%
R2C15	100.00%
R2C47	100.00%
R4C3	100.00%
R6C23	100.00%
R21C25	100.00%
R41C4	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk_50 -period 20 -waveform {0 10} [get_ports {CLK_IN}]
TC_CLOCK	Actived	create_clock -name clk_120 -period 8.333 -waveform {0 4.167} [get_nets {u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/sclk}]
TC_CLOCK	Actived	create_clock -name clk_60 -period 16.667 -waveform {0 8.334} [get_nets {PHY_CLKOUT}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk_120}] -to [get_clocks {clk_60}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk_60}] -to [get_clocks {clk_120}]