Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\PWM\data\pwm_wrapper.v C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\PWM\data\pwm.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.02 (64-bit) |
| Part Number | GW1N-LV9QN88C6/I5 |
| Device | GW1N-9 |
| Device Version | C |
| Created Time | Tue Apr 15 15:15:46 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | PWM_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.073s, Peak memory usage = 56.281MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0s, Peak memory usage = 56.281MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 56.281MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 56.281MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 56.281MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 56.281MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 56.281MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0s, Peak memory usage = 56.281MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 56.281MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 56.281MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 56.281MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 56.281MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.574s, Peak memory usage = 84.934MB Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 84.934MB Generate output files: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 84.934MB |
| Total Time and Memory Usage | CPU time = 0h 0m 0.638s, Elapsed time = 0h 0m 0.682s, Peak memory usage = 84.934MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 38 |
| I/O Buf | 35 |
| IBUF | 34 |
| OBUF | 1 |
| Register | 59 |
| DFF | 9 |
| DFFE | 34 |
| DFFR | 16 |
| LUT | 85 |
| LUT2 | 9 |
| LUT3 | 17 |
| LUT4 | 59 |
| ALU | 19 |
| ALU | 19 |
| INV | 4 |
| INV | 4 |
| IOLOGIC | 1 |
| OSER8 | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 108(89 LUT, 19 ALU) / 8640 | 2% |
| Register | 59 / 6693 | <1% |
| --Register as Latch | 0 / 6693 | 0% |
| --Register as FF | 59 / 6693 | <1% |
| BSRAM | 0 / 26 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | pclk | Base | 20.000 | 50.000 | 0.000 | 10.000 | pclk_ibuf/I | ||
| 2 | fclk | Base | 20.000 | 50.000 | 0.000 | 10.000 | fclk_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | pclk | 50.000(MHz) | 88.997(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 8.764 |
| Data Arrival Time | 11.562 |
| Data Required Time | 20.326 |
| From | u_pwm/cnt_0_s0 |
| To | u_pwm/d_0_s0 |
| Launch Clk | pclk[R] |
| Latch Clk | pclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | pclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | pclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 60 | pclk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | u_pwm/cnt_0_s0/CLK |
| 1.184 | 0.458 | tC2Q | RF | 6 | u_pwm/cnt_0_s0/Q |
| 2.144 | 0.960 | tNET | FF | 2 | u_pwm/n278_s14/I1 |
| 3.189 | 1.045 | tINS | FF | 1 | u_pwm/n278_s14/COUT |
| 3.189 | 0.000 | tNET | FF | 2 | u_pwm/n278_s15/CIN |
| 3.246 | 0.057 | tINS | FF | 1 | u_pwm/n278_s15/COUT |
| 3.246 | 0.000 | tNET | FF | 2 | u_pwm/n278_s16/CIN |
| 3.303 | 0.057 | tINS | FF | 1 | u_pwm/n278_s16/COUT |
| 3.303 | 0.000 | tNET | FF | 2 | u_pwm/n278_s17/CIN |
| 3.360 | 0.057 | tINS | FF | 1 | u_pwm/n278_s17/COUT |
| 3.360 | 0.000 | tNET | FF | 2 | u_pwm/n278_s18/CIN |
| 3.417 | 0.057 | tINS | FF | 1 | u_pwm/n278_s18/COUT |
| 3.417 | 0.000 | tNET | FF | 2 | u_pwm/n278_s19/CIN |
| 3.474 | 0.057 | tINS | FF | 1 | u_pwm/n278_s19/COUT |
| 4.434 | 0.960 | tNET | FF | 1 | u_pwm/n278_s20/I2 |
| 5.256 | 0.822 | tINS | FF | 4 | u_pwm/n278_s20/F |
| 6.216 | 0.960 | tNET | FF | 1 | u_pwm/n335_s1/I2 |
| 7.038 | 0.822 | tINS | FF | 3 | u_pwm/n335_s1/F |
| 7.998 | 0.960 | tNET | FF | 1 | u_pwm/n337_s1/I2 |
| 8.820 | 0.822 | tINS | FF | 2 | u_pwm/n337_s1/F |
| 9.780 | 0.960 | tNET | FF | 1 | u_pwm/n338_s1/I2 |
| 10.602 | 0.822 | tINS | FF | 1 | u_pwm/n338_s1/F |
| 11.562 | 0.960 | tNET | FF | 1 | u_pwm/d_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | pclk | |||
| 20.000 | 0.000 | tCL | RR | 1 | pclk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 60 | pclk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | u_pwm/d_0_s0/CLK |
| 20.326 | -0.400 | tSu | 1 | u_pwm/d_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 4.618, 42.616%; route: 5.760, 53.154%; tC2Q: 0.458, 4.230% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 2
Path Summary:| Slack | 9.946 |
| Data Arrival Time | 10.380 |
| Data Required Time | 20.326 |
| From | u_pwm/duty_cycle_int_1_s1 |
| To | u_pwm/duty_cycle_int_5_s1 |
| Launch Clk | pclk[R] |
| Latch Clk | pclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | pclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | pclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 60 | pclk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | u_pwm/duty_cycle_int_1_s1/CLK |
| 1.184 | 0.458 | tC2Q | RF | 7 | u_pwm/duty_cycle_int_1_s1/Q |
| 2.144 | 0.960 | tNET | FF | 1 | u_pwm/n65_s8/I1 |
| 3.243 | 1.099 | tINS | FF | 7 | u_pwm/n65_s8/F |
| 4.203 | 0.960 | tNET | FF | 1 | u_pwm/n69_s4/I1 |
| 5.302 | 1.099 | tINS | FF | 1 | u_pwm/n69_s4/F |
| 6.262 | 0.960 | tNET | FF | 1 | u_pwm/n69_s2/I1 |
| 7.361 | 1.099 | tINS | FF | 1 | u_pwm/n69_s2/F |
| 8.321 | 0.960 | tNET | FF | 1 | u_pwm/n69_s0/I1 |
| 9.420 | 1.099 | tINS | FF | 1 | u_pwm/n69_s0/F |
| 10.380 | 0.960 | tNET | FF | 1 | u_pwm/duty_cycle_int_5_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | pclk | |||
| 20.000 | 0.000 | tCL | RR | 1 | pclk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 60 | pclk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | u_pwm/duty_cycle_int_5_s1/CLK |
| 20.326 | -0.400 | tSu | 1 | u_pwm/duty_cycle_int_5_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 4.396, 45.534%; route: 4.800, 49.719%; tC2Q: 0.458, 4.747% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 3
Path Summary:| Slack | 9.946 |
| Data Arrival Time | 10.380 |
| Data Required Time | 20.326 |
| From | u_pwm/duty_cycle_int_1_s1 |
| To | u_pwm/duty_cycle_int_7_s1 |
| Launch Clk | pclk[R] |
| Latch Clk | pclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | pclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | pclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 60 | pclk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | u_pwm/duty_cycle_int_1_s1/CLK |
| 1.184 | 0.458 | tC2Q | RF | 7 | u_pwm/duty_cycle_int_1_s1/Q |
| 2.144 | 0.960 | tNET | FF | 1 | u_pwm/n65_s8/I1 |
| 3.243 | 1.099 | tINS | FF | 7 | u_pwm/n65_s8/F |
| 4.203 | 0.960 | tNET | FF | 1 | u_pwm/n67_s4/I1 |
| 5.302 | 1.099 | tINS | FF | 1 | u_pwm/n67_s4/F |
| 6.262 | 0.960 | tNET | FF | 1 | u_pwm/n67_s2/I1 |
| 7.361 | 1.099 | tINS | FF | 1 | u_pwm/n67_s2/F |
| 8.321 | 0.960 | tNET | FF | 1 | u_pwm/n67_s0/I1 |
| 9.420 | 1.099 | tINS | FF | 1 | u_pwm/n67_s0/F |
| 10.380 | 0.960 | tNET | FF | 1 | u_pwm/duty_cycle_int_7_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | pclk | |||
| 20.000 | 0.000 | tCL | RR | 1 | pclk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 60 | pclk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | u_pwm/duty_cycle_int_7_s1/CLK |
| 20.326 | -0.400 | tSu | 1 | u_pwm/duty_cycle_int_7_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 4.396, 45.534%; route: 4.800, 49.719%; tC2Q: 0.458, 4.747% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 4
Path Summary:| Slack | 10.013 |
| Data Arrival Time | 10.313 |
| Data Required Time | 20.326 |
| From | u_pwm/duty_cycle_int_1_s1 |
| To | u_pwm/duty_cycle_int_4_s1 |
| Launch Clk | pclk[R] |
| Latch Clk | pclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | pclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | pclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 60 | pclk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | u_pwm/duty_cycle_int_1_s1/CLK |
| 1.184 | 0.458 | tC2Q | RF | 7 | u_pwm/duty_cycle_int_1_s1/Q |
| 2.144 | 0.960 | tNET | FF | 1 | u_pwm/n69_s3/I1 |
| 3.243 | 1.099 | tINS | FF | 6 | u_pwm/n69_s3/F |
| 4.203 | 0.960 | tNET | FF | 1 | u_pwm/n70_s6/I1 |
| 5.302 | 1.099 | tINS | FF | 1 | u_pwm/n70_s6/F |
| 6.262 | 0.960 | tNET | FF | 1 | u_pwm/n70_s1/I1 |
| 7.361 | 1.099 | tINS | FF | 1 | u_pwm/n70_s1/F |
| 8.321 | 0.960 | tNET | FF | 1 | u_pwm/n70_s7/I0 |
| 9.353 | 1.032 | tINS | FF | 1 | u_pwm/n70_s7/F |
| 10.313 | 0.960 | tNET | FF | 1 | u_pwm/duty_cycle_int_4_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | pclk | |||
| 20.000 | 0.000 | tCL | RR | 1 | pclk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 60 | pclk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | u_pwm/duty_cycle_int_4_s1/CLK |
| 20.326 | -0.400 | tSu | 1 | u_pwm/duty_cycle_int_4_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 4.329, 45.153%; route: 4.800, 50.066%; tC2Q: 0.458, 4.781% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 5
Path Summary:| Slack | 10.013 |
| Data Arrival Time | 10.313 |
| Data Required Time | 20.326 |
| From | u_pwm/duty_cycle_int_1_s1 |
| To | u_pwm/duty_cycle_int_9_s1 |
| Launch Clk | pclk[R] |
| Latch Clk | pclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | pclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | pclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 60 | pclk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | u_pwm/duty_cycle_int_1_s1/CLK |
| 1.184 | 0.458 | tC2Q | RF | 7 | u_pwm/duty_cycle_int_1_s1/Q |
| 2.144 | 0.960 | tNET | FF | 1 | u_pwm/n65_s8/I1 |
| 3.243 | 1.099 | tINS | FF | 7 | u_pwm/n65_s8/F |
| 4.203 | 0.960 | tNET | FF | 1 | u_pwm/n65_s4/I1 |
| 5.302 | 1.099 | tINS | FF | 1 | u_pwm/n65_s4/F |
| 6.262 | 0.960 | tNET | FF | 1 | u_pwm/n65_s2/I0 |
| 7.294 | 1.032 | tINS | FF | 1 | u_pwm/n65_s2/F |
| 8.254 | 0.960 | tNET | FF | 1 | u_pwm/n65_s0/I1 |
| 9.353 | 1.099 | tINS | FF | 1 | u_pwm/n65_s0/F |
| 10.313 | 0.960 | tNET | FF | 1 | u_pwm/duty_cycle_int_9_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | pclk | |||
| 20.000 | 0.000 | tCL | RR | 1 | pclk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 60 | pclk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | u_pwm/duty_cycle_int_9_s1/CLK |
| 20.326 | -0.400 | tSu | 1 | u_pwm/duty_cycle_int_9_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 4.329, 45.153%; route: 4.800, 50.066%; tC2Q: 0.458, 4.781% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |