PnR Messages

Report Title PnR Report
Design File E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_PWM_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_PWM_RefDesign\project\src\fpga_project.cst
Timing Constraints File E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_PWM_RefDesign\project\src\fpga_project.sdc
Tool Version V1.9.11.02 (64-bit)
Part Number GW1N-LV9QN88C6/I5
Device GW1N-9
Device Version C
Created Time Tue Apr 15 15:23:05 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.181s, Elapsed time = 0h 0m 0.181s Placement Phase 1: CPU time = 0h 0m 0.004s, Elapsed time = 0h 0m 0.005s Placement Phase 2: CPU time = 0h 0m 0.028s, Elapsed time = 0h 0m 0.028s Placement Phase 3: CPU time = 0h 0m 0.716s, Elapsed time = 0h 0m 0.716s Total Placement: CPU time = 0h 0m 0.929s, Elapsed time = 0h 0m 0.93s Running routing: Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Routing Phase 1: CPU time = 0h 0m 0.17s, Elapsed time = 0h 0m 0.17s Routing Phase 2: CPU time = 0h 0m 0.178s, Elapsed time = 0h 0m 0.179s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 0.348s, Elapsed time = 0h 0m 0.349s Generate output files: CPU time = 0h 0m 0.869s, Elapsed time = 0h 0m 0.869s
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 491MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 311/8640 4%
    --LUT,ALU,ROM16 275(251 LUT, 24 ALU, 0 ROM16) -
    --SSRAM(RAM16) 6 -
Register 223/6693 4%
    --Logic Register as Latch 0/6480 0%
    --Logic Register as FF 223/6480 4%
    --I/O Register as Latch 0/213 0%
    --I/O Register as FF 0/213 0%
CLS 262/4320 7%
I/O Port 7/71 10%
I/O Buf 7 -
    --Input Buf 4 -
    --Output Buf 3 -
    --Inout Buf 0 -
IOLOGIC 1 OSER8
 3%

I/O Bank Usage Summary:

I/O Bank UsageUtilization
bank 1 0/250%
bank 2 2/239%
bank 3 5/2322%

Clock Resource Usage Summary:

Clock Resource Usage Utilization
PRIMARY 2/8 25%
LW 1/8 13%
GCLK_PIN 1/3 34%
CLKDIV 1/8 13%
rPLL 1/2 50%

Global Clock Signals:

Signal Global Clock Location
pclk_d PRIMARY BL
gw_gvio_inst_0/control0[0] PRIMARY TL BL
gw_gvio_inst_0/gvio_jtag_reset LW -
clk_d HCLK TOP[0]
fclk HCLK BOTTOM[0]

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
clk - 11/3 Y in IOL15[A] GCLKT_6 LVCMOS33 NA NONE ON NONE NA NA OFF NA 3.3
tms_pad_i - 5/3 N in IOL11[A] TMS LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
tck_pad_i - 6/3 N in IOL11[B] TCK LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
tdi_pad_i - 7/3 N in IOL12[B] TDI LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
pwm - 26/2 Y out IOB8[B] - LVCMOS33 24 NONE NA NA OFF NA NA NA 3.3
pclk - 34/2 Y out IOB23[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
tdo_pad_o - 8/3 N out IOL13[A] TDO LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3

All Package Pins:

Loc./Bank Signal Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
88/3 - in IOT5[A] MODE0 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
87/3 - in IOT6[B] MODE1 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
86/3 - in IOT8[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
85/3 - in IOT8[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
84/3 - in IOT10[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
83/3 - in IOT10[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
82/3 - in IOT11[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
81/3 - in IOT11[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
80/3 - in IOT12[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
79/3 - in IOT12[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
77/1 - in IOT37[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
76/1 - in IOT37[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
75/1 - in IOT38[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
74/1 - in IOT38[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
73/1 - in IOT39[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
72/1 - in IOT39[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
71/1 - in IOT41[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
70/1 - in IOT41[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
69/1 - in IOT42[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
68/1 - in IOT42[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
17/2 - in IOB2[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
18/2 - in IOB2[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
19/2 - in IOB4[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
20/2 - in IOB4[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
25/2 - in IOB8[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
26/2 pwm out IOB8[B] - LVCMOS33 24 NONE NA NA OFF NA NA NA 3.3
27/2 - in IOB11[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
28/2 - in IOB11[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
29/2 - in IOB13[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
30/2 - in IOB13[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
31/2 - in IOB17[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
32/2 - in IOB17[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
33/2 - in IOB23[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
34/2 pclk out IOB23[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
35/2 - in IOB29[A] GCLKT_4 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
36/2 - in IOB29[B] GCLKC_4 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
37/2 - in IOB31[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
38/2 - in IOB31[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
39/2 - in IOB33[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
40/2 - in IOB33[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
41/2 - in IOB41[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
42/2 - in IOB41[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
47/2 - in IOB43[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
3/3 - in IOL2[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
4/3 - in IOL5[A] JTAGSEL_N/LPLL_T_in LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
5/3 tms_pad_i in IOL11[A] TMS LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
6/3 tck_pad_i in IOL11[B] TCK LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
7/3 tdi_pad_i in IOL12[B] TDI LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
8/3 tdo_pad_o out IOL13[A] TDO LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
9/3 - in IOL13[B] RECONFIG_N LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
10/3 - in IOL14[A] DONE LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
11/3 clk in IOL15[A] GCLKT_6 LVCMOS33 NA NONE ON NONE NA NA OFF NA 3.3
13/3 - in IOL22[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
14/3 - in IOL22[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
15/3 - in IOL26[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
16/3 - in IOL26[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
63/1 - in IOR5[A] RPLL_T_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
62/1 - in IOR11[A] MI/D7 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
61/1 - in IOR11[B] MO/D6 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
60/1 - in IOR12[A] MCS_N/D5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
59/1 - in IOR12[B] MCLK/D4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
57/1 - in IOR13[A] FASTRD_N/D3 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
56/1 - in IOR14[A] SO/D1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
55/1 - in IOR14[B] SSPI_CS_N/D0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
54/1 - in IOR15[A] DIN/CLKHOLD_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
53/1 - in IOR15[B] DOUT/WE_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
52/1 - in IOR17[A] GCLKT_3 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
51/1 - in IOR17[B] GCLKC_3 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
50/1 - in IOR22[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
49/1 - in IOR24[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
48/1 - in IOR24[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8