Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_soc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_ddr3.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_flash.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\ddr3_1_4code_hs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\DDR3_TOP.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\fifo_top_32to128.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\fifo_top_128to32.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\gw_dtcm.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\gw_itcm.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.02 (64-bit) |
| Part Number | GW5AST-LV138FPG676AC1/I0 |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Tue May 6 13:57:04 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | RiscV_AE350_SOC_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 148.102MB Running netlist conversion: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.11s, Peak memory usage = 148.102MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.875s, Elapsed time = 0h 0m 0.875s, Peak memory usage = 148.102MB Optimizing Phase 1: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.378s, Peak memory usage = 148.102MB Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 148.102MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.536s, Peak memory usage = 148.102MB Inferring Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 148.102MB Inferring Phase 2: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.121s, Peak memory usage = 148.102MB Inferring Phase 3: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 148.102MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 148.102MB Tech-Mapping Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 148.102MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.671s, Elapsed time = 0h 0m 0.664s, Peak memory usage = 148.102MB Tech-Mapping Phase 3: CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s, Peak memory usage = 156.016MB Tech-Mapping Phase 4: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 156.016MB Generate output files: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 221.418MB |
| Total Time and Memory Usage | CPU time = 0h 0m 19s, Elapsed time = 0h 0m 19s, Peak memory usage = 221.418MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 209 |
| I/O Buf | 206 |
| IBUF | 70 |
| OBUF | 109 |
| TBUF | 2 |
| IOBUF | 22 |
| ELVDS_OBUF | 1 |
| ELVDS_IOBUF | 2 |
| Register | 8251 |
| DFFSE | 1 |
| DFFRE | 4330 |
| DFFPE | 89 |
| DFFCE | 3830 |
| DLCE | 1 |
| LUT | 5488 |
| LUT2 | 458 |
| LUT3 | 1321 |
| LUT4 | 3709 |
| ALU | 220 |
| ALU | 220 |
| INV | 38 |
| INV | 38 |
| IOLOGIC | 76 |
| IDES8_MEM | 16 |
| OSER8 | 24 |
| OSER8_MEM | 20 |
| IODELAY | 16 |
| BSRAM | 12 |
| SDPB | 4 |
| SDPX9B | 8 |
| CLOCK | 4 |
| CLKDIV | 1 |
| DQS | 2 |
| DDRDLL | 1 |
| AE350_SOC | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 5746(5526 LUT, 220 ALU) / 138240 | 5% |
| Register | 8251 / 139140 | 6% |
| --Register as Latch | 1 / 139140 | <1% |
| --Register as FF | 8250 / 139140 | 6% |
| BSRAM | 12 / 340 | 4% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | DDR3_MEMORY_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | DDR3_MEMORY_CLK_ibuf/I | ||
| 2 | AHB_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | AHB_CLK_ibuf/I | ||
| 3 | FLASH_SPI_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | FLASH_SPI_CLK_iobuf/IO | ||
| 4 | DDR3_CLK_IN | Base | 10.000 | 100.000 | 0.000 | 5.000 | DDR3_CLK_IN_ibuf/I | ||
| 5 | DDR_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | DDR_CLK_ibuf/I | ||
| 6 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 40.000 | 25.000 | 0.000 | 20.000 | DDR3_MEMORY_CLK_ibuf/I | DDR3_MEMORY_CLK | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | DDR3_MEMORY_CLK | 100.000(MHz) | 1115.449(MHz) | 1 | TOP |
| 2 | AHB_CLK | 100.000(MHz) | 80.653(MHz) | 14 | TOP |
| 3 | DDR3_CLK_IN | 100.000(MHz) | 173.310(MHz) | 6 | TOP |
| 4 | DDR_CLK | 100.000(MHz) | 224.090(MHz) | 5 | TOP |
| 5 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 25.000(MHz) | 161.225(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -2.399 |
| Data Arrival Time | 12.748 |
| Data Required Time | 10.349 |
| From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0 |
| To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s3 |
| Launch Clk | AHB_CLK[R] |
| Latch Clk | AHB_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | AHB_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 4323 | AHB_CLK_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 26 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_trans_end_sclk_Z_s0/I0 |
| 1.786 | 0.579 | tINS | RR | 7 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_trans_end_sclk_Z_s0/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s10/I0 |
| 2.778 | 0.579 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s10/F |
| 3.190 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s8/I1 |
| 3.758 | 0.567 | tINS | RR | 7 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s8/F |
| 4.170 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/n332_s2/I0 |
| 4.749 | 0.579 | tINS | RR | 5 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/n332_s2/F |
| 5.161 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s15/I0 |
| 5.740 | 0.579 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s15/F |
| 6.153 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s4/I1 |
| 6.720 | 0.567 | tINS | RR | 6 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s4/F |
| 7.133 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/I2 |
| 7.640 | 0.507 | tINS | RR | 34 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/F |
| 8.053 | 0.413 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1 |
| 8.653 | 0.600 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT |
| 8.653 | 0.000 | tNET | FF | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN |
| 8.703 | 0.050 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT |
| 8.703 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN |
| 8.753 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT |
| 8.753 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN |
| 8.803 | 0.050 | tINS | RR | 12 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT |
| 9.215 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/I0 |
| 9.794 | 0.579 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/F |
| 10.206 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s6/I3 |
| 10.495 | 0.289 | tINS | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s6/F |
| 10.908 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s15/I2 |
| 11.415 | 0.507 | tINS | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s15/F |
| 11.828 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n503_s6/I2 |
| 12.335 | 0.507 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n503_s6/F |
| 12.748 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s3/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | AHB_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 4323 | AHB_CLK_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s3/CLK |
| 10.349 | -0.064 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s3 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 14 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 6.590, 53.425%; route: 5.362, 43.474%; tC2Q: 0.382, 3.101% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:| Slack | -1.726 |
| Data Arrival Time | 11.828 |
| Data Required Time | 10.101 |
| From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0 |
| To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1 |
| Launch Clk | AHB_CLK[R] |
| Latch Clk | AHB_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | AHB_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 4323 | AHB_CLK_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 26 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_trans_end_sclk_Z_s0/I0 |
| 1.786 | 0.579 | tINS | RR | 7 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_trans_end_sclk_Z_s0/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s10/I0 |
| 2.778 | 0.579 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s10/F |
| 3.190 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s8/I1 |
| 3.758 | 0.567 | tINS | RR | 7 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s8/F |
| 4.170 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/n332_s2/I0 |
| 4.749 | 0.579 | tINS | RR | 5 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/n332_s2/F |
| 5.161 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s15/I0 |
| 5.740 | 0.579 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s15/F |
| 6.153 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s4/I1 |
| 6.720 | 0.567 | tINS | RR | 6 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s4/F |
| 7.133 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/I2 |
| 7.640 | 0.507 | tINS | RR | 34 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/F |
| 8.053 | 0.413 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1 |
| 8.653 | 0.600 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT |
| 8.653 | 0.000 | tNET | FF | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN |
| 8.703 | 0.050 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT |
| 8.703 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN |
| 8.753 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT |
| 8.753 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN |
| 8.803 | 0.050 | tINS | RR | 12 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT |
| 9.215 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/I0 |
| 9.794 | 0.579 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/F |
| 10.206 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s6/I3 |
| 10.495 | 0.289 | tINS | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s6/F |
| 10.908 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s15/I2 |
| 11.415 | 0.507 | tINS | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s15/F |
| 11.828 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | AHB_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 4323 | AHB_CLK_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1/CLK |
| 10.101 | -0.311 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 13 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 6.083, 53.285%; route: 4.950, 43.364%; tC2Q: 0.382, 3.351% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:| Slack | -1.726 |
| Data Arrival Time | 11.828 |
| Data Required Time | 10.101 |
| From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0 |
| To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1 |
| Launch Clk | AHB_CLK[R] |
| Latch Clk | AHB_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | AHB_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 4323 | AHB_CLK_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 26 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_trans_end_sclk_Z_s0/I0 |
| 1.786 | 0.579 | tINS | RR | 7 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_trans_end_sclk_Z_s0/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s10/I0 |
| 2.778 | 0.579 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s10/F |
| 3.190 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s8/I1 |
| 3.758 | 0.567 | tINS | RR | 7 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s8/F |
| 4.170 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/n332_s2/I0 |
| 4.749 | 0.579 | tINS | RR | 5 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/n332_s2/F |
| 5.161 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s15/I0 |
| 5.740 | 0.579 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s15/F |
| 6.153 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s4/I1 |
| 6.720 | 0.567 | tINS | RR | 6 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s4/F |
| 7.133 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/I2 |
| 7.640 | 0.507 | tINS | RR | 34 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/F |
| 8.053 | 0.413 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1 |
| 8.653 | 0.600 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT |
| 8.653 | 0.000 | tNET | FF | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN |
| 8.703 | 0.050 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT |
| 8.703 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN |
| 8.753 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT |
| 8.753 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN |
| 8.803 | 0.050 | tINS | RR | 12 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT |
| 9.215 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/I0 |
| 9.794 | 0.579 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/F |
| 10.206 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s6/I3 |
| 10.495 | 0.289 | tINS | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s6/F |
| 10.908 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s15/I2 |
| 11.415 | 0.507 | tINS | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s15/F |
| 11.828 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | AHB_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 4323 | AHB_CLK_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1/CLK |
| 10.101 | -0.311 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 13 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 6.083, 53.285%; route: 4.950, 43.364%; tC2Q: 0.382, 3.351% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:| Slack | -1.726 |
| Data Arrival Time | 11.828 |
| Data Required Time | 10.101 |
| From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0 |
| To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_3_s1 |
| Launch Clk | AHB_CLK[R] |
| Latch Clk | AHB_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | AHB_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 4323 | AHB_CLK_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 26 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_trans_end_sclk_Z_s0/I0 |
| 1.786 | 0.579 | tINS | RR | 7 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_trans_end_sclk_Z_s0/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s10/I0 |
| 2.778 | 0.579 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s10/F |
| 3.190 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s8/I1 |
| 3.758 | 0.567 | tINS | RR | 7 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s8/F |
| 4.170 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/n332_s2/I0 |
| 4.749 | 0.579 | tINS | RR | 5 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/n332_s2/F |
| 5.161 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s15/I0 |
| 5.740 | 0.579 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s15/F |
| 6.153 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s4/I1 |
| 6.720 | 0.567 | tINS | RR | 6 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s4/F |
| 7.133 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/I2 |
| 7.640 | 0.507 | tINS | RR | 34 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/F |
| 8.053 | 0.413 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1 |
| 8.653 | 0.600 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT |
| 8.653 | 0.000 | tNET | FF | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN |
| 8.703 | 0.050 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT |
| 8.703 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN |
| 8.753 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT |
| 8.753 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN |
| 8.803 | 0.050 | tINS | RR | 12 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT |
| 9.215 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/I0 |
| 9.794 | 0.579 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/F |
| 10.206 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s6/I3 |
| 10.495 | 0.289 | tINS | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s6/F |
| 10.908 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s15/I2 |
| 11.415 | 0.507 | tINS | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s15/F |
| 11.828 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_3_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | AHB_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 4323 | AHB_CLK_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_3_s1/CLK |
| 10.101 | -0.311 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_3_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 13 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 6.083, 53.285%; route: 4.950, 43.364%; tC2Q: 0.382, 3.351% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:| Slack | -1.726 |
| Data Arrival Time | 11.828 |
| Data Required Time | 10.101 |
| From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0 |
| To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_4_s1 |
| Launch Clk | AHB_CLK[R] |
| Latch Clk | AHB_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | AHB_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 4323 | AHB_CLK_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 26 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_trans_end_sclk_Z_s0/I0 |
| 1.786 | 0.579 | tINS | RR | 7 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_trans_end_sclk_Z_s0/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s10/I0 |
| 2.778 | 0.579 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s10/F |
| 3.190 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s8/I1 |
| 3.758 | 0.567 | tINS | RR | 7 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s8/F |
| 4.170 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/n332_s2/I0 |
| 4.749 | 0.579 | tINS | RR | 5 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/n332_s2/F |
| 5.161 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s15/I0 |
| 5.740 | 0.579 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s15/F |
| 6.153 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s4/I1 |
| 6.720 | 0.567 | tINS | RR | 6 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s4/F |
| 7.133 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/I2 |
| 7.640 | 0.507 | tINS | RR | 34 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/F |
| 8.053 | 0.413 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1 |
| 8.653 | 0.600 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT |
| 8.653 | 0.000 | tNET | FF | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN |
| 8.703 | 0.050 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT |
| 8.703 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN |
| 8.753 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT |
| 8.753 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN |
| 8.803 | 0.050 | tINS | RR | 12 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT |
| 9.215 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/I0 |
| 9.794 | 0.579 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/F |
| 10.206 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s6/I3 |
| 10.495 | 0.289 | tINS | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s6/F |
| 10.908 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s15/I2 |
| 11.415 | 0.507 | tINS | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s15/F |
| 11.828 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_4_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | AHB_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 4323 | AHB_CLK_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_4_s1/CLK |
| 10.101 | -0.311 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_4_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 13 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 6.083, 53.285%; route: 4.950, 43.364%; tC2Q: 0.382, 3.351% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |