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         IIR Filter 参考设计阅读指南
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目标器件：GW2A-LV18PG256C8/I7
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文件列表
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.
| -- doc
|    `-- readme.txt				-->	自述文件
| -- Ref_Design
|    `-- Ref_Design.gprj			-->	参考设计工程
|    |-- impl
|    |-- src
|        `-- data
|        |   `-- coeff_a.dat			-->	初始化系数文件(十进制)
|        |   |-- coeff_b.dat			-->	初始化数文件(十进制)
|        |-- iir_filter
|        |   `-- iir_filter.ipc
|        |   |-- iir_filter.v
|        |   |-- iir_filter_tmp.v
|        |   |-- iir_filter.vo			-->	仿真使用vo文件
|        |-- exp_iir.v				-->	工程顶层模块
|        |-- data_in.dat				-->	输入数据文件（二进制）
|        |-- Default.cst
|        |-- fpga_project.gao
| -- simulation
|        `-- Modelsim
|        |   `-- cmd.do				-->	modelsim仿真脚本
|        |   |-- data_in.dat			-->	输入数据文件（二进制）
|        |-- VCS_SIM
|        |    `-- makefile				-->	vcs仿真脚本
|        |    |-- data_in.dat			-->	输入数据文件（二进制）
| -- tb
     `-- tb_vcs.v				-->	vcs仿真testbench
     |-- tb_mod.v				-->	modelsim仿真testbench
     |-- prim_sim.v				-->	仿真原语库

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使用说明：
	1、板测：使用云源软件打开上述文件中Ref_Design.gprj，设置工程顶层模块，将src设置为加载路径，综合；根据所使用器件设置约束和gao.v后布局布线后下载测试。使用GAO抓取数据。
	2、modelsim仿真：仿真脚本存放于Modelsim文件夹中
	3、vcs仿真：在VCS_SIM中，运行“make vcs”，执行仿真；运行“make vd”,打开使用verdi查看波形；运行“make clean”，清除仿真产生的文件。

	注：tb文件夹下prim_sim.v仅供参考，建议用户根据情况在仿真时使用最新版替换。

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        Example IIR Filter Design Readme
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Object device:GW2A-LV18PG256C8/I7
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File List:
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.
| -- doc
|    `-- readme.txt				-->	Read Me file (this file)
| -- Ref_Design
|    `-- Ref_Design.gprj			-->	GowinYunYuan Project File for Example Design
|    |-- impl
|    |-- src
|        `-- data
|        |   `-- coeff_a.dat			-->	Initialization coefficient file(DEC)
|        |   |-- coeff_b.dat			-->	Initialization coefficient file(DEC)
|        |-- iir_filter
|        |   `-- iir_filter.ipc
|        |   |-- iir_filter.v
|        |   |-- iir_filter_tmp.v
|        |   |-- iir_filter.vo			-->	Verilog simulation File for tb
|        |-- exp_iir.v				-->	File for GowinYunYuan Project
|        |-- data_in.dat				-->	Input data file(BIN)）
|        |-- Default.cst
|        |-- fpga_project.gao
| -- simulation
|        `-- Modelsim
|        |   `-- cmd.do				-->	modelsim simulation script
|        |    |-- data_in.dat			-->	Input data file(BIN)）
|        |-- VCS_SIM
|            `-- makefile				-->	vcs simulation script
|        |    |-- data_in.dat			-->	Input data file(BIN)）
| -- tb
     `-- tb_vcs.v				-->	TestBench for vcs simulation
     |-- tb_mod.v				-->	TestBench for modelsim simulation
     |-- prim_sim.v				-->	Verilog functional simulation library
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Instructions:
	1、Onboard test:Launch GowinYunYuan and select "File -> Open -> Project", set Top Module and Include Path. After Sythesize, cofigure Physical Constraints and GAO Config Files.
	2、modelsim simulation:Use script in Modelsim folder.
	3、VCS simulation: Open the terminal window in the above VCS_SIM folder and enter the "make vcs" command to simulate, enter the "make vd" command to view the waveform, enter the "make clean" command to clear the generated files.