#Build: Synplify Pro (R) P-2019.03G-Beta4, Build 231R, Aug 2 2019 #install: C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro #OS: Windows 8 6.2 #Hostname: GW-SW-063 # Tue Sep 29 16:33:26 2020 #Implementation: rev_1 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.03G-Beta4 Install: C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro OS: Windows 6.2 Hostname: GW-SW-063 Implementation : rev_1 Synopsys HDL Compiler, Version comp2019q1p1, Build 231R, Built Aug 2 2019 09:58:27 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.03G-Beta4 Install: C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro OS: Windows 6.2 Hostname: GW-SW-063 Implementation : rev_1 Synopsys Verilog Compiler, Version comp2019q1p1, Build 231R, Built Aug 2 2019 09:58:27 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\generic\gw2a.v" (library work) @I::"C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"E:\W_File\IIR\chunxiang\Gowin_IIR_Filter_RefDesign\Ref_Design\temp\gao\ao_0\gw_ao_parameter.v" (library work) @I::"E:\W_File\IIR\chunxiang\Gowin_IIR_Filter_RefDesign\Ref_Design\temp\gao\ao_0\gw_ao_top_define.v" (library work) @I::"E:\W_File\IIR\chunxiang\Gowin_IIR_Filter_RefDesign\Ref_Design\temp\gao\ao_0\gw_ao_expression.v" (library work) @I::"C:\Gowin\Gowin_V1.9.1Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v" (library work) @I::"C:\Gowin\Gowin_V1.9.1Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_define.v" (library work) @I::"C:\Gowin\Gowin_V1.9.1Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v" (library work) @W:CG1337 : gw_ao_match.v(109) | Net match_m0_en_reg_wr is not declared. @W:CG1337 : gw_ao_match.v(110) | Net match_m1_en_reg_wr is not declared. @W:CG1337 : gw_ao_match.v(111) | Net match_m2_en_reg_wr is not declared. @W:CG1337 : gw_ao_match.v(112) | Net match_ctl_en_reg_wr is not declared. @W:CG1337 : gw_ao_match.v(113) | Net match_cnt_reg_wr is not declared. @I::"C:\Gowin\Gowin_V1.9.1Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v" (library work) @W:CG1337 : gw_ao_mem_ctrl.v(122) | Net capture_length_zero is not declared. @I::"C:\Gowin\Gowin_V1.9.1Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v" (library work) @W:CG1337 : gw_ao_top.v(500) | Net start_reg_wr is not declared. @W:CG1337 : gw_ao_top.v(503) | Net trig_level_max_reg_wr is not declared. @W:CG1337 : gw_ao_top.v(504) | Net capture_mem_addr_max_wr is not declared. @W:CG1337 : gw_ao_top.v(505) | Net capture_mem_addr_rem_wr is not declared. @W:CG1337 : gw_ao_top.v(506) | Net capture_windows_num_wr is not declared. @W:CG1337 : gw_ao_top.v(1717) | Net match_en_0 is not declared. @W:CG1337 : gw_ao_top.v(1718) | Net match_en_1 is not declared. @W:CG1337 : gw_ao_top.v(1719) | Net match_en_2 is not declared. @W:CG1337 : gw_ao_top.v(1720) | Net match_en_3 is not declared. @W:CG1337 : gw_ao_top.v(1721) | Net match_en_4 is not declared. @W:CG1337 : gw_ao_top.v(1722) | Net match_en_5 is not declared. @W:CG1337 : gw_ao_top.v(1723) | Net match_en_6 is not declared. @W:CG1337 : gw_ao_top.v(1724) | Net match_en_7 is not declared. @W:CG1337 : gw_ao_top.v(1725) | Net match_en_8 is not declared. @W:CG1337 : gw_ao_top.v(1726) | Net match_en_9 is not declared. @W:CG1337 : gw_ao_top.v(1727) | Net match_en_10 is not declared. @W:CG1337 : gw_ao_top.v(1728) | Net match_en_11 is not declared. @W:CG1337 : gw_ao_top.v(1729) | Net match_en_12 is not declared. @W:CG1337 : gw_ao_top.v(1730) | Net match_en_13 is not declared. @W:CG1337 : gw_ao_top.v(1731) | Net match_en_14 is not declared. @W:CG1337 : gw_ao_top.v(1732) | Net match_en_15 is not declared. @W:CG1337 : gw_ao_top.v(2213) | Net stop_reg is not declared. Verilog syntax check successful! @N:CG364 : gw_ao_parameter.v(1) | Synthesizing module work_E:\W_File\IIR\chunxiang\Gowin_IIR_Filter_RefDesign\Ref_Design\temp\gao\ao_0\gw_ao_parameter.v_unit in library work. Selecting top level module ao_top_0 Running optimization stage 1 on ao_mem_ctrl_0_1024s_20s_10s ....... Running optimization stage 1 on ao_crc32_0 ....... Running optimization stage 1 on ao_match_0_0s_1s_20s_0_1_0_1_2_3_4 ....... Running optimization stage 1 on ao_top_0 ....... Running optimization stage 2 on ao_match_0_0s_1s_20s_0_1_0_1_2_3_4 ....... Running optimization stage 2 on ao_top_0 ....... Extracted state machine for register module_state State machine has 11 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1001 1010 1011 Running optimization stage 2 on ao_crc32_0 ....... Running optimization stage 2 on ao_mem_ctrl_0_1024s_20s_10s ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 97MB peak: 106MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Sep 29 16:33:28 2020 ###########################################################] ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.03G-Beta4 Install: C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro OS: Windows 6.2 Hostname: GW-SW-063 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 231R, Built Aug 2 2019 09:58:27 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 89MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Sep 29 16:33:29 2020 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: ao_0_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 19MB peak: 20MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime Process completed successfully. # Tue Sep 29 16:33:29 2020 ###########################################################] ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.03G-Beta4 Install: C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro OS: Windows 6.2 Hostname: GW-SW-063 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 231R, Built Aug 2 2019 09:58:27 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 88MB peak: 90MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Sep 29 16:33:31 2020 ###########################################################] Premap Report # Tue Sep 29 16:33:31 2020 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.03G-Beta4 Install: C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro OS: Windows 6.2 Hostname: GW-SW-063 Implementation : rev_1 Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1429R, Built Aug 27 2019 09:36:45 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) @A:MF827 : | No constraint file specified. Linked File: ao_0_scck.rpt Printing clock summary report in "E:\W_File\IIR\chunxiang\Gowin_IIR_Filter_RefDesign\Ref_Design\temp\gao\ao_0\rev_1\ao_0_scck.rpt" file @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) @N:BN133 : | Ignoring syn_hier=hard property on top-level design. Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) Encoding state machine module_state[10:0] (in view: work.ao_top_0(verilog)) original code -> new code 0000 -> 00000000001 0001 -> 00000000010 0010 -> 00000000100 0011 -> 00000001000 0100 -> 00000010000 0101 -> 00000100000 0110 -> 00001000000 0111 -> 00010000000 1001 -> 00100000000 1010 -> 01000000000 1011 -> 10000000000 Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB) Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB) Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB) Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ---------------------------------------------------------------------------------------------------------- 0 - ao_top_0|control[0] 186.5 MHz 5.362 inferred Autoconstr_clkgroup_1 261 0 - ao_top_0|clk_i 237.7 MHz 4.207 inferred Autoconstr_clkgroup_0 81 ========================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example -------------------------------------------------------------------------------------------------------------------------------------- ao_top_0|control[0] 261 control[0](port) data_register[40:0].C - - ao_top_0|clk_i 81 clk_i(port) internal_reg_force_triger_syn[1:0].C - clk_ao.I[0](keepbuf) ====================================================================================================================================== ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 2 non-gated/non-generated clock tree(s) driving 323 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId_0_0 ENCRYPTED port 62 ENCRYPTED ClockId_0_1 ENCRYPTED IO_port 261 ENCRYPTED ======================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ###### @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file E:\W_File\IIR\chunxiang\Gowin_IIR_Filter_RefDesign\Ref_Design\temp\gao\ao_0\rev_1\ao_0.sap. Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 223MB peak: 223MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 223MB peak: 223MB) Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 224MB peak: 224MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 144MB peak: 224MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Tue Sep 29 16:33:34 2020 ###########################################################] Map & Optimize Report # Tue Sep 29 16:33:34 2020 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.03G-Beta4 Install: C:\Gowin\Gowin_V1.9.1Beta\SynplifyPro OS: Windows 6.2 Hostname: GW-SW-063 Implementation : rev_1 Synopsys Generic Technology Mapper, Version mapgw, Build 1429R, Built Aug 27 2019 09:36:45 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 119MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 119MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 121MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 217MB peak: 217MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 221MB peak: 221MB) Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 224MB peak: 224MB) Finished factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 227MB peak: 227MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 229MB peak: 229MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 229MB peak: 229MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 229MB peak: 229MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 229MB peak: 229MB) Finished preparing to map (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 229MB peak: 229MB) Finished technology mapping (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 247MB peak: 247MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:03s -2.45ns 415 / 296 2 0h:00m:03s -2.30ns 422 / 296 3 0h:00m:04s -2.27ns 422 / 296 Timing driven replication report Added 2 Registers via timing driven replication Added 2 LUTs via timing driven replication 4 0h:00m:04s -2.27ns 438 / 298 5 0h:00m:04s -2.40ns 440 / 298 6 0h:00m:04s -2.27ns 440 / 298 7 0h:00m:04s -2.40ns 441 / 298 8 0h:00m:04s -2.27ns 444 / 298 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 248MB peak: 248MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. Finished restoring hierarchy (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 248MB peak: 248MB) Start Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 175MB peak: 249MB) Writing Analyst data base E:\W_File\IIR\chunxiang\Gowin_IIR_Filter_RefDesign\Ref_Design\temp\gao\ao_0\rev_1\synwork\ao_0_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 250MB peak: 250MB) Writing Verilog Simulation files Writing scf file... (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 251MB peak: 251MB) @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 251MB peak: 251MB) Start final timing analysis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 247MB peak: 251MB) @W:MT420 : | Found inferred clock ao_top_0|clk_i with period 4.33ns. Please declare a user-defined clock on port clk_i. @W:MT420 : | Found inferred clock ao_top_0|control[0] with period 5.48ns. Please declare a user-defined clock on port control[0]. ##### START OF TIMING REPORT #####[ # Timing report written on Tue Sep 29 16:33:43 2020 # Top view: ao_top_0 Requested Frequency: 182.4 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -0.968 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------- ao_top_0|clk_i 231.0 MHz 196.3 MHz 4.329 5.093 -0.764 inferred Autoconstr_clkgroup_0 ao_top_0|control[0] 182.4 MHz 155.0 MHz 5.483 6.450 -0.968 inferred Autoconstr_clkgroup_1 System 150.0 MHz 223.2 MHz 6.667 4.480 2.187 system system_clkgroup ============================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------------------------- System ao_top_0|clk_i | 4.329 2.187 | No paths - | No paths - | No paths - System ao_top_0|control[0] | 5.483 3.567 | No paths - | No paths - | No paths - ao_top_0|clk_i System | 4.329 3.551 | No paths - | No paths - | No paths - ao_top_0|clk_i ao_top_0|clk_i | 4.329 -0.764 | 4.329 3.490 | No paths - | 2.165 1.326 ao_top_0|clk_i ao_top_0|control[0] | Diff grp - | No paths - | No paths - | No paths - ao_top_0|control[0] System | 5.483 4.644 | No paths - | No paths - | No paths - ao_top_0|control[0] ao_top_0|clk_i | Diff grp - | No paths - | No paths - | No paths - ao_top_0|control[0] ao_top_0|control[0] | 5.483 -0.968 | No paths - | No paths - | No paths - ================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: ao_top_0|clk_i ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_length[0] ao_top_0|clk_i DFFC Q capture_length[0] 0.243 -0.764 u_ao_mem_ctrl.capture_length[1] ao_top_0|clk_i DFFC Q capture_length[1] 0.243 -0.729 u_ao_mem_ctrl.capture_length[2] ao_top_0|clk_i DFFC Q capture_length[2] 0.243 -0.694 u_ao_mem_ctrl.capture_length[3] ao_top_0|clk_i DFFP Q capture_length[3] 0.243 -0.659 internal_reg_force_triger_syn[1] ao_top_0|clk_i DFFC Q internal_reg_force_triger_syn[1] 0.243 -0.633 u_ao_mem_ctrl.capture_length[4] ao_top_0|clk_i DFFC Q capture_length[4] 0.243 -0.624 genblk1\.u_ao_match_0.match_sep ao_top_0|clk_i DFFC Q match 0.243 -0.612 u_ao_mem_ctrl.capture_length[5] ao_top_0|clk_i DFFC Q capture_length[5] 0.243 -0.589 u_ao_mem_ctrl.capture_length[6] ao_top_0|clk_i DFFC Q capture_length[6] 0.243 -0.554 triger_level_cnt[2] ao_top_0|clk_i DFFC Q triger_level_cnt[2] 0.243 -0.525 ================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.mem_addr_inc_en ao_top_0|clk_i DFFCE CE g0_3 4.268 -0.764 u_ao_mem_ctrl.capture_mem_wr ao_top_0|clk_i DFFCE CE g0_0 4.268 -0.633 triger_level_cnt[2] ao_top_0|clk_i DFFC D triger_level_cnt_4[2] 4.268 -0.041 u_ao_mem_ctrl.capture_loop ao_top_0|clk_i DFFCE CE un1_mem_addr_inc_en6 4.268 -0.022 u_ao_mem_ctrl.capture_mem_addr[0] ao_top_0|clk_i DFFCE D capture_mem_addr_lm[0] 4.268 -0.022 u_ao_mem_ctrl.capture_mem_addr[1] ao_top_0|clk_i DFFCE D capture_mem_addr_lm[1] 4.268 -0.022 u_ao_mem_ctrl.capture_mem_addr[2] ao_top_0|clk_i DFFCE D capture_mem_addr_lm[2] 4.268 -0.022 u_ao_mem_ctrl.capture_mem_addr[3] ao_top_0|clk_i DFFCE D capture_mem_addr_lm[3] 4.268 -0.022 u_ao_mem_ctrl.capture_mem_addr[4] ao_top_0|clk_i DFFCE D capture_mem_addr_lm[4] 4.268 -0.022 u_ao_mem_ctrl.capture_mem_addr[5] ao_top_0|clk_i DFFCE D capture_mem_addr_lm[5] 4.268 -0.022 ========================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 4.329 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.268 - Propagation time: 5.032 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.764 Number of logic level(s): 14 Starting point: u_ao_mem_ctrl.capture_length[0] / Q Ending point: u_ao_mem_ctrl.mem_addr_inc_en / CE The start point is clocked by ao_top_0|clk_i [rising] on pin CLK The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_length[0] DFFC Q Out 0.243 0.243 - capture_length[0] Net - - 0.535 - 4 u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU I0 In - 0.778 - u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU COUT Out 0.549 1.327 - capture_length_zero_cry_0 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU CIN In - 1.327 - u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU COUT Out 0.035 1.362 - capture_length_zero_cry_1 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU CIN In - 1.362 - u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU COUT Out 0.035 1.397 - capture_length_zero_cry_2 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU CIN In - 1.397 - u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU COUT Out 0.035 1.432 - capture_length_zero_cry_3 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU CIN In - 1.432 - u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU COUT Out 0.035 1.467 - capture_length_zero_cry_4 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU CIN In - 1.467 - u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU COUT Out 0.035 1.502 - capture_length_zero_cry_5 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU CIN In - 1.502 - u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU COUT Out 0.035 1.537 - capture_length_zero_cry_6 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU CIN In - 1.537 - u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU COUT Out 0.035 1.572 - capture_length_zero_cry_7 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU CIN In - 1.572 - u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU COUT Out 0.035 1.607 - capture_length_zero_cry_8 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_s_9_0 ALU CIN In - 1.607 - u_ao_mem_ctrl.capture_length_zero_s_9_0 ALU SUM Out 0.470 2.077 - capture_length_zero[9] Net - - 0.535 - 2 u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M LUT2 I1 In - 2.612 - u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M LUT2 F Out 0.570 3.182 - g3_4_0 Net - - 0.535 - 4 u_ao_mem_ctrl.g0_3_0_0 LUT4 I1 In - 3.717 - u_ao_mem_ctrl.g0_3_0_0 LUT4 F Out 0.570 4.287 - g0_3_0_0 Net - - 0.000 - 1 u_ao_mem_ctrl.g0_3_0 MUX2_LUT5 I0 In - 4.287 - u_ao_mem_ctrl.g0_3_0 MUX2_LUT5 O Out 0.105 4.392 - g0_3_0 Net - - 0.000 - 1 u_ao_mem_ctrl.g0_3 MUX2_LUT6 I0 In - 4.392 - u_ao_mem_ctrl.g0_3 MUX2_LUT6 O Out 0.105 4.497 - g0_3 Net - - 0.535 - 1 u_ao_mem_ctrl.mem_addr_inc_en DFFCE CE In - 5.032 - =================================================================================================================== Total path delay (propagation time + setup) of 5.093 is 2.953(58.0%) logic and 2.140(42.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 4.329 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.268 - Propagation time: 5.032 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.764 Number of logic level(s): 14 Starting point: u_ao_mem_ctrl.capture_length[0] / Q Ending point: u_ao_mem_ctrl.mem_addr_inc_en / CE The start point is clocked by ao_top_0|clk_i [rising] on pin CLK The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_length[0] DFFC Q Out 0.243 0.243 - capture_length[0] Net - - 0.535 - 4 u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU I0 In - 0.778 - u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU COUT Out 0.549 1.327 - capture_length_zero_cry_0 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU CIN In - 1.327 - u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU COUT Out 0.035 1.362 - capture_length_zero_cry_1 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU CIN In - 1.362 - u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU COUT Out 0.035 1.397 - capture_length_zero_cry_2 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU CIN In - 1.397 - u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU COUT Out 0.035 1.432 - capture_length_zero_cry_3 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU CIN In - 1.432 - u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU COUT Out 0.035 1.467 - capture_length_zero_cry_4 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU CIN In - 1.467 - u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU COUT Out 0.035 1.502 - capture_length_zero_cry_5 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU CIN In - 1.502 - u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU COUT Out 0.035 1.537 - capture_length_zero_cry_6 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU CIN In - 1.537 - u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU COUT Out 0.035 1.572 - capture_length_zero_cry_7 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU CIN In - 1.572 - u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU COUT Out 0.035 1.607 - capture_length_zero_cry_8 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_s_9_0 ALU CIN In - 1.607 - u_ao_mem_ctrl.capture_length_zero_s_9_0 ALU SUM Out 0.470 2.077 - capture_length_zero[9] Net - - 0.535 - 2 u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M LUT2 I1 In - 2.612 - u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M LUT2 F Out 0.570 3.182 - g3_4_0 Net - - 0.535 - 4 u_ao_mem_ctrl.g0_3_0_1 LUT4 I1 In - 3.717 - u_ao_mem_ctrl.g0_3_0_1 LUT4 F Out 0.570 4.287 - g0_3_0_1 Net - - 0.000 - 1 u_ao_mem_ctrl.g0_3_0 MUX2_LUT5 I1 In - 4.287 - u_ao_mem_ctrl.g0_3_0 MUX2_LUT5 O Out 0.105 4.392 - g0_3_0 Net - - 0.000 - 1 u_ao_mem_ctrl.g0_3 MUX2_LUT6 I0 In - 4.392 - u_ao_mem_ctrl.g0_3 MUX2_LUT6 O Out 0.105 4.497 - g0_3 Net - - 0.535 - 1 u_ao_mem_ctrl.mem_addr_inc_en DFFCE CE In - 5.032 - =================================================================================================================== Total path delay (propagation time + setup) of 5.093 is 2.953(58.0%) logic and 2.140(42.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 4.329 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.268 - Propagation time: 5.032 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.764 Number of logic level(s): 14 Starting point: u_ao_mem_ctrl.capture_length[0] / Q Ending point: u_ao_mem_ctrl.mem_addr_inc_en / CE The start point is clocked by ao_top_0|clk_i [rising] on pin CLK The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_length[0] DFFC Q Out 0.243 0.243 - capture_length[0] Net - - 0.535 - 4 u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU I0 In - 0.778 - u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU COUT Out 0.549 1.327 - capture_length_zero_cry_0 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU CIN In - 1.327 - u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU COUT Out 0.035 1.362 - capture_length_zero_cry_1 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU CIN In - 1.362 - u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU COUT Out 0.035 1.397 - capture_length_zero_cry_2 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU CIN In - 1.397 - u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU COUT Out 0.035 1.432 - capture_length_zero_cry_3 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU CIN In - 1.432 - u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU COUT Out 0.035 1.467 - capture_length_zero_cry_4 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU CIN In - 1.467 - u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU COUT Out 0.035 1.502 - capture_length_zero_cry_5 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU CIN In - 1.502 - u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU COUT Out 0.035 1.537 - capture_length_zero_cry_6 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU CIN In - 1.537 - u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU COUT Out 0.035 1.572 - capture_length_zero_cry_7 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU CIN In - 1.572 - u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU COUT Out 0.035 1.607 - capture_length_zero_cry_8 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_s_9_0 ALU CIN In - 1.607 - u_ao_mem_ctrl.capture_length_zero_s_9_0 ALU SUM Out 0.470 2.077 - capture_length_zero[9] Net - - 0.535 - 2 u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M LUT2 I1 In - 2.612 - u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M LUT2 F Out 0.570 3.182 - g3_4_0 Net - - 0.535 - 4 u_ao_mem_ctrl.g0_3_1_1 LUT4 I1 In - 3.717 - u_ao_mem_ctrl.g0_3_1_1 LUT4 F Out 0.570 4.287 - g0_3_1_1 Net - - 0.000 - 1 u_ao_mem_ctrl.g0_3_1 MUX2_LUT5 I1 In - 4.287 - u_ao_mem_ctrl.g0_3_1 MUX2_LUT5 O Out 0.105 4.392 - g0_3_1 Net - - 0.000 - 1 u_ao_mem_ctrl.g0_3 MUX2_LUT6 I1 In - 4.392 - u_ao_mem_ctrl.g0_3 MUX2_LUT6 O Out 0.105 4.497 - g0_3 Net - - 0.535 - 1 u_ao_mem_ctrl.mem_addr_inc_en DFFCE CE In - 5.032 - =================================================================================================================== Total path delay (propagation time + setup) of 5.093 is 2.953(58.0%) logic and 2.140(42.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 4.329 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.268 - Propagation time: 5.032 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.764 Number of logic level(s): 14 Starting point: u_ao_mem_ctrl.capture_length[0] / Q Ending point: u_ao_mem_ctrl.mem_addr_inc_en / CE The start point is clocked by ao_top_0|clk_i [rising] on pin CLK The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_length[0] DFFC Q Out 0.243 0.243 - capture_length[0] Net - - 0.535 - 4 u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU I0 In - 0.778 - u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU COUT Out 0.549 1.327 - capture_length_zero_cry_0 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU CIN In - 1.327 - u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU COUT Out 0.035 1.362 - capture_length_zero_cry_1 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU CIN In - 1.362 - u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU COUT Out 0.035 1.397 - capture_length_zero_cry_2 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU CIN In - 1.397 - u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU COUT Out 0.035 1.432 - capture_length_zero_cry_3 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU CIN In - 1.432 - u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU COUT Out 0.035 1.467 - capture_length_zero_cry_4 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU CIN In - 1.467 - u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU COUT Out 0.035 1.502 - capture_length_zero_cry_5 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU CIN In - 1.502 - u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU COUT Out 0.035 1.537 - capture_length_zero_cry_6 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU CIN In - 1.537 - u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU COUT Out 0.035 1.572 - capture_length_zero_cry_7 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU CIN In - 1.572 - u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU COUT Out 0.035 1.607 - capture_length_zero_cry_8 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_s_9_0 ALU CIN In - 1.607 - u_ao_mem_ctrl.capture_length_zero_s_9_0 ALU SUM Out 0.470 2.077 - capture_length_zero[9] Net - - 0.535 - 2 u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M LUT2 I1 In - 2.612 - u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M LUT2 F Out 0.570 3.182 - g3_4_0 Net - - 0.535 - 4 u_ao_mem_ctrl.g0_3_1_0 LUT4 I1 In - 3.717 - u_ao_mem_ctrl.g0_3_1_0 LUT4 F Out 0.570 4.287 - g0_3_1_0 Net - - 0.000 - 1 u_ao_mem_ctrl.g0_3_1 MUX2_LUT5 I0 In - 4.287 - u_ao_mem_ctrl.g0_3_1 MUX2_LUT5 O Out 0.105 4.392 - g0_3_1 Net - - 0.000 - 1 u_ao_mem_ctrl.g0_3 MUX2_LUT6 I1 In - 4.392 - u_ao_mem_ctrl.g0_3 MUX2_LUT6 O Out 0.105 4.497 - g0_3 Net - - 0.535 - 1 u_ao_mem_ctrl.mem_addr_inc_en DFFCE CE In - 5.032 - =================================================================================================================== Total path delay (propagation time + setup) of 5.093 is 2.953(58.0%) logic and 2.140(42.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 4.329 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.268 - Propagation time: 4.997 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.729 Number of logic level(s): 13 Starting point: u_ao_mem_ctrl.capture_length[1] / Q Ending point: u_ao_mem_ctrl.mem_addr_inc_en / CE The start point is clocked by ao_top_0|clk_i [rising] on pin CLK The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_length[1] DFFC Q Out 0.243 0.243 - capture_length[1] Net - - 0.535 - 2 u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU I0 In - 0.778 - u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU COUT Out 0.549 1.327 - capture_length_zero_cry_1 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU CIN In - 1.327 - u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU COUT Out 0.035 1.362 - capture_length_zero_cry_2 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU CIN In - 1.362 - u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU COUT Out 0.035 1.397 - capture_length_zero_cry_3 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU CIN In - 1.397 - u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU COUT Out 0.035 1.432 - capture_length_zero_cry_4 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU CIN In - 1.432 - u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU COUT Out 0.035 1.467 - capture_length_zero_cry_5 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU CIN In - 1.467 - u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU COUT Out 0.035 1.502 - capture_length_zero_cry_6 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU CIN In - 1.502 - u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU COUT Out 0.035 1.537 - capture_length_zero_cry_7 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU CIN In - 1.537 - u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU COUT Out 0.035 1.572 - capture_length_zero_cry_8 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_s_9_0 ALU CIN In - 1.572 - u_ao_mem_ctrl.capture_length_zero_s_9_0 ALU SUM Out 0.470 2.042 - capture_length_zero[9] Net - - 0.535 - 2 u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M LUT2 I1 In - 2.577 - u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M LUT2 F Out 0.570 3.147 - g3_4_0 Net - - 0.535 - 4 u_ao_mem_ctrl.g0_3_0_0 LUT4 I1 In - 3.682 - u_ao_mem_ctrl.g0_3_0_0 LUT4 F Out 0.570 4.252 - g0_3_0_0 Net - - 0.000 - 1 u_ao_mem_ctrl.g0_3_0 MUX2_LUT5 I0 In - 4.252 - u_ao_mem_ctrl.g0_3_0 MUX2_LUT5 O Out 0.105 4.357 - g0_3_0 Net - - 0.000 - 1 u_ao_mem_ctrl.g0_3 MUX2_LUT6 I0 In - 4.357 - u_ao_mem_ctrl.g0_3 MUX2_LUT6 O Out 0.105 4.462 - g0_3 Net - - 0.535 - 1 u_ao_mem_ctrl.mem_addr_inc_en DFFCE CE In - 4.997 - =================================================================================================================== Total path delay (propagation time + setup) of 5.058 is 2.918(57.7%) logic and 2.140(42.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: ao_top_0|control[0] ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------ internal_register_select[13] ao_top_0|control[0] DFFCE Q internal_register_select[13] 0.243 -0.968 internal_register_select[9] ao_top_0|control[0] DFFCE Q internal_register_select[9] 0.243 -0.947 internal_register_select[12] ao_top_0|control[0] DFFCE Q internal_register_select[12] 0.243 -0.947 internal_register_select[4] ao_top_0|control[0] DFFCE Q internal_register_select[4] 0.243 -0.926 internal_register_select[7] ao_top_0|control[0] DFFCE Q internal_register_select[7] 0.243 -0.926 internal_register_select[3] ao_top_0|control[0] DFFCE Q internal_register_select[3] 0.243 -0.905 internal_register_select[14] ao_top_0|control[0] DFFCE Q internal_register_select[14] 0.243 -0.860 internal_register_select[10] ao_top_0|control[0] DFFCE Q internal_register_select[10] 0.243 -0.839 internal_register_select[6] ao_top_0|control[0] DFFCE Q internal_register_select[6] 0.243 -0.818 internal_register_select[2] ao_top_0|control[0] DFFCE Q internal_register_select[2] 0.243 -0.813 ============================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------- data_out_shift_reg[14] ao_top_0|control[0] DFFCE D data_out_shift_reg_4[14] 5.422 -0.968 data_out_shift_reg[3] ao_top_0|control[0] DFFCE D data_out_shift_reg_4[3] 5.422 -0.856 data_out_shift_reg[0] ao_top_0|control[0] DFFCE D data_out_shift_reg_4[0] 5.422 -0.769 data_out_shift_reg[1] ao_top_0|control[0] DFFCE D data_out_shift_reg_4[1] 5.422 -0.723 capture_windows_num[0] ao_top_0|control[0] DFFC D capture_windows_nume_0[0] 5.422 -0.699 capture_windows_num[1] ao_top_0|control[0] DFFC D capture_windows_nume_0[1] 5.422 -0.699 capture_windows_num[2] ao_top_0|control[0] DFFC D capture_windows_nume_0[2] 5.422 -0.699 internal_reg_trig_level_max[0] ao_top_0|control[0] DFFC D internal_reg_trig_level_maxe_0[0] 5.422 -0.591 internal_reg_trig_level_max[1] ao_top_0|control[0] DFFC D internal_reg_trig_level_maxe_0[1] 5.422 -0.591 internal_reg_trig_level_max[2] ao_top_0|control[0] DFFC D internal_reg_trig_level_maxe_0[2] 5.422 -0.591 ====================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.483 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.422 - Propagation time: 6.389 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.968 Number of logic level(s): 6 Starting point: internal_register_select[13] / Q Ending point: data_out_shift_reg[14] / D The start point is clocked by ao_top_0|control[0] [rising] on pin CLK The end point is clocked by ao_top_0|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------- internal_register_select[13] DFFCE Q Out 0.243 0.243 - internal_register_select[13] Net - - 0.535 - 1 internal_reg_start_m_12 LUT4 I1 In - 0.778 - internal_reg_start_m_12 LUT4 F Out 0.570 1.348 - match_unit_rd_en_9[0] Net - - 0.535 - 8 data_from_internal_reg100_14 LUT2 I1 In - 1.883 - data_from_internal_reg100_14 LUT2 F Out 0.570 2.453 - internal_reg_start_m_14 Net - - 0.535 - 10 data_out_shift_reg_4_1_a2_5[14] LUT4 I1 In - 2.988 - data_out_shift_reg_4_1_a2_5[14] LUT4 F Out 0.570 3.558 - N_198 Net - - 0.535 - 6 data_out_shift_reg_4_1_1[14] LUT4 I1 In - 4.093 - data_out_shift_reg_4_1_1[14] LUT4 F Out 0.570 4.663 - data_out_shift_reg_4_1_1[14] Net - - 0.401 - 1 data_out_shift_reg_4_1_2[14] LUT4 I2 In - 5.064 - data_out_shift_reg_4_1_2[14] LUT4 F Out 0.462 5.526 - data_out_shift_reg_4_1_2[14] Net - - 0.401 - 1 data_out_shift_reg_4_1[14] LUT3 I2 In - 5.927 - data_out_shift_reg_4_1[14] LUT3 F Out 0.462 6.389 - data_out_shift_reg_4[14] Net - - 0.000 - 1 data_out_shift_reg[14] DFFCE D In - 6.389 - =============================================================================================== Total path delay (propagation time + setup) of 6.450 is 3.508(54.4%) logic and 2.942(45.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 5.483 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.422 - Propagation time: 6.368 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.947 Number of logic level(s): 6 Starting point: internal_register_select[9] / Q Ending point: data_out_shift_reg[14] / D The start point is clocked by ao_top_0|control[0] [rising] on pin CLK The end point is clocked by ao_top_0|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------- internal_register_select[9] DFFCE Q Out 0.243 0.243 - internal_register_select[9] Net - - 0.535 - 1 internal_reg_start_m_11 LUT4 I1 In - 0.778 - internal_reg_start_m_11 LUT4 F Out 0.570 1.348 - match_unit_rd_en_8[0] Net - - 0.535 - 8 data_from_internal_reg100_14 LUT2 I0 In - 1.883 - data_from_internal_reg100_14 LUT2 F Out 0.549 2.432 - internal_reg_start_m_14 Net - - 0.535 - 10 data_out_shift_reg_4_1_a2_5[14] LUT4 I1 In - 2.967 - data_out_shift_reg_4_1_a2_5[14] LUT4 F Out 0.570 3.537 - N_198 Net - - 0.535 - 6 data_out_shift_reg_4_1_1[14] LUT4 I1 In - 4.072 - data_out_shift_reg_4_1_1[14] LUT4 F Out 0.570 4.642 - data_out_shift_reg_4_1_1[14] Net - - 0.401 - 1 data_out_shift_reg_4_1_2[14] LUT4 I2 In - 5.043 - data_out_shift_reg_4_1_2[14] LUT4 F Out 0.462 5.505 - data_out_shift_reg_4_1_2[14] Net - - 0.401 - 1 data_out_shift_reg_4_1[14] LUT3 I2 In - 5.906 - data_out_shift_reg_4_1[14] LUT3 F Out 0.462 6.368 - data_out_shift_reg_4[14] Net - - 0.000 - 1 data_out_shift_reg[14] DFFCE D In - 6.368 - =============================================================================================== Total path delay (propagation time + setup) of 6.429 is 3.487(54.2%) logic and 2.942(45.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 5.483 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.422 - Propagation time: 6.368 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.947 Number of logic level(s): 6 Starting point: internal_register_select[12] / Q Ending point: data_out_shift_reg[14] / D The start point is clocked by ao_top_0|control[0] [rising] on pin CLK The end point is clocked by ao_top_0|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------- internal_register_select[12] DFFCE Q Out 0.243 0.243 - internal_register_select[12] Net - - 0.535 - 1 internal_reg_start_m_12 LUT4 I0 In - 0.778 - internal_reg_start_m_12 LUT4 F Out 0.549 1.327 - match_unit_rd_en_9[0] Net - - 0.535 - 8 data_from_internal_reg100_14 LUT2 I1 In - 1.862 - data_from_internal_reg100_14 LUT2 F Out 0.570 2.432 - internal_reg_start_m_14 Net - - 0.535 - 10 data_out_shift_reg_4_1_a2_5[14] LUT4 I1 In - 2.967 - data_out_shift_reg_4_1_a2_5[14] LUT4 F Out 0.570 3.537 - N_198 Net - - 0.535 - 6 data_out_shift_reg_4_1_1[14] LUT4 I1 In - 4.072 - data_out_shift_reg_4_1_1[14] LUT4 F Out 0.570 4.642 - data_out_shift_reg_4_1_1[14] Net - - 0.401 - 1 data_out_shift_reg_4_1_2[14] LUT4 I2 In - 5.043 - data_out_shift_reg_4_1_2[14] LUT4 F Out 0.462 5.505 - data_out_shift_reg_4_1_2[14] Net - - 0.401 - 1 data_out_shift_reg_4_1[14] LUT3 I2 In - 5.906 - data_out_shift_reg_4_1[14] LUT3 F Out 0.462 6.368 - data_out_shift_reg_4[14] Net - - 0.000 - 1 data_out_shift_reg[14] DFFCE D In - 6.368 - =============================================================================================== Total path delay (propagation time + setup) of 6.429 is 3.487(54.2%) logic and 2.942(45.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 5.483 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.422 - Propagation time: 6.347 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.926 Number of logic level(s): 6 Starting point: internal_register_select[4] / Q Ending point: data_out_shift_reg[14] / D The start point is clocked by ao_top_0|control[0] [rising] on pin CLK The end point is clocked by ao_top_0|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------ internal_register_select[4] DFFCE Q Out 0.243 0.243 - internal_register_select[4] Net - - 0.535 - 7 data_from_internal_reg97_10_0_a2 LUT4 I1 In - 0.778 - data_from_internal_reg97_10_0_a2 LUT4 F Out 0.570 1.348 - data_from_internal_reg97_10 Net - - 0.535 - 3 data_from_internal_reg98_13 LUT4 I0 In - 1.883 - data_from_internal_reg98_13 LUT4 F Out 0.549 2.432 - data_from_internal_reg98_13 Net - - 0.535 - 5 data_out_shift_reg_4_1_a2_5[14] LUT4 I0 In - 2.967 - data_out_shift_reg_4_1_a2_5[14] LUT4 F Out 0.549 3.516 - N_198 Net - - 0.535 - 6 data_out_shift_reg_4_1_1[14] LUT4 I1 In - 4.051 - data_out_shift_reg_4_1_1[14] LUT4 F Out 0.570 4.621 - data_out_shift_reg_4_1_1[14] Net - - 0.401 - 1 data_out_shift_reg_4_1_2[14] LUT4 I2 In - 5.022 - data_out_shift_reg_4_1_2[14] LUT4 F Out 0.462 5.484 - data_out_shift_reg_4_1_2[14] Net - - 0.401 - 1 data_out_shift_reg_4_1[14] LUT3 I2 In - 5.885 - data_out_shift_reg_4_1[14] LUT3 F Out 0.462 6.347 - data_out_shift_reg_4[14] Net - - 0.000 - 1 data_out_shift_reg[14] DFFCE D In - 6.347 - ================================================================================================ Total path delay (propagation time + setup) of 6.408 is 3.466(54.1%) logic and 2.942(45.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 5.483 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.422 - Propagation time: 6.347 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.926 Number of logic level(s): 6 Starting point: internal_register_select[7] / Q Ending point: data_out_shift_reg[14] / D The start point is clocked by ao_top_0|control[0] [rising] on pin CLK The end point is clocked by ao_top_0|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------- internal_register_select[7] DFFCE Q Out 0.243 0.243 - internal_register_select[7] Net - - 0.535 - 1 internal_reg_start_m_11 LUT4 I0 In - 0.778 - internal_reg_start_m_11 LUT4 F Out 0.549 1.327 - match_unit_rd_en_8[0] Net - - 0.535 - 8 data_from_internal_reg100_14 LUT2 I0 In - 1.862 - data_from_internal_reg100_14 LUT2 F Out 0.549 2.411 - internal_reg_start_m_14 Net - - 0.535 - 10 data_out_shift_reg_4_1_a2_5[14] LUT4 I1 In - 2.946 - data_out_shift_reg_4_1_a2_5[14] LUT4 F Out 0.570 3.516 - N_198 Net - - 0.535 - 6 data_out_shift_reg_4_1_1[14] LUT4 I1 In - 4.051 - data_out_shift_reg_4_1_1[14] LUT4 F Out 0.570 4.621 - data_out_shift_reg_4_1_1[14] Net - - 0.401 - 1 data_out_shift_reg_4_1_2[14] LUT4 I2 In - 5.022 - data_out_shift_reg_4_1_2[14] LUT4 F Out 0.462 5.484 - data_out_shift_reg_4_1_2[14] Net - - 0.401 - 1 data_out_shift_reg_4_1[14] LUT3 I2 In - 5.885 - data_out_shift_reg_4_1[14] LUT3 F Out 0.462 6.347 - data_out_shift_reg_4[14] Net - - 0.000 - 1 data_out_shift_reg[14] DFFCE D In - 6.347 - =============================================================================================== Total path delay (propagation time + setup) of 6.408 is 3.466(54.1%) logic and 2.942(45.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 System INV O capture_end 0.000 2.187 address_counter_cry_0_RNO[0] System INV O address_counter 0.000 3.567 ============================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------- capture_window_sel[2] System DFFC D capture_window_sel_3[2] 4.268 2.187 capture_window_sel[3] System DFFC D capture_window_sel_3[3] 4.268 2.187 capture_window_sel[1] System DFFC D capture_window_sel_3[1] 4.268 2.412 capture_window_sel[0] System DFFC D capture_window_sel_3[0] 4.268 3.184 internal_reg_start_dly[0] System DFFC D internal_reg_start_dly_2[0] 4.268 3.184 address_counter[9] System DFFCE D address_counter_s[9] 5.422 3.567 address_counter[8] System DFFCE D address_counter_s[8] 5.422 3.602 address_counter[7] System DFFCE D address_counter_s[7] 5.422 3.637 address_counter[6] System DFFCE D address_counter_s[6] 5.422 3.672 address_counter[5] System DFFCE D address_counter_s[5] 5.422 3.707 ================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 4.329 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.268 - Propagation time: 2.081 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 2.187 Number of logic level(s): 2 Starting point: u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 / O Ending point: capture_window_sel[2] / D The start point is clocked by System [rising] The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 INV O Out 0.000 0.000 - capture_end Net - - 0.535 - 6 un1_capture_window_sel_ac0_1 LUT4 I0 In - 0.535 - un1_capture_window_sel_ac0_1 LUT4 F Out 0.549 1.084 - un1_capture_window_sel_c2 Net - - 0.535 - 2 capture_window_sel_3[2] LUT3 I2 In - 1.619 - capture_window_sel_3[2] LUT3 F Out 0.462 2.081 - capture_window_sel_3[2] Net - - 0.000 - 1 capture_window_sel[2] DFFC D In - 2.081 - =================================================================================================== Total path delay (propagation time + setup) of 2.142 is 1.072(50.0%) logic and 1.070(50.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied Finished final timing analysis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 248MB peak: 251MB) Finished timing report (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 248MB peak: 251MB) --------------------------------------- Resource Usage Report for ao_top_0 Mapping to part: gw2a_18pbga256-8 Cell usage: ALU 69 uses DFF 19 uses DFFC 49 uses DFFCE 191 uses DFFNP 2 uses DFFP 5 uses DFFPE 32 uses GSR 1 use INV 2 uses MUX2_LUT5 5 uses MUX2_LUT6 2 uses SDPX9 2 uses LUT2 53 uses LUT3 105 uses LUT4 238 uses I/O ports: 31 I/O primitives: 31 IBUF 29 uses OBUF 2 uses I/O Register bits: 0 Register bits not including I/Os: 298 of 15552 (1%) RAM/ROM usage summary Block Rams : 2 of 46 (4%) Total load per clock: ao_top_0|clk_i: 1 ao_top_0|control[0]: 239 @S |Mapping Summary: Total LUTs: 396 (1%) Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 76MB peak: 251MB) Process took 0h:00m:09s realtime, 0h:00m:08s cputime # Tue Sep 29 16:33:44 2020 ###########################################################]