@W: CS263 :"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/IIR_Filter/data/iir_top_wrap.v":64:9:64:15|Port-width mismatch for port coeff_a. The port definition is 18 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
@W: CS263 :"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/IIR_Filter/data/iir_top_wrap.v":65:9:65:15|Port-width mismatch for port coeff_b. The port definition is 18 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
@W: CL246 :"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/IIR_Filter/data/iir_top_wrap.v":44:29:44:35|Input port bits 31 to 18 of coeff_a[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/IIR_Filter/data/iir_top_wrap.v":45:29:45:35|Input port bits 31 to 18 of coeff_b[31:0] are unused. Assign logic for all port bits or change the input port size.

