@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
@N: CG364 :"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/IIR_Filter/data/iir_top_wrap.v":13:19:13:19|Synthesizing module IIR_Filter_Top in library work.
@N|Running in 64-bit mode
@N: NF107 :"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/IIR_Filter/data/iir_top_wrap.v":13:19:13:19|Selected library: work cell: IIR_Filter_Top view verilog as top level
@N: NF107 :"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/IIR_Filter/data/iir_top_wrap.v":13:19:13:19|Selected library: work cell: IIR_Filter_Top view verilog as top level

