Timing Messages

Report Title	Timing Analysis Report
Design File	E:\work\work\Confidential_IP\code\TDC\Gowin_TDC_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\work\work\Confidential_IP\code\TDC\Gowin_TDC_RefDesign\project\src\fpga_project.cst
Timing Constraint File	---
Tool Version	V1.9.11.02 (64-bit)
Part Number	GW1N-LV9QN88C6/I5
Device	GW1N-9
Device Version	C
Created Time	Mon Jul 14 10:07:12 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C C6/I5
Hold Delay Model	Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed	1196
Numbers of Endpoints Analyzed	1162
Numbers of Falling Endpoints	4
Numbers of Setup Violated Endpoints	16
Numbers of Hold Violated Endpoints	1

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clk	Base	20.000	50.000	0.000	10.000			clk_ibuf/I
2	tck_pad_i	Base	50.000	20.000	0.000	25.000			tck_pad_i_ibuf/I
3	Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk	Generated	2.500	400.000	0.000	1.250	clk_ibuf/I	clk	Gowin_PLL/rpll_inst/CLKOUT
4	Gowin_PLL/rpll_inst/CLKOUTP.default_gen_clk	Generated	2.500	400.000	0.000	1.250	clk_ibuf/I	clk	Gowin_PLL/rpll_inst/CLKOUTP
5	Gowin_PLL/rpll_inst/CLKOUTD.default_gen_clk	Generated	5.000	200.000	0.000	2.500	clk_ibuf/I	clk	Gowin_PLL/rpll_inst/CLKOUTD
6	Gowin_PLL/rpll_inst/CLKOUTD3.default_gen_clk	Generated	7.500	133.333	0.000	3.750	clk_ibuf/I	clk	Gowin_PLL/rpll_inst/CLKOUTD3
7	u_CLKDIV/CLKOUT.default_gen_clk	Generated	10.000	100.000	0.000	5.000	Gowin_PLL/rpll_inst/CLKOUT	Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk	u_CLKDIV/CLKOUT

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	tck_pad_i	20.000(MHz)	77.414(MHz)	1	TOP
2	u_CLKDIV/CLKOUT.default_gen_clk	100.000(MHz)	104.822(MHz)	6	TOP

No timing paths to get frequency of clk!

No timing paths to get frequency of Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk!

No timing paths to get frequency of Gowin_PLL/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of Gowin_PLL/rpll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of Gowin_PLL/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0
Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk	Setup	0.000	0
Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk	Hold	0.000	0
Gowin_PLL/rpll_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
Gowin_PLL/rpll_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
Gowin_PLL/rpll_inst/CLKOUTD.default_gen_clk	Setup	0.000	0
Gowin_PLL/rpll_inst/CLKOUTD.default_gen_clk	Hold	0.000	0
Gowin_PLL/rpll_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
Gowin_PLL/rpll_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0
u_CLKDIV/CLKOUT.default_gen_clk	Setup	0.000	0
u_CLKDIV/CLKOUT.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-2.662	gw_gao_gvio_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q	gw_gao_gvio_inst_0/u_la0_top/trigger_seq_start_s1/CE	tck_pad_i:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	3.859	8.730
2	-1.418	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE	tck_pad_i:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	3.859	7.486
3	-1.268	gw_gao_gvio_inst_0/u_la0_top/capture_windows_num_0_s0/Q	gw_gao_gvio_inst_0/u_la0_top/start_reg_s0/D	tck_pad_i:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	3.859	6.980
4	-1.155	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D	tck_pad_i:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	3.859	6.866
5	-1.140	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D	tck_pad_i:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	3.859	6.852
6	-1.140	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D	tck_pad_i:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	3.859	6.852
7	-1.136	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/D	tck_pad_i:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	3.859	6.847
8	-0.757	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D	tck_pad_i:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	3.859	6.468
9	-0.757	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D	tck_pad_i:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	3.859	6.468
10	-0.757	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D	tck_pad_i:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	3.859	6.468
11	-0.716	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D	tck_pad_i:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	3.859	6.427
12	-0.431	gw_gao_gvio_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q	gw_gao_gvio_inst_0/u_la0_top/triger_s0/D	tck_pad_i:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	3.859	6.142
13	-0.365	gw_gao_gvio_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_2_s1/D	tck_pad_i:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	3.859	6.077
14	-0.116	gw_gao_gvio_inst_0/u_la0_top/capture_windows_num_0_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0/D	tck_pad_i:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	3.859	5.827
15	-0.080	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_rem_0_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE	tck_pad_i:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	3.859	6.148
16	0.272	gw_gao_gvio_inst_0/u_la0_top/capture_windows_num_1_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0/D	tck_pad_i:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	3.859	5.439
17	0.316	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/internal_reg_match_m1_en_0_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/D	tck_pad_i:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	3.859	5.395
18	0.460	dut/u_tdc/q_d_7_s0/Q	dut/u_tdc/count_tmp_6_s1/D	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	0.000	9.140
19	0.502	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_rem_0_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D	tck_pad_i:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	3.859	5.209
20	0.527	dut/u_tdc/q_d_7_s0/Q	dut/u_tdc/count_tmp_9_s1/D	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	0.000	9.073
21	0.530	dut/u_tdc/q_d_7_s0/Q	dut/u_tdc/count_tmp_7_s1/D	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	0.000	9.070
22	0.530	dut/u_tdc/q_d_7_s0/Q	dut/u_tdc/count_tmp_8_s1/D	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	0.000	9.070
23	0.542	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_rem_0_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE	tck_pad_i:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	3.859	5.526
24	0.739	gw_gao_gvio_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_1_s1/D	tck_pad_i:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	3.859	4.972
25	0.739	gw_gao_gvio_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1/D	tck_pad_i:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	3.859	4.972

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-1.592	gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_7_s1/Q	gw_gao_gvio_inst_0/u_la0_top/capture_end_tck_0_s0/D	u_CLKDIV/CLKOUT.default_gen_clk:[R]	tck_pad_i:[R]	0.000	-2.689	1.127
2	0.708	gw_gao_gvio_inst_0/u_la0_top/bit_count_0_s1/Q	gw_gao_gvio_inst_0/u_la0_top/bit_count_0_s1/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.708
3	0.708	gw_gao_gvio_inst_0/u_la0_top/bit_count_3_s1/Q	gw_gao_gvio_inst_0/u_la0_top/bit_count_3_s1/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.708
4	0.708	gw_gao_gvio_inst_0/u_la0_top/word_count_7_s0/Q	gw_gao_gvio_inst_0/u_la0_top/word_count_7_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.708
5	0.708	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_5_s1/Q	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_5_s1/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.708
6	0.708	gw_gao_gvio_inst_0/u_gvio0_top/addr_all_5_s1/Q	gw_gao_gvio_inst_0/u_gvio0_top/addr_all_5_s1/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.708
7	0.708	gw_gao_gvio_inst_0/u_gvio0_top/word_count_3_s0/Q	gw_gao_gvio_inst_0/u_gvio0_top/word_count_3_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.708
8	0.708	gw_gao_gvio_inst_0/u_gvio0_top/word_count_11_s0/Q	gw_gao_gvio_inst_0/u_gvio0_top/word_count_11_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.708
9	0.708	gw_gao_gvio_inst_0/u_gvio0_top/word_count_12_s0/Q	gw_gao_gvio_inst_0/u_gvio0_top/word_count_12_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.708
10	0.708	gw_gao_gvio_inst_0/u_gvio0_top/word_count_15_s0/Q	gw_gao_gvio_inst_0/u_gvio0_top/word_count_15_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.708
11	0.708	gw_gao_gvio_inst_0/u_gvio_icon_top/tdo_select_s5/Q	gw_gao_gvio_inst_0/u_gvio_icon_top/tdo_select_s5/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.708
12	0.708	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/D	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.708
13	0.709	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/D	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.709
14	0.709	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/D	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.709
15	0.709	gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1/Q	gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1/D	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.709
16	0.709	gw_gao_gvio_inst_0/u_la0_top/word_count_1_s0/Q	gw_gao_gvio_inst_0/u_la0_top/word_count_1_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.709
17	0.709	gw_gao_gvio_inst_0/u_la0_top/word_count_2_s0/Q	gw_gao_gvio_inst_0/u_la0_top/word_count_2_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.709
18	0.709	gw_gao_gvio_inst_0/u_la0_top/word_count_5_s0/Q	gw_gao_gvio_inst_0/u_la0_top/word_count_5_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.709
19	0.709	gw_gao_gvio_inst_0/u_la0_top/address_counter_4_s0/Q	gw_gao_gvio_inst_0/u_la0_top/address_counter_4_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.709
20	0.709	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_2_s1/Q	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_2_s1/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.709
21	0.709	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_6_s1/Q	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_6_s1/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.709
22	0.709	gw_gao_gvio_inst_0/u_gvio0_top/addr_all_2_s1/Q	gw_gao_gvio_inst_0/u_gvio0_top/addr_all_2_s1/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.709
23	0.709	gw_gao_gvio_inst_0/u_gvio0_top/word_count_4_s0/Q	gw_gao_gvio_inst_0/u_gvio0_top/word_count_4_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.709
24	0.709	gw_gao_gvio_inst_0/u_gvio0_top/word_count_8_s0/Q	gw_gao_gvio_inst_0/u_gvio0_top/word_count_8_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.709
25	0.709	gw_gao_gvio_inst_0/u_gvio0_top/word_count_9_s0/Q	gw_gao_gvio_inst_0/u_gvio0_top/word_count_9_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.709

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-1.722	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/u_IDES8/RESET	u_CLKDIV/CLKOUT.default_gen_clk:[R]	Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk:[F]	1.250	-1.943	4.840
2	-0.479	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/u_IDES8/RESET	u_CLKDIV/CLKOUT.default_gen_clk:[R]	Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk:[R]	2.500	-1.937	4.840
3	0.714	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[F]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	5.000	0.015	4.227
4	0.714	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[F]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	5.000	0.015	4.227
5	0.714	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[F]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	5.000	0.015	4.227
6	0.873	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[F]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	5.000	0.015	4.069
7	1.693	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	u_CLKDIV/CLKOUT.default_gen_clk:[F]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	5.000	0.015	3.249
8	1.693	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[F]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	5.000	0.015	3.249
9	1.693	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[F]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	5.000	0.015	3.249
10	1.693	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[F]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	5.000	0.015	3.249
11	1.693	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[F]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	5.000	0.015	3.249
12	1.694	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[F]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	5.000	0.015	3.248
13	2.169	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[F]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	5.000	0.015	2.773
14	2.169	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[F]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	5.000	0.015	2.773
15	2.169	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[F]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	5.000	0.015	2.773
16	2.169	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[F]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	5.000	0.015	2.773
17	2.169	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[F]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	5.000	0.015	2.773
18	2.169	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[F]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	5.000	0.015	2.773
19	2.178	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[F]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	5.000	0.015	2.763
20	2.178	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[F]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	5.000	0.015	2.763
21	2.178	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[F]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	5.000	0.015	2.763
22	2.182	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[F]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	5.000	0.015	2.760
23	2.182	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_gvio_inst_0/u_la0_top/capture_end_dly_s0/PRESET	u_CLKDIV/CLKOUT.default_gen_clk:[F]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	5.000	0.015	2.760
24	2.349	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[F]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	5.000	0.015	2.592
25	5.115	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/u_IDES8/RESET	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	10.000	0.000	4.840

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.113	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/u_IDES8/RESET	u_CLKDIV/CLKOUT.default_gen_clk:[R]	Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.965	3.121
2	2.357	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/u_IDES8/RESET	u_CLKDIV/CLKOUT.default_gen_clk:[R]	Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk:[F]	-1.250	-1.971	3.121
3	3.109	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/u_IDES8/RESET	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.121
4	3.109	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/count_tmp_0_s1/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.121
5	3.109	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/count_tmp_1_s1/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.121
6	3.109	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/count_tmp_2_s1/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.121
7	3.109	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/count_tmp_3_s1/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.121
8	3.109	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/count_tmp_4_s1/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.121
9	3.109	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/count_tmp_5_s1/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.121
10	3.109	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/count_tmp_6_s1/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.121
11	3.109	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/count_tmp_7_s1/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.121
12	3.109	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/count_tmp_8_s1/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.121
13	3.109	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/count_tmp_9_s1/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.121
14	3.109	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/start_d1_s0/PRESET	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.121
15	3.109	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/start_d0_s0/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.121
16	3.109	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/c_state_0_s0/PRESET	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.121
17	3.109	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/c_state_1_s0/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.121
18	3.109	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/c_state_2_s0/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.121
19	3.109	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/c_state_3_s0/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.121
20	3.109	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/q_d_0_s0/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.121
21	3.109	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/q_d_1_s0/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.121
22	3.109	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/q_d_2_s0/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.121
23	3.109	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/q_d_3_s0/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.121
24	3.109	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/q_d_4_s0/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.121
25	3.109	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q	dut/u_tdc/q_d_5_s0/CLEAR	u_CLKDIV/CLKOUT.default_gen_clk:[R]	u_CLKDIV/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.121

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.676	4.926	1.250	Low Pulse Width	u_CLKDIV/CLKOUT.default_gen_clk	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg1_0_s0
2	3.676	4.926	1.250	Low Pulse Width	u_CLKDIV/CLKOUT.default_gen_clk	gw_gao_gvio_inst_0/u_gvio0_top/probe_out1_reg1_0_s0
3	3.676	4.926	1.250	Low Pulse Width	u_CLKDIV/CLKOUT.default_gen_clk	gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_syn_1_s0
4	3.676	4.926	1.250	Low Pulse Width	u_CLKDIV/CLKOUT.default_gen_clk	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1
5	3.676	4.926	1.250	Low Pulse Width	u_CLKDIV/CLKOUT.default_gen_clk	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_6_s0
6	3.676	4.926	1.250	Low Pulse Width	u_CLKDIV/CLKOUT.default_gen_clk	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
7	3.676	4.926	1.250	Low Pulse Width	u_CLKDIV/CLKOUT.default_gen_clk	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
8	3.676	4.926	1.250	Low Pulse Width	u_CLKDIV/CLKOUT.default_gen_clk	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_7_s0
9	3.676	4.926	1.250	Low Pulse Width	u_CLKDIV/CLKOUT.default_gen_clk	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
10	3.676	4.926	1.250	Low Pulse Width	u_CLKDIV/CLKOUT.default_gen_clk	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-2.662
Data Arrival Time	13.161
Data Required Time	10.499
From	gw_gao_gvio_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To	gw_gao_gvio_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
2.088	2.088	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
2.088	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
3.070	0.982	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
4.431	1.361	tNET	RR	1	R18C10[0][A]	gw_gao_gvio_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
4.889	0.458	tC2Q	RF	2	R18C10[0][A]	gw_gao_gvio_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
6.197	1.308	tNET	FF	2	R16C8[0][B]	gw_gao_gvio_inst_0/u_la0_top/n1274_s0/I1
7.242	1.045	tINS	FF	1	R16C8[0][B]	gw_gao_gvio_inst_0/u_la0_top/n1274_s0/COUT
7.242	0.000	tNET	FF	2	R16C8[1][A]	gw_gao_gvio_inst_0/u_la0_top/n1275_s0/CIN
7.299	0.057	tINS	FF	1	R16C8[1][A]	gw_gao_gvio_inst_0/u_la0_top/n1275_s0/COUT
7.299	0.000	tNET	FF	2	R16C8[1][B]	gw_gao_gvio_inst_0/u_la0_top/n1276_s0/CIN
7.356	0.057	tINS	FF	1	R16C8[1][B]	gw_gao_gvio_inst_0/u_la0_top/n1276_s0/COUT
7.356	0.000	tNET	FF	2	R16C8[2][A]	gw_gao_gvio_inst_0/u_la0_top/n1277_s0/CIN
7.413	0.057	tINS	FF	6	R16C8[2][A]	gw_gao_gvio_inst_0/u_la0_top/n1277_s0/COUT
9.474	2.060	tNET	FF	1	R18C13[1][B]	gw_gao_gvio_inst_0/u_la0_top/n1318_s1/I0
10.573	1.099	tINS	FF	1	R18C13[1][B]	gw_gao_gvio_inst_0/u_la0_top/n1318_s1/F
10.578	0.005	tNET	FF	1	R18C13[1][A]	gw_gao_gvio_inst_0/u_la0_top/trigger_seq_start_s3/I3
11.639	1.061	tINS	FR	1	R18C13[1][A]	gw_gao_gvio_inst_0/u_la0_top/trigger_seq_start_s3/F
13.161	1.522	tNET	RR	1	R18C13[2][A]	gw_gao_gvio_inst_0/u_la0_top/trigger_seq_start_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R18C13[2][A]	gw_gao_gvio_inst_0/u_la0_top/trigger_seq_start_s1/CLK
10.542	-0.030	tUnc				gw_gao_gvio_inst_0/u_la0_top/trigger_seq_start_s1
10.499	-0.043	tSu		1	R18C13[2][A]	gw_gao_gvio_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	-3.859
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 3.070, 69.285%; route: 1.361, 30.715%
Arrival Data Path Delay	cell: 3.376, 38.671%; route: 4.896, 56.079%; tC2Q: 0.458, 5.250%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path2

Path Summary:

Slack	-1.418
Data Arrival Time	11.916
Data Required Time	10.499
From	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
2.088	2.088	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
2.088	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
3.070	0.982	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
4.431	1.361	tNET	RR	1	R20C10[0][B]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/CLK
4.889	0.458	tC2Q	RF	2	R20C10[0][B]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/Q
5.696	0.807	tNET	FF	1	R21C11[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s8/I1
6.728	1.032	tINS	FF	1	R21C11[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s8/F
7.703	0.975	tNET	FF	1	R20C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/I0
8.525	0.822	tINS	FF	1	R20C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/F
8.530	0.005	tNET	FF	1	R20C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/I1
9.352	0.822	tINS	FF	9	R20C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/F
9.369	0.016	tNET	FF	1	R20C13[1][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
10.395	1.026	tINS	FR	1	R20C13[1][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
11.916	1.522	tNET	RR	1	R20C13[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R20C13[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
10.542	-0.030	tUnc				gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
10.499	-0.043	tSu		1	R20C13[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-3.859
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 3.070, 69.285%; route: 1.361, 30.715%
Arrival Data Path Delay	cell: 3.702, 49.455%; route: 3.325, 44.422%; tC2Q: 0.458, 6.123%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path3

Path Summary:

Slack	-1.268
Data Arrival Time	11.410
Data Required Time	10.142
From	gw_gao_gvio_inst_0/u_la0_top/capture_windows_num_0_s0
To	gw_gao_gvio_inst_0/u_la0_top/start_reg_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
2.088	2.088	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
2.088	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
3.070	0.982	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
4.431	1.361	tNET	RR	1	R18C10[1][A]	gw_gao_gvio_inst_0/u_la0_top/capture_windows_num_0_s0/CLK
4.889	0.458	tC2Q	RF	3	R18C10[1][A]	gw_gao_gvio_inst_0/u_la0_top/capture_windows_num_0_s0/Q
8.136	3.246	tNET	FF	2	R17C13[0][A]	gw_gao_gvio_inst_0/u_la0_top/n1248_s16/CIN
8.193	0.057	tINS	FF	1	R17C13[0][A]	gw_gao_gvio_inst_0/u_la0_top/n1248_s16/COUT
8.193	0.000	tNET	FF	2	R17C13[0][B]	gw_gao_gvio_inst_0/u_la0_top/n1248_s17/CIN
8.250	0.057	tINS	FF	1	R17C13[0][B]	gw_gao_gvio_inst_0/u_la0_top/n1248_s17/COUT
8.250	0.000	tNET	FF	2	R17C13[1][A]	gw_gao_gvio_inst_0/u_la0_top/n1248_s18/CIN
8.307	0.057	tINS	FF	1	R17C13[1][A]	gw_gao_gvio_inst_0/u_la0_top/n1248_s18/COUT
8.307	0.000	tNET	FF	2	R17C13[1][B]	gw_gao_gvio_inst_0/u_la0_top/n1248_s19/CIN
8.364	0.057	tINS	FF	1	R17C13[1][B]	gw_gao_gvio_inst_0/u_la0_top/n1248_s19/COUT
8.364	0.000	tNET	FF	2	R17C13[2][A]	gw_gao_gvio_inst_0/u_la0_top/n1248_s20/CIN
8.421	0.057	tINS	FF	1	R17C13[2][A]	gw_gao_gvio_inst_0/u_la0_top/n1248_s20/COUT
8.421	0.000	tNET	FF	2	R17C13[2][B]	gw_gao_gvio_inst_0/u_la0_top/n1248_s21/CIN
8.478	0.057	tINS	FF	1	R17C13[2][B]	gw_gao_gvio_inst_0/u_la0_top/n1248_s21/COUT
8.478	0.000	tNET	FF	2	R17C14[0][A]	gw_gao_gvio_inst_0/u_la0_top/n1248_s22/CIN
8.535	0.057	tINS	FF	2	R17C14[0][A]	gw_gao_gvio_inst_0/u_la0_top/n1248_s22/COUT
9.109	0.574	tNET	FF	1	R17C14[2][A]	gw_gao_gvio_inst_0/u_la0_top/start_reg1_s1/I1
10.170	1.061	tINS	FR	1	R17C14[2][A]	gw_gao_gvio_inst_0/u_la0_top/start_reg1_s1/F
10.588	0.419	tNET	RR	1	R18C14[0][B]	gw_gao_gvio_inst_0/u_la0_top/start_reg1_s0/I1
11.410	0.822	tINS	RF	1	R18C14[0][B]	gw_gao_gvio_inst_0/u_la0_top/start_reg1_s0/F
11.410	0.000	tNET	FF	1	R18C14[0][B]	gw_gao_gvio_inst_0/u_la0_top/start_reg_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R18C14[0][B]	gw_gao_gvio_inst_0/u_la0_top/start_reg_s0/CLK
10.542	-0.030	tUnc				gw_gao_gvio_inst_0/u_la0_top/start_reg_s0
10.142	-0.400	tSu		1	R18C14[0][B]	gw_gao_gvio_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	-3.859
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 3.070, 69.285%; route: 1.361, 30.715%
Arrival Data Path Delay	cell: 2.282, 32.695%; route: 4.239, 60.738%; tC2Q: 0.458, 6.567%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path4

Path Summary:

Slack	-1.155
Data Arrival Time	11.297
Data Required Time	10.142
From	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
2.088	2.088	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
2.088	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
3.070	0.982	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
4.431	1.361	tNET	RR	1	R20C10[0][B]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/CLK
4.889	0.458	tC2Q	RF	2	R20C10[0][B]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/Q
5.696	0.807	tNET	FF	1	R21C11[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s8/I1
6.728	1.032	tINS	FF	1	R21C11[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s8/F
7.703	0.975	tNET	FF	1	R20C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/I0
8.525	0.822	tINS	FF	1	R20C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/F
8.530	0.005	tNET	FF	1	R20C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/I1
9.352	0.822	tINS	FF	9	R20C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/F
10.198	0.845	tNET	FF	1	R20C15[1][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n241_s1/I2
11.297	1.099	tINS	FF	1	R20C15[1][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n241_s1/F
11.297	0.000	tNET	FF	1	R20C15[1][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R20C15[1][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
10.542	-0.030	tUnc				gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
10.142	-0.400	tSu		1	R20C15[1][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-3.859
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 3.070, 69.285%; route: 1.361, 30.715%
Arrival Data Path Delay	cell: 3.775, 54.981%; route: 2.633, 38.343%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path5

Path Summary:

Slack	-1.140
Data Arrival Time	11.282
Data Required Time	10.142
From	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
2.088	2.088	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
2.088	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
3.070	0.982	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
4.431	1.361	tNET	RR	1	R20C10[0][B]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/CLK
4.889	0.458	tC2Q	RF	2	R20C10[0][B]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/Q
5.696	0.807	tNET	FF	1	R21C11[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s8/I1
6.728	1.032	tINS	FF	1	R21C11[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s8/F
7.703	0.975	tNET	FF	1	R20C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/I0
8.525	0.822	tINS	FF	1	R20C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/F
8.530	0.005	tNET	FF	1	R20C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/I1
9.352	0.822	tINS	FF	9	R20C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/F
10.183	0.831	tNET	FF	1	R21C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n240_s1/I3
11.282	1.099	tINS	FF	1	R21C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n240_s1/F
11.282	0.000	tNET	FF	1	R21C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R21C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
10.542	-0.030	tUnc				gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
10.142	-0.400	tSu		1	R21C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-3.859
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 3.070, 69.285%; route: 1.361, 30.715%
Arrival Data Path Delay	cell: 3.775, 55.096%; route: 2.618, 38.215%; tC2Q: 0.458, 6.689%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path6

Path Summary:

Slack	-1.140
Data Arrival Time	11.282
Data Required Time	10.142
From	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
2.088	2.088	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
2.088	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
3.070	0.982	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
4.431	1.361	tNET	RR	1	R20C10[0][B]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/CLK
4.889	0.458	tC2Q	RF	2	R20C10[0][B]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/Q
5.696	0.807	tNET	FF	1	R21C11[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s8/I1
6.728	1.032	tINS	FF	1	R21C11[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s8/F
7.703	0.975	tNET	FF	1	R20C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/I0
8.525	0.822	tINS	FF	1	R20C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/F
8.530	0.005	tNET	FF	1	R20C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/I1
9.352	0.822	tINS	FF	9	R20C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/F
10.183	0.831	tNET	FF	1	R21C15[0][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n239_s1/I2
11.282	1.099	tINS	FF	1	R21C15[0][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n239_s1/F
11.282	0.000	tNET	FF	1	R21C15[0][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R21C15[0][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
10.542	-0.030	tUnc				gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
10.142	-0.400	tSu		1	R21C15[0][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-3.859
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 3.070, 69.285%; route: 1.361, 30.715%
Arrival Data Path Delay	cell: 3.775, 55.096%; route: 2.618, 38.215%; tC2Q: 0.458, 6.689%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path7

Path Summary:

Slack	-1.136
Data Arrival Time	11.278
Data Required Time	10.142
From	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5
Launch Clk	tck_pad_i:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
2.088	2.088	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
2.088	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
3.070	0.982	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
4.431	1.361	tNET	RR	1	R20C10[0][B]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/CLK
4.889	0.458	tC2Q	RF	2	R20C10[0][B]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/Q
5.696	0.807	tNET	FF	1	R21C11[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s8/I1
6.728	1.032	tINS	FF	1	R21C11[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s8/F
7.703	0.975	tNET	FF	1	R20C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/I0
8.525	0.822	tINS	FF	1	R20C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/F
8.530	0.005	tNET	FF	1	R20C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/I1
9.352	0.822	tINS	FF	9	R20C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/F
10.179	0.827	tNET	FF	1	R21C14[2][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n244_s3/I2
11.278	1.099	tINS	FF	1	R21C14[2][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n244_s3/F
11.278	0.000	tNET	FF	1	R21C14[2][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R21C14[2][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK
10.542	-0.030	tUnc				gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5
10.142	-0.400	tSu		1	R21C14[2][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5

Path Statistics:

Clock Skew	-3.859
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 3.070, 69.285%; route: 1.361, 30.715%
Arrival Data Path Delay	cell: 3.775, 55.133%; route: 2.614, 38.173%; tC2Q: 0.458, 6.694%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path8

Path Summary:

Slack	-0.757
Data Arrival Time	10.899
Data Required Time	10.142
From	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
2.088	2.088	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
2.088	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
3.070	0.982	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
4.431	1.361	tNET	RR	1	R20C10[0][B]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/CLK
4.889	0.458	tC2Q	RF	2	R20C10[0][B]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/Q
5.696	0.807	tNET	FF	1	R21C11[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s8/I1
6.728	1.032	tINS	FF	1	R21C11[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s8/F
7.703	0.975	tNET	FF	1	R20C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/I0
8.525	0.822	tINS	FF	1	R20C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/F
8.530	0.005	tNET	FF	1	R20C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/I1
9.352	0.822	tINS	FF	9	R20C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/F
9.867	0.515	tNET	FF	1	R20C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n242_s1/I3
10.899	1.032	tINS	FF	1	R20C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n242_s1/F
10.899	0.000	tNET	FF	1	R20C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R20C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
10.542	-0.030	tUnc				gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
10.142	-0.400	tSu		1	R20C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-3.859
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 3.070, 69.285%; route: 1.361, 30.715%
Arrival Data Path Delay	cell: 3.708, 57.327%; route: 2.302, 35.587%; tC2Q: 0.458, 7.086%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path9

Path Summary:

Slack	-0.757
Data Arrival Time	10.899
Data Required Time	10.142
From	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
2.088	2.088	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
2.088	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
3.070	0.982	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
4.431	1.361	tNET	RR	1	R20C10[0][B]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/CLK
4.889	0.458	tC2Q	RF	2	R20C10[0][B]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/Q
5.696	0.807	tNET	FF	1	R21C11[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s8/I1
6.728	1.032	tINS	FF	1	R21C11[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s8/F
7.703	0.975	tNET	FF	1	R20C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/I0
8.525	0.822	tINS	FF	1	R20C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/F
8.530	0.005	tNET	FF	1	R20C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/I1
9.352	0.822	tINS	FF	9	R20C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/F
9.867	0.515	tNET	FF	1	R20C15[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n238_s1/I2
10.899	1.032	tINS	FF	1	R20C15[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n238_s1/F
10.899	0.000	tNET	FF	1	R20C15[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R20C15[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
10.542	-0.030	tUnc				gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
10.142	-0.400	tSu		1	R20C15[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-3.859
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 3.070, 69.285%; route: 1.361, 30.715%
Arrival Data Path Delay	cell: 3.708, 57.327%; route: 2.302, 35.587%; tC2Q: 0.458, 7.086%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path10

Path Summary:

Slack	-0.757
Data Arrival Time	10.899
Data Required Time	10.142
From	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
2.088	2.088	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
2.088	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
3.070	0.982	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
4.431	1.361	tNET	RR	1	R20C10[0][B]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/CLK
4.889	0.458	tC2Q	RF	2	R20C10[0][B]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/Q
5.696	0.807	tNET	FF	1	R21C11[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s8/I1
6.728	1.032	tINS	FF	1	R21C11[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s8/F
7.703	0.975	tNET	FF	1	R20C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/I0
8.525	0.822	tINS	FF	1	R20C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/F
8.530	0.005	tNET	FF	1	R20C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/I1
9.352	0.822	tINS	FF	9	R20C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/F
9.867	0.515	tNET	FF	1	R20C15[0][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s2/I3
10.899	1.032	tINS	FF	1	R20C15[0][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s2/F
10.899	0.000	tNET	FF	1	R20C15[0][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R20C15[0][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
10.542	-0.030	tUnc				gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
10.142	-0.400	tSu		1	R20C15[0][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	-3.859
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 3.070, 69.285%; route: 1.361, 30.715%
Arrival Data Path Delay	cell: 3.708, 57.327%; route: 2.302, 35.587%; tC2Q: 0.458, 7.086%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path11

Path Summary:

Slack	-0.716
Data Arrival Time	10.858
Data Required Time	10.142
From	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
2.088	2.088	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
2.088	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
3.070	0.982	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
4.431	1.361	tNET	RR	1	R20C10[0][B]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/CLK
4.889	0.458	tC2Q	RF	2	R20C10[0][B]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_max_9_s0/Q
5.696	0.807	tNET	FF	1	R21C11[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s8/I1
6.728	1.032	tINS	FF	1	R21C11[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s8/F
7.703	0.975	tNET	FF	1	R20C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/I0
8.525	0.822	tINS	FF	1	R20C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/F
8.530	0.005	tNET	FF	1	R20C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/I1
9.332	0.802	tINS	FR	9	R20C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/F
9.759	0.427	tNET	RR	1	R21C13[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n243_s1/I2
10.858	1.099	tINS	RF	1	R21C13[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n243_s1/F
10.858	0.000	tNET	FF	1	R21C13[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R21C13[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
10.542	-0.030	tUnc				gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
10.142	-0.400	tSu		1	R21C13[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-3.859
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 3.070, 69.285%; route: 1.361, 30.715%
Arrival Data Path Delay	cell: 3.755, 58.424%; route: 2.214, 34.445%; tC2Q: 0.458, 7.131%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path12

Path Summary:

Slack	-0.431
Data Arrival Time	10.573
Data Required Time	10.142
From	gw_gao_gvio_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To	gw_gao_gvio_inst_0/u_la0_top/triger_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
2.088	2.088	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
2.088	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
3.070	0.982	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
4.431	1.361	tNET	RR	1	R18C10[0][A]	gw_gao_gvio_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
4.889	0.458	tC2Q	RF	2	R18C10[0][A]	gw_gao_gvio_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
6.197	1.308	tNET	FF	2	R16C8[0][B]	gw_gao_gvio_inst_0/u_la0_top/n1274_s0/I1
7.242	1.045	tINS	FF	1	R16C8[0][B]	gw_gao_gvio_inst_0/u_la0_top/n1274_s0/COUT
7.242	0.000	tNET	FF	2	R16C8[1][A]	gw_gao_gvio_inst_0/u_la0_top/n1275_s0/CIN
7.299	0.057	tINS	FF	1	R16C8[1][A]	gw_gao_gvio_inst_0/u_la0_top/n1275_s0/COUT
7.299	0.000	tNET	FF	2	R16C8[1][B]	gw_gao_gvio_inst_0/u_la0_top/n1276_s0/CIN
7.356	0.057	tINS	FF	1	R16C8[1][B]	gw_gao_gvio_inst_0/u_la0_top/n1276_s0/COUT
7.356	0.000	tNET	FF	2	R16C8[2][A]	gw_gao_gvio_inst_0/u_la0_top/n1277_s0/CIN
7.413	0.057	tINS	FF	6	R16C8[2][A]	gw_gao_gvio_inst_0/u_la0_top/n1277_s0/COUT
9.474	2.060	tNET	FF	1	R18C13[0][B]	gw_gao_gvio_inst_0/u_la0_top/n1318_s2/I1
10.573	1.099	tINS	FF	1	R18C13[0][B]	gw_gao_gvio_inst_0/u_la0_top/n1318_s2/F
10.573	0.000	tNET	FF	1	R18C13[0][B]	gw_gao_gvio_inst_0/u_la0_top/triger_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R18C13[0][B]	gw_gao_gvio_inst_0/u_la0_top/triger_s0/CLK
10.542	-0.030	tUnc				gw_gao_gvio_inst_0/u_la0_top/triger_s0
10.142	-0.400	tSu		1	R18C13[0][B]	gw_gao_gvio_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew	-3.859
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 3.070, 69.285%; route: 1.361, 30.715%
Arrival Data Path Delay	cell: 2.315, 37.692%; route: 3.369, 54.846%; tC2Q: 0.458, 7.462%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path13

Path Summary:

Slack	-0.365
Data Arrival Time	10.507
Data Required Time	10.142
From	gw_gao_gvio_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
2.088	2.088	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
2.088	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
3.070	0.982	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
4.431	1.361	tNET	RR	1	R18C10[0][A]	gw_gao_gvio_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
4.889	0.458	tC2Q	RF	2	R18C10[0][A]	gw_gao_gvio_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
6.197	1.308	tNET	FF	2	R16C8[0][B]	gw_gao_gvio_inst_0/u_la0_top/n1274_s0/I1
7.242	1.045	tINS	FF	1	R16C8[0][B]	gw_gao_gvio_inst_0/u_la0_top/n1274_s0/COUT
7.242	0.000	tNET	FF	2	R16C8[1][A]	gw_gao_gvio_inst_0/u_la0_top/n1275_s0/CIN
7.299	0.057	tINS	FF	1	R16C8[1][A]	gw_gao_gvio_inst_0/u_la0_top/n1275_s0/COUT
7.299	0.000	tNET	FF	2	R16C8[1][B]	gw_gao_gvio_inst_0/u_la0_top/n1276_s0/CIN
7.356	0.057	tINS	FF	1	R16C8[1][B]	gw_gao_gvio_inst_0/u_la0_top/n1276_s0/COUT
7.356	0.000	tNET	FF	2	R16C8[2][A]	gw_gao_gvio_inst_0/u_la0_top/n1277_s0/CIN
7.410	0.054	tINS	FR	6	R16C8[2][A]	gw_gao_gvio_inst_0/u_la0_top/n1277_s0/COUT
8.371	0.961	tNET	RR	1	R16C9[1][B]	gw_gao_gvio_inst_0/u_la0_top/n1298_s2/I1
9.403	1.032	tINS	RF	1	R16C9[1][B]	gw_gao_gvio_inst_0/u_la0_top/n1298_s2/F
9.408	0.005	tNET	FF	1	R16C9[2][B]	gw_gao_gvio_inst_0/u_la0_top/n1297_s1/I3
10.507	1.099	tINS	FF	1	R16C9[2][B]	gw_gao_gvio_inst_0/u_la0_top/n1297_s1/F
10.507	0.000	tNET	FF	1	R16C9[2][B]	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R16C9[2][B]	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
10.542	-0.030	tUnc				gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_2_s1
10.142	-0.400	tSu		1	R16C9[2][B]	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	-3.859
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 3.070, 69.285%; route: 1.361, 30.715%
Arrival Data Path Delay	cell: 3.344, 55.030%; route: 2.274, 37.427%; tC2Q: 0.458, 7.543%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path14

Path Summary:

Slack	-0.116
Data Arrival Time	10.258
Data Required Time	10.142
From	gw_gao_gvio_inst_0/u_la0_top/capture_windows_num_0_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
2.088	2.088	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
2.088	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
3.070	0.982	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
4.431	1.361	tNET	RR	1	R18C10[1][A]	gw_gao_gvio_inst_0/u_la0_top/capture_windows_num_0_s0/CLK
4.889	0.458	tC2Q	RF	3	R18C10[1][A]	gw_gao_gvio_inst_0/u_la0_top/capture_windows_num_0_s0/Q
6.527	1.638	tNET	FF	1	R20C13[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s12/I0
7.152	0.625	tINS	FR	1	R20C13[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s12/F
7.571	0.419	tNET	RR	1	R20C14[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s10/I0
8.393	0.822	tINS	RF	1	R20C14[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s10/F
8.398	0.005	tNET	FF	1	R20C14[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s9/I2
9.220	0.822	tINS	FF	1	R20C14[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s9/F
9.226	0.005	tNET	FF	1	R20C14[0][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s8/I0
10.258	1.032	tINS	FF	1	R20C14[0][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s8/F
10.258	0.000	tNET	FF	1	R20C14[0][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R20C14[0][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0/CLK
10.542	-0.030	tUnc				gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0
10.142	-0.400	tSu		1	R20C14[0][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0

Path Statistics:

Clock Skew	-3.859
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 3.070, 69.285%; route: 1.361, 30.715%
Arrival Data Path Delay	cell: 3.301, 56.650%; route: 2.068, 35.485%; tC2Q: 0.458, 7.866%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path15

Path Summary:

Slack	-0.080
Data Arrival Time	10.578
Data Required Time	10.499
From	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_rem_0_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
2.088	2.088	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
2.088	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
3.070	0.982	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
4.431	1.361	tNET	RR	1	R21C10[1][A]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_rem_0_s0/CLK
4.889	0.458	tC2Q	RF	3	R21C10[1][A]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_rem_0_s0/Q
6.665	1.776	tNET	FF	1	R24C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/I0
7.764	1.099	tINS	FF	1	R24C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/F
7.770	0.005	tNET	FF	1	R24C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I0
8.802	1.032	tINS	FF	3	R24C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
9.617	0.815	tNET	FF	1	R23C14[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/I0
10.242	0.625	tINS	FR	1	R23C14[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/F
10.578	0.336	tNET	RR	1	R23C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R23C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
10.542	-0.030	tUnc				gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
10.499	-0.043	tSu		1	R23C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-3.859
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 3.070, 69.285%; route: 1.361, 30.715%
Arrival Data Path Delay	cell: 2.756, 44.831%; route: 2.933, 47.714%; tC2Q: 0.458, 7.455%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path16

Path Summary:

Slack	0.272
Data Arrival Time	9.870
Data Required Time	10.142
From	gw_gao_gvio_inst_0/u_la0_top/capture_windows_num_1_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
2.088	2.088	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
2.088	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
3.070	0.982	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
4.431	1.361	tNET	RR	1	R17C11[0][A]	gw_gao_gvio_inst_0/u_la0_top/capture_windows_num_1_s0/CLK
4.889	0.458	tC2Q	RF	4	R17C11[0][A]	gw_gao_gvio_inst_0/u_la0_top/capture_windows_num_1_s0/Q
6.681	1.792	tNET	FF	1	R20C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s10/I0
7.307	0.626	tINS	FF	1	R20C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s10/F
7.312	0.005	tNET	FF	1	R20C14[1][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s9/I0
7.938	0.626	tINS	FF	1	R20C14[1][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s9/F
7.944	0.005	tNET	FF	1	R20C14[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s8/I0
9.043	1.099	tINS	FF	1	R20C14[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s8/F
9.048	0.005	tNET	FF	1	R20C14[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s7/I0
9.870	0.822	tINS	FF	1	R20C14[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s7/F
9.870	0.000	tNET	FF	1	R20C14[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R20C14[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0/CLK
10.542	-0.030	tUnc				gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0
10.142	-0.400	tSu		1	R20C14[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0

Path Statistics:

Clock Skew	-3.859
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 3.070, 69.285%; route: 1.361, 30.715%
Arrival Data Path Delay	cell: 3.173, 58.334%; route: 1.808, 33.240%; tC2Q: 0.458, 8.426%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path17

Path Summary:

Slack	0.316
Data Arrival Time	9.826
Data Required Time	10.142
From	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/internal_reg_match_m1_en_0_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
2.088	2.088	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
2.088	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
3.070	0.982	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
4.431	1.361	tNET	RR	1	R20C9[1][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/internal_reg_match_m1_en_0_s0/CLK
4.889	0.458	tC2Q	RF	3	R20C9[1][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/internal_reg_match_m1_en_0_s0/Q
6.192	1.303	tNET	FF	1	R17C8[1][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/n156_s2/I1
7.291	1.099	tINS	FF	1	R17C8[1][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/n156_s2/F
7.297	0.005	tNET	FF	1	R17C8[2][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/n156_s1/I3
8.396	1.099	tINS	FF	1	R17C8[2][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/n156_s1/F
9.200	0.804	tNET	FF	1	R18C7[2][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/n156_s0/I1
9.826	0.626	tINS	FF	1	R18C7[2][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/n156_s0/F
9.826	0.000	tNET	FF	1	R18C7[2][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R18C7[2][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
10.542	-0.030	tUnc				gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
10.142	-0.400	tSu		1	R18C7[2][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	-3.859
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 3.070, 69.285%; route: 1.361, 30.715%
Arrival Data Path Delay	cell: 2.824, 52.344%; route: 2.113, 39.161%; tC2Q: 0.458, 8.495%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path18

Path Summary:

Slack	0.460
Data Arrival Time	9.712
Data Required Time	10.172
From	dut/u_tdc/q_d_7_s0
To	dut/u_tdc/count_tmp_6_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.572	0.242	tNET	RR	1	R23C22[2][A]	dut/u_tdc/q_d_7_s0/CLK
1.030	0.458	tC2Q	RF	2	R23C22[2][A]	dut/u_tdc/q_d_7_s0/Q
1.375	0.345	tNET	FF	1	R23C22[3][A]	dut/u_tdc/n176_s3/I1
2.436	1.061	tINS	FR	2	R23C22[3][A]	dut/u_tdc/n176_s3/F
2.859	0.423	tNET	RR	1	R22C22[0][B]	dut/u_tdc/n175_s4/I0
3.681	0.822	tINS	RF	2	R22C22[0][B]	dut/u_tdc/n175_s4/F
5.305	1.624	tNET	FF	1	R18C22[3][B]	dut/u_tdc/n174_s4/I0
6.337	1.032	tINS	FF	4	R18C22[3][B]	dut/u_tdc/n174_s4/F
7.164	0.827	tNET	FF	1	R17C23[3][B]	dut/u_tdc/n170_s3/I2
8.190	1.026	tINS	FR	4	R17C23[3][B]	dut/u_tdc/n170_s3/F
8.613	0.423	tNET	RR	1	R17C22[0][B]	dut/u_tdc/n170_s10/I1
9.712	1.099	tINS	RF	1	R17C22[0][B]	dut/u_tdc/n170_s10/F
9.712	0.000	tNET	FF	1	R17C22[0][B]	dut/u_tdc/count_tmp_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R17C22[0][B]	dut/u_tdc/count_tmp_6_s1/CLK
10.172	-0.400	tSu		1	R17C22[0][B]	dut/u_tdc/count_tmp_6_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 5.040, 55.143%; route: 3.642, 39.843%; tC2Q: 0.458, 5.015%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path19

Path Summary:

Slack	0.502
Data Arrival Time	9.640
Data Required Time	10.142
From	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_rem_0_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
2.088	2.088	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
2.088	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
3.070	0.982	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
4.431	1.361	tNET	RR	1	R21C10[1][A]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_rem_0_s0/CLK
4.889	0.458	tC2Q	RF	3	R21C10[1][A]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_rem_0_s0/Q
6.665	1.776	tNET	FF	1	R24C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/I0
7.764	1.099	tINS	FF	1	R24C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/F
7.770	0.005	tNET	FF	1	R24C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I0
8.802	1.032	tINS	FF	3	R24C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
8.818	0.016	tNET	FF	1	R24C13[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n146_s3/I1
9.640	0.822	tINS	FF	1	R24C13[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n146_s3/F
9.640	0.000	tNET	FF	1	R24C13[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R24C13[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
10.542	-0.030	tUnc				gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
10.142	-0.400	tSu		1	R24C13[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-3.859
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 3.070, 69.285%; route: 1.361, 30.715%
Arrival Data Path Delay	cell: 2.953, 56.686%; route: 1.798, 34.516%; tC2Q: 0.458, 8.798%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path20

Path Summary:

Slack	0.527
Data Arrival Time	9.645
Data Required Time	10.172
From	dut/u_tdc/q_d_7_s0
To	dut/u_tdc/count_tmp_9_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.572	0.242	tNET	RR	1	R23C22[2][A]	dut/u_tdc/q_d_7_s0/CLK
1.030	0.458	tC2Q	RF	2	R23C22[2][A]	dut/u_tdc/q_d_7_s0/Q
1.375	0.345	tNET	FF	1	R23C22[3][A]	dut/u_tdc/n176_s3/I1
2.436	1.061	tINS	FR	2	R23C22[3][A]	dut/u_tdc/n176_s3/F
2.859	0.423	tNET	RR	1	R22C22[0][B]	dut/u_tdc/n175_s4/I0
3.681	0.822	tINS	RF	2	R22C22[0][B]	dut/u_tdc/n175_s4/F
5.305	1.624	tNET	FF	1	R18C22[3][B]	dut/u_tdc/n174_s4/I0
6.337	1.032	tINS	FF	4	R18C22[3][B]	dut/u_tdc/n174_s4/F
7.164	0.827	tNET	FF	1	R17C23[3][B]	dut/u_tdc/n170_s3/I2
8.190	1.026	tINS	FR	4	R17C23[3][B]	dut/u_tdc/n170_s3/F
8.613	0.423	tNET	RR	1	R16C23[1][A]	dut/u_tdc/n167_s2/I0
9.645	1.032	tINS	RF	1	R16C23[1][A]	dut/u_tdc/n167_s2/F
9.645	0.000	tNET	FF	1	R16C23[1][A]	dut/u_tdc/count_tmp_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R16C23[1][A]	dut/u_tdc/count_tmp_9_s1/CLK
10.172	-0.400	tSu		1	R16C23[1][A]	dut/u_tdc/count_tmp_9_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 4.973, 54.811%; route: 3.642, 40.137%; tC2Q: 0.458, 5.052%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path21

Path Summary:

Slack	0.530
Data Arrival Time	9.642
Data Required Time	10.172
From	dut/u_tdc/q_d_7_s0
To	dut/u_tdc/count_tmp_7_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.572	0.242	tNET	RR	1	R23C22[2][A]	dut/u_tdc/q_d_7_s0/CLK
1.030	0.458	tC2Q	RF	2	R23C22[2][A]	dut/u_tdc/q_d_7_s0/Q
1.375	0.345	tNET	FF	1	R23C22[3][A]	dut/u_tdc/n176_s3/I1
2.436	1.061	tINS	FR	2	R23C22[3][A]	dut/u_tdc/n176_s3/F
2.859	0.423	tNET	RR	1	R22C22[0][B]	dut/u_tdc/n175_s4/I0
3.681	0.822	tINS	RF	2	R22C22[0][B]	dut/u_tdc/n175_s4/F
5.305	1.624	tNET	FF	1	R18C22[3][B]	dut/u_tdc/n174_s4/I0
6.337	1.032	tINS	FF	4	R18C22[3][B]	dut/u_tdc/n174_s4/F
7.164	0.827	tNET	FF	1	R17C23[3][B]	dut/u_tdc/n170_s3/I2
8.196	1.032	tINS	FF	4	R17C23[3][B]	dut/u_tdc/n170_s3/F
9.016	0.820	tNET	FF	1	R16C22[0][B]	dut/u_tdc/n169_s2/I0
9.642	0.626	tINS	FF	1	R16C22[0][B]	dut/u_tdc/n169_s2/F
9.642	0.000	tNET	FF	1	R16C22[0][B]	dut/u_tdc/count_tmp_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R16C22[0][B]	dut/u_tdc/count_tmp_7_s1/CLK
10.172	-0.400	tSu		1	R16C22[0][B]	dut/u_tdc/count_tmp_7_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 4.573, 50.419%; route: 4.039, 44.528%; tC2Q: 0.458, 5.053%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path22

Path Summary:

Slack	0.530
Data Arrival Time	9.642
Data Required Time	10.172
From	dut/u_tdc/q_d_7_s0
To	dut/u_tdc/count_tmp_8_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.572	0.242	tNET	RR	1	R23C22[2][A]	dut/u_tdc/q_d_7_s0/CLK
1.030	0.458	tC2Q	RF	2	R23C22[2][A]	dut/u_tdc/q_d_7_s0/Q
1.375	0.345	tNET	FF	1	R23C22[3][A]	dut/u_tdc/n176_s3/I1
2.436	1.061	tINS	FR	2	R23C22[3][A]	dut/u_tdc/n176_s3/F
2.859	0.423	tNET	RR	1	R22C22[0][B]	dut/u_tdc/n175_s4/I0
3.681	0.822	tINS	RF	2	R22C22[0][B]	dut/u_tdc/n175_s4/F
5.305	1.624	tNET	FF	1	R18C22[3][B]	dut/u_tdc/n174_s4/I0
6.337	1.032	tINS	FF	4	R18C22[3][B]	dut/u_tdc/n174_s4/F
7.164	0.827	tNET	FF	1	R17C23[3][B]	dut/u_tdc/n170_s3/I2
8.196	1.032	tINS	FF	4	R17C23[3][B]	dut/u_tdc/n170_s3/F
9.016	0.820	tNET	FF	1	R16C22[1][A]	dut/u_tdc/n168_s2/I0
9.642	0.626	tINS	FF	1	R16C22[1][A]	dut/u_tdc/n168_s2/F
9.642	0.000	tNET	FF	1	R16C22[1][A]	dut/u_tdc/count_tmp_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R16C22[1][A]	dut/u_tdc/count_tmp_8_s1/CLK
10.172	-0.400	tSu		1	R16C22[1][A]	dut/u_tdc/count_tmp_8_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 4.573, 50.419%; route: 4.039, 44.528%; tC2Q: 0.458, 5.053%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path23

Path Summary:

Slack	0.542
Data Arrival Time	9.957
Data Required Time	10.499
From	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_rem_0_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
2.088	2.088	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
2.088	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
3.070	0.982	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
4.431	1.361	tNET	RR	1	R21C10[1][A]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_rem_0_s0/CLK
4.889	0.458	tC2Q	RF	3	R21C10[1][A]	gw_gao_gvio_inst_0/u_la0_top/capture_mem_addr_rem_0_s0/Q
6.665	1.776	tNET	FF	1	R24C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/I0
7.764	1.099	tINS	FF	1	R24C13[3][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/F
7.770	0.005	tNET	FF	1	R24C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I0
8.802	1.032	tINS	FF	3	R24C13[3][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
8.818	0.016	tNET	FF	1	R24C13[0][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s7/I1
9.620	0.802	tINS	FR	1	R24C13[0][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s7/F
9.957	0.336	tNET	RR	1	R24C13[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R24C13[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
10.542	-0.030	tUnc				gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
10.499	-0.043	tSu		1	R24C13[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-3.859
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 3.070, 69.285%; route: 1.361, 30.715%
Arrival Data Path Delay	cell: 2.933, 53.079%; route: 2.134, 38.626%; tC2Q: 0.458, 8.295%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path24

Path Summary:

Slack	0.739
Data Arrival Time	9.403
Data Required Time	10.142
From	gw_gao_gvio_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
2.088	2.088	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
2.088	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
3.070	0.982	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
4.431	1.361	tNET	RR	1	R18C10[0][A]	gw_gao_gvio_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
4.889	0.458	tC2Q	RF	2	R18C10[0][A]	gw_gao_gvio_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
6.197	1.308	tNET	FF	2	R16C8[0][B]	gw_gao_gvio_inst_0/u_la0_top/n1274_s0/I1
7.242	1.045	tINS	FF	1	R16C8[0][B]	gw_gao_gvio_inst_0/u_la0_top/n1274_s0/COUT
7.242	0.000	tNET	FF	2	R16C8[1][A]	gw_gao_gvio_inst_0/u_la0_top/n1275_s0/CIN
7.299	0.057	tINS	FF	1	R16C8[1][A]	gw_gao_gvio_inst_0/u_la0_top/n1275_s0/COUT
7.299	0.000	tNET	FF	2	R16C8[1][B]	gw_gao_gvio_inst_0/u_la0_top/n1276_s0/CIN
7.356	0.057	tINS	FF	1	R16C8[1][B]	gw_gao_gvio_inst_0/u_la0_top/n1276_s0/COUT
7.356	0.000	tNET	FF	2	R16C8[2][A]	gw_gao_gvio_inst_0/u_la0_top/n1277_s0/CIN
7.410	0.054	tINS	FR	6	R16C8[2][A]	gw_gao_gvio_inst_0/u_la0_top/n1277_s0/COUT
8.371	0.961	tNET	RR	1	R16C9[1][A]	gw_gao_gvio_inst_0/u_la0_top/n1298_s3/I3
9.403	1.032	tINS	RF	1	R16C9[1][A]	gw_gao_gvio_inst_0/u_la0_top/n1298_s3/F
9.403	0.000	tNET	FF	1	R16C9[1][A]	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R16C9[1][A]	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
10.542	-0.030	tUnc				gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_1_s1
10.142	-0.400	tSu		1	R16C9[1][A]	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	-3.859
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 3.070, 69.285%; route: 1.361, 30.715%
Arrival Data Path Delay	cell: 2.245, 45.151%; route: 2.269, 45.631%; tC2Q: 0.458, 9.218%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path25

Path Summary:

Slack	0.739
Data Arrival Time	9.403
Data Required Time	10.142
From	gw_gao_gvio_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
2.088	2.088	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
2.088	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
3.070	0.982	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
4.431	1.361	tNET	RR	1	R18C10[0][A]	gw_gao_gvio_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
4.889	0.458	tC2Q	RF	2	R18C10[0][A]	gw_gao_gvio_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
6.197	1.308	tNET	FF	2	R16C8[0][B]	gw_gao_gvio_inst_0/u_la0_top/n1274_s0/I1
7.242	1.045	tINS	FF	1	R16C8[0][B]	gw_gao_gvio_inst_0/u_la0_top/n1274_s0/COUT
7.242	0.000	tNET	FF	2	R16C8[1][A]	gw_gao_gvio_inst_0/u_la0_top/n1275_s0/CIN
7.299	0.057	tINS	FF	1	R16C8[1][A]	gw_gao_gvio_inst_0/u_la0_top/n1275_s0/COUT
7.299	0.000	tNET	FF	2	R16C8[1][B]	gw_gao_gvio_inst_0/u_la0_top/n1276_s0/CIN
7.356	0.057	tINS	FF	1	R16C8[1][B]	gw_gao_gvio_inst_0/u_la0_top/n1276_s0/COUT
7.356	0.000	tNET	FF	2	R16C8[2][A]	gw_gao_gvio_inst_0/u_la0_top/n1277_s0/CIN
7.410	0.054	tINS	FR	6	R16C8[2][A]	gw_gao_gvio_inst_0/u_la0_top/n1277_s0/COUT
8.371	0.961	tNET	RR	1	R16C9[2][A]	gw_gao_gvio_inst_0/u_la0_top/n1296_s3/I2
9.403	1.032	tINS	RF	1	R16C9[2][A]	gw_gao_gvio_inst_0/u_la0_top/n1296_s3/F
9.403	0.000	tNET	FF	1	R16C9[2][A]	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R16C9[2][A]	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
10.542	-0.030	tUnc				gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1
10.142	-0.400	tSu		1	R16C9[2][A]	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	-3.859
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 3.070, 69.285%; route: 1.361, 30.715%
Arrival Data Path Delay	cell: 2.245, 45.151%; route: 2.269, 45.631%; tC2Q: 0.458, 9.218%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-1.592
Data Arrival Time	51.640
Data Required Time	53.232
From	gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_7_s1
To	gw_gao_gvio_inst_0/u_la0_top/capture_end_tck_0_s0
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
50.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
50.513	0.183	tNET	RR	1	R16C14[1][B]	gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
50.846	0.333	tC2Q	RF	3	R16C14[1][B]	gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_7_s1/Q
51.084	0.238	tNET	FF	1	R17C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/n1310_s1/I2
51.640	0.556	tINS	FR	1	R17C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/n1310_s1/F
51.640	0.000	tNET	RR	1	R17C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/capture_end_tck_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
51.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
51.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
52.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
53.202	0.966	tNET	RR	1	R17C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/capture_end_tck_0_s0/CLK
53.232	0.030	tUnc				gw_gao_gvio_inst_0/u_la0_top/capture_end_tck_0_s0
53.232	0.000	tHld		1	R17C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/capture_end_tck_0_s0

Path Statistics:

Clock Skew	2.689
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.556, 49.333%; route: 0.238, 21.092%; tC2Q: 0.333, 29.576%
Required Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%

Path2

Path Summary:

Slack	0.708
Data Arrival Time	3.910
Data Required Time	3.202
From	gw_gao_gvio_inst_0/u_la0_top/bit_count_0_s1
To	gw_gao_gvio_inst_0/u_la0_top/bit_count_0_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R20C4[1][A]	gw_gao_gvio_inst_0/u_la0_top/bit_count_0_s1/CLK
3.536	0.333	tC2Q	RR	6	R20C4[1][A]	gw_gao_gvio_inst_0/u_la0_top/bit_count_0_s1/Q
3.538	0.002	tNET	RR	1	R20C4[1][A]	gw_gao_gvio_inst_0/u_la0_top/n485_s4/I0
3.910	0.372	tINS	RF	1	R20C4[1][A]	gw_gao_gvio_inst_0/u_la0_top/n485_s4/F
3.910	0.000	tNET	FF	1	R20C4[1][A]	gw_gao_gvio_inst_0/u_la0_top/bit_count_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R20C4[1][A]	gw_gao_gvio_inst_0/u_la0_top/bit_count_0_s1/CLK
3.202	0.000	tHld		1	R20C4[1][A]	gw_gao_gvio_inst_0/u_la0_top/bit_count_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%

Path3

Path Summary:

Slack	0.708
Data Arrival Time	3.910
Data Required Time	3.202
From	gw_gao_gvio_inst_0/u_la0_top/bit_count_3_s1
To	gw_gao_gvio_inst_0/u_la0_top/bit_count_3_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R20C4[0][A]	gw_gao_gvio_inst_0/u_la0_top/bit_count_3_s1/CLK
3.536	0.333	tC2Q	RR	3	R20C4[0][A]	gw_gao_gvio_inst_0/u_la0_top/bit_count_3_s1/Q
3.538	0.002	tNET	RR	1	R20C4[0][A]	gw_gao_gvio_inst_0/u_la0_top/n482_s2/I2
3.910	0.372	tINS	RF	1	R20C4[0][A]	gw_gao_gvio_inst_0/u_la0_top/n482_s2/F
3.910	0.000	tNET	FF	1	R20C4[0][A]	gw_gao_gvio_inst_0/u_la0_top/bit_count_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R20C4[0][A]	gw_gao_gvio_inst_0/u_la0_top/bit_count_3_s1/CLK
3.202	0.000	tHld		1	R20C4[0][A]	gw_gao_gvio_inst_0/u_la0_top/bit_count_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%

Path4

Path Summary:

Slack	0.708
Data Arrival Time	3.910
Data Required Time	3.202
From	gw_gao_gvio_inst_0/u_la0_top/word_count_7_s0
To	gw_gao_gvio_inst_0/u_la0_top/word_count_7_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R17C10[1][A]	gw_gao_gvio_inst_0/u_la0_top/word_count_7_s0/CLK
3.536	0.333	tC2Q	RR	4	R17C10[1][A]	gw_gao_gvio_inst_0/u_la0_top/word_count_7_s0/Q
3.538	0.002	tNET	RR	1	R17C10[1][A]	gw_gao_gvio_inst_0/u_la0_top/data_to_word_counter_7_s0/I1
3.910	0.372	tINS	RF	1	R17C10[1][A]	gw_gao_gvio_inst_0/u_la0_top/data_to_word_counter_7_s0/F
3.910	0.000	tNET	FF	1	R17C10[1][A]	gw_gao_gvio_inst_0/u_la0_top/word_count_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R17C10[1][A]	gw_gao_gvio_inst_0/u_la0_top/word_count_7_s0/CLK
3.202	0.000	tHld		1	R17C10[1][A]	gw_gao_gvio_inst_0/u_la0_top/word_count_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%

Path5

Path Summary:

Slack	0.708
Data Arrival Time	3.910
Data Required Time	3.202
From	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_5_s1
To	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_5_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R18C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_5_s1/CLK
3.536	0.333	tC2Q	RR	4	R18C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_5_s1/Q
3.538	0.002	tNET	RR	1	R18C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/n534_s2/I3
3.910	0.372	tINS	RF	1	R18C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/n534_s2/F
3.910	0.000	tNET	FF	1	R18C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R18C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_5_s1/CLK
3.202	0.000	tHld		1	R18C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%

Path6

Path Summary:

Slack	0.708
Data Arrival Time	3.910
Data Required Time	3.202
From	gw_gao_gvio_inst_0/u_gvio0_top/addr_all_5_s1
To	gw_gao_gvio_inst_0/u_gvio0_top/addr_all_5_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R21C20[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/addr_all_5_s1/CLK
3.536	0.333	tC2Q	RR	5	R21C20[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/addr_all_5_s1/Q
3.538	0.002	tNET	RR	1	R21C20[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/n291_s2/I3
3.910	0.372	tINS	RF	1	R21C20[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/n291_s2/F
3.910	0.000	tNET	FF	1	R21C20[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/addr_all_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R21C20[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/addr_all_5_s1/CLK
3.202	0.000	tHld		1	R21C20[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/addr_all_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%

Path7

Path Summary:

Slack	0.708
Data Arrival Time	3.910
Data Required Time	3.202
From	gw_gao_gvio_inst_0/u_gvio0_top/word_count_3_s0
To	gw_gao_gvio_inst_0/u_gvio0_top/word_count_3_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R17C20[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_3_s0/CLK
3.536	0.333	tC2Q	RR	2	R17C20[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_3_s0/Q
3.538	0.002	tNET	RR	1	R17C20[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_3_s2/I3
3.910	0.372	tINS	RF	1	R17C20[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_3_s2/F
3.910	0.000	tNET	FF	1	R17C20[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R17C20[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_3_s0/CLK
3.202	0.000	tHld		1	R17C20[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%

Path8

Path Summary:

Slack	0.708
Data Arrival Time	3.910
Data Required Time	3.202
From	gw_gao_gvio_inst_0/u_gvio0_top/word_count_11_s0
To	gw_gao_gvio_inst_0/u_gvio0_top/word_count_11_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R17C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_11_s0/CLK
3.536	0.333	tC2Q	RR	3	R17C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_11_s0/Q
3.538	0.002	tNET	RR	1	R17C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_11_s2/I3
3.910	0.372	tINS	RF	1	R17C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_11_s2/F
3.910	0.000	tNET	FF	1	R17C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R17C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_11_s0/CLK
3.202	0.000	tHld		1	R17C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%

Path9

Path Summary:

Slack	0.708
Data Arrival Time	3.910
Data Required Time	3.202
From	gw_gao_gvio_inst_0/u_gvio0_top/word_count_12_s0
To	gw_gao_gvio_inst_0/u_gvio0_top/word_count_12_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R17C21[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_12_s0/CLK
3.536	0.333	tC2Q	RR	2	R17C21[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_12_s0/Q
3.538	0.002	tNET	RR	1	R17C21[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_12_s2/I3
3.910	0.372	tINS	RF	1	R17C21[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_12_s2/F
3.910	0.000	tNET	FF	1	R17C21[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R17C21[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_12_s0/CLK
3.202	0.000	tHld		1	R17C21[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%

Path10

Path Summary:

Slack	0.708
Data Arrival Time	3.910
Data Required Time	3.202
From	gw_gao_gvio_inst_0/u_gvio0_top/word_count_15_s0
To	gw_gao_gvio_inst_0/u_gvio0_top/word_count_15_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R17C19[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_15_s0/CLK
3.536	0.333	tC2Q	RR	2	R17C19[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_15_s0/Q
3.538	0.002	tNET	RR	1	R17C19[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_15_s2/I3
3.910	0.372	tINS	RF	1	R17C19[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_15_s2/F
3.910	0.000	tNET	FF	1	R17C19[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R17C19[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_15_s0/CLK
3.202	0.000	tHld		1	R17C19[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_15_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%

Path11

Path Summary:

Slack	0.708
Data Arrival Time	3.910
Data Required Time	3.202
From	gw_gao_gvio_inst_0/u_gvio_icon_top/tdo_select_s5
To	gw_gao_gvio_inst_0/u_gvio_icon_top/tdo_select_s5
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R20C16[0][A]	gw_gao_gvio_inst_0/u_gvio_icon_top/tdo_select_s5/CLK
3.536	0.333	tC2Q	RR	2	R20C16[0][A]	gw_gao_gvio_inst_0/u_gvio_icon_top/tdo_select_s5/Q
3.538	0.002	tNET	RR	1	R20C16[0][A]	gw_gao_gvio_inst_0/u_gvio_icon_top/n47_s4/I1
3.910	0.372	tINS	RF	1	R20C16[0][A]	gw_gao_gvio_inst_0/u_gvio_icon_top/n47_s4/F
3.910	0.000	tNET	FF	1	R20C16[0][A]	gw_gao_gvio_inst_0/u_gvio_icon_top/tdo_select_s5/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R20C16[0][A]	gw_gao_gvio_inst_0/u_gvio_icon_top/tdo_select_s5/CLK
3.202	0.000	tHld		1	R20C16[0][A]	gw_gao_gvio_inst_0/u_gvio_icon_top/tdo_select_s5

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%

Path12

Path Summary:

Slack	0.708
Data Arrival Time	1.221
Data Required Time	0.513
From	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R25C13[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
0.846	0.333	tC2Q	RR	3	R25C13[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/Q
0.849	0.002	tNET	RR	1	R25C13[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n162_s0/I1
1.221	0.372	tINS	RF	1	R25C13[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n162_s0/F
1.221	0.000	tNET	FF	1	R25C13[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R25C13[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
0.513	0.000	tHld		1	R25C13[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path13

Path Summary:

Slack	0.709
Data Arrival Time	1.222
Data Required Time	0.513
From	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R25C14[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
0.846	0.333	tC2Q	RR	3	R25C14[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/Q
0.850	0.004	tNET	RR	1	R25C14[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n164_s0/I1
1.222	0.372	tINS	RF	1	R25C14[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n164_s0/F
1.222	0.000	tNET	FF	1	R25C14[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R25C14[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
0.513	0.000	tHld		1	R25C14[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path14

Path Summary:

Slack	0.709
Data Arrival Time	1.222
Data Required Time	0.513
From	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R25C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
0.846	0.333	tC2Q	RR	5	R25C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q
0.850	0.004	tNET	RR	1	R25C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n166_s0/I2
1.222	0.372	tINS	RF	1	R25C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n166_s0/F
1.222	0.000	tNET	FF	1	R25C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R25C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
0.513	0.000	tHld		1	R25C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path15

Path Summary:

Slack	0.709
Data Arrival Time	1.222
Data Required Time	0.513
From	gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1
To	gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R16C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
0.846	0.333	tC2Q	RR	3	R16C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1/Q
0.850	0.004	tNET	RR	1	R16C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/n1336_s1/I2
1.222	0.372	tINS	RF	1	R16C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/n1336_s1/F
1.222	0.000	tNET	FF	1	R16C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R16C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
0.513	0.000	tHld		1	R16C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path16

Path Summary:

Slack	0.709
Data Arrival Time	3.911
Data Required Time	3.202
From	gw_gao_gvio_inst_0/u_la0_top/word_count_1_s0
To	gw_gao_gvio_inst_0/u_la0_top/word_count_1_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R21C9[1][A]	gw_gao_gvio_inst_0/u_la0_top/word_count_1_s0/CLK
3.536	0.333	tC2Q	RR	5	R21C9[1][A]	gw_gao_gvio_inst_0/u_la0_top/word_count_1_s0/Q
3.539	0.004	tNET	RR	1	R21C9[1][A]	gw_gao_gvio_inst_0/u_la0_top/data_to_word_counter_1_s0/I2
3.911	0.372	tINS	RF	1	R21C9[1][A]	gw_gao_gvio_inst_0/u_la0_top/data_to_word_counter_1_s0/F
3.911	0.000	tNET	FF	1	R21C9[1][A]	gw_gao_gvio_inst_0/u_la0_top/word_count_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R21C9[1][A]	gw_gao_gvio_inst_0/u_la0_top/word_count_1_s0/CLK
3.202	0.000	tHld		1	R21C9[1][A]	gw_gao_gvio_inst_0/u_la0_top/word_count_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%

Path17

Path Summary:

Slack	0.709
Data Arrival Time	3.911
Data Required Time	3.202
From	gw_gao_gvio_inst_0/u_la0_top/word_count_2_s0
To	gw_gao_gvio_inst_0/u_la0_top/word_count_2_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R21C9[0][A]	gw_gao_gvio_inst_0/u_la0_top/word_count_2_s0/CLK
3.536	0.333	tC2Q	RR	4	R21C9[0][A]	gw_gao_gvio_inst_0/u_la0_top/word_count_2_s0/Q
3.539	0.004	tNET	RR	1	R21C9[0][A]	gw_gao_gvio_inst_0/u_la0_top/data_to_word_counter_2_s0/I1
3.911	0.372	tINS	RF	1	R21C9[0][A]	gw_gao_gvio_inst_0/u_la0_top/data_to_word_counter_2_s0/F
3.911	0.000	tNET	FF	1	R21C9[0][A]	gw_gao_gvio_inst_0/u_la0_top/word_count_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R21C9[0][A]	gw_gao_gvio_inst_0/u_la0_top/word_count_2_s0/CLK
3.202	0.000	tHld		1	R21C9[0][A]	gw_gao_gvio_inst_0/u_la0_top/word_count_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%

Path18

Path Summary:

Slack	0.709
Data Arrival Time	3.911
Data Required Time	3.202
From	gw_gao_gvio_inst_0/u_la0_top/word_count_5_s0
To	gw_gao_gvio_inst_0/u_la0_top/word_count_5_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R22C9[1][A]	gw_gao_gvio_inst_0/u_la0_top/word_count_5_s0/CLK
3.536	0.333	tC2Q	RR	5	R22C9[1][A]	gw_gao_gvio_inst_0/u_la0_top/word_count_5_s0/Q
3.539	0.004	tNET	RR	1	R22C9[1][A]	gw_gao_gvio_inst_0/u_la0_top/data_to_word_counter_5_s0/I1
3.911	0.372	tINS	RF	1	R22C9[1][A]	gw_gao_gvio_inst_0/u_la0_top/data_to_word_counter_5_s0/F
3.911	0.000	tNET	FF	1	R22C9[1][A]	gw_gao_gvio_inst_0/u_la0_top/word_count_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R22C9[1][A]	gw_gao_gvio_inst_0/u_la0_top/word_count_5_s0/CLK
3.202	0.000	tHld		1	R22C9[1][A]	gw_gao_gvio_inst_0/u_la0_top/word_count_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%

Path19

Path Summary:

Slack	0.709
Data Arrival Time	3.911
Data Required Time	3.202
From	gw_gao_gvio_inst_0/u_la0_top/address_counter_4_s0
To	gw_gao_gvio_inst_0/u_la0_top/address_counter_4_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R24C7[0][A]	gw_gao_gvio_inst_0/u_la0_top/address_counter_4_s0/CLK
3.536	0.333	tC2Q	RR	5	R24C7[0][A]	gw_gao_gvio_inst_0/u_la0_top/address_counter_4_s0/Q
3.539	0.004	tNET	RR	1	R24C7[0][A]	gw_gao_gvio_inst_0/u_la0_top/data_to_addr_counter_4_s0/I1
3.911	0.372	tINS	RF	1	R24C7[0][A]	gw_gao_gvio_inst_0/u_la0_top/data_to_addr_counter_4_s0/F
3.911	0.000	tNET	FF	1	R24C7[0][A]	gw_gao_gvio_inst_0/u_la0_top/address_counter_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R24C7[0][A]	gw_gao_gvio_inst_0/u_la0_top/address_counter_4_s0/CLK
3.202	0.000	tHld		1	R24C7[0][A]	gw_gao_gvio_inst_0/u_la0_top/address_counter_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%

Path20

Path Summary:

Slack	0.709
Data Arrival Time	3.911
Data Required Time	3.202
From	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_2_s1
To	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_2_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R18C20[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_2_s1/CLK
3.536	0.333	tC2Q	RR	4	R18C20[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_2_s1/Q
3.539	0.004	tNET	RR	1	R18C20[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/n537_s4/I1
3.911	0.372	tINS	RF	1	R18C20[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/n537_s4/F
3.911	0.000	tNET	FF	1	R18C20[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R18C20[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_2_s1/CLK
3.202	0.000	tHld		1	R18C20[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%

Path21

Path Summary:

Slack	0.709
Data Arrival Time	3.911
Data Required Time	3.202
From	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_6_s1
To	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_6_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R18C20[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_6_s1/CLK
3.536	0.333	tC2Q	RR	3	R18C20[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_6_s1/Q
3.539	0.004	tNET	RR	1	R18C20[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/n533_s2/I3
3.911	0.372	tINS	RF	1	R18C20[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/n533_s2/F
3.911	0.000	tNET	FF	1	R18C20[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R18C20[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_6_s1/CLK
3.202	0.000	tHld		1	R18C20[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/bit_count_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%

Path22

Path Summary:

Slack	0.709
Data Arrival Time	3.911
Data Required Time	3.202
From	gw_gao_gvio_inst_0/u_gvio0_top/addr_all_2_s1
To	gw_gao_gvio_inst_0/u_gvio0_top/addr_all_2_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R22C19[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/addr_all_2_s1/CLK
3.536	0.333	tC2Q	RR	5	R22C19[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/addr_all_2_s1/Q
3.539	0.004	tNET	RR	1	R22C19[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/n294_s2/I3
3.911	0.372	tINS	RF	1	R22C19[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/n294_s2/F
3.911	0.000	tNET	FF	1	R22C19[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/addr_all_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R22C19[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/addr_all_2_s1/CLK
3.202	0.000	tHld		1	R22C19[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/addr_all_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%

Path23

Path Summary:

Slack	0.709
Data Arrival Time	3.911
Data Required Time	3.202
From	gw_gao_gvio_inst_0/u_gvio0_top/word_count_4_s0
To	gw_gao_gvio_inst_0/u_gvio0_top/word_count_4_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R18C21[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_4_s0/CLK
3.536	0.333	tC2Q	RR	4	R18C21[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_4_s0/Q
3.539	0.004	tNET	RR	1	R18C21[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_4_s2/I1
3.911	0.372	tINS	RF	1	R18C21[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_4_s2/F
3.911	0.000	tNET	FF	1	R18C21[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R18C21[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_4_s0/CLK
3.202	0.000	tHld		1	R18C21[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%

Path24

Path Summary:

Slack	0.709
Data Arrival Time	3.911
Data Required Time	3.202
From	gw_gao_gvio_inst_0/u_gvio0_top/word_count_8_s0
To	gw_gao_gvio_inst_0/u_gvio0_top/word_count_8_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R16C18[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_8_s0/CLK
3.536	0.333	tC2Q	RR	4	R16C18[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_8_s0/Q
3.539	0.004	tNET	RR	1	R16C18[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_8_s2/I3
3.911	0.372	tINS	RF	1	R16C18[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_8_s2/F
3.911	0.000	tNET	FF	1	R16C18[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R16C18[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_8_s0/CLK
3.202	0.000	tHld		1	R16C18[0][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%

Path25

Path Summary:

Slack	0.709
Data Arrival Time	3.911
Data Required Time	3.202
From	gw_gao_gvio_inst_0/u_gvio0_top/word_count_9_s0
To	gw_gao_gvio_inst_0/u_gvio0_top/word_count_9_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R16C18[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_9_s0/CLK
3.536	0.333	tC2Q	RR	3	R16C18[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_9_s0/Q
3.539	0.004	tNET	RR	1	R16C18[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_9_s2/I3
3.911	0.372	tINS	RF	1	R16C18[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_9_s2/F
3.911	0.000	tNET	FF	1	R16C18[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL11[B]	tck_pad_i_ibuf/I
1.392	1.392	tINS	RR	1	IOL11[B]	tck_pad_i_ibuf/O
1.392	0.000	tNET	RR	1	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236	0.844	tINS	RR	304	R1C1	gw_gao_gvio_inst_0/u_gw_jtag/tck_o
3.202	0.966	tNET	RR	1	R16C18[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_9_s0/CLK
3.202	0.000	tHld		1	R16C18[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/word_count_9_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 2.236, 69.836%; route: 0.966, 30.164%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-1.722
Data Arrival Time	5.412
Data Required Time	3.690
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/u_IDES8
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.572	0.242	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
1.030	0.458	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.366	0.336	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
2.465	1.099	tINS	RF	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
5.412	2.947	tNET	FF	8	IOB23[B]	dut/u_tdc/u_IDES8/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.250	1.250					active clock edge time
1.250	0.000					Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk
3.644	2.394	tCL	FF	2	PLL_L	Gowin_PLL/rpll_inst/CLKOUT
3.765	0.121	tNET	FF	1	IOB23[B]	dut/u_tdc/u_IDES8/FCLK
3.735	-0.030	tUnc				dut/u_tdc/u_IDES8
3.690	-0.045	tSu		1	IOB23[B]	dut/u_tdc/u_IDES8

Path Statistics:

Clock Skew	1.943
Setup Relationship	1.250
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 1.099, 22.705%; route: 3.283, 67.825%; tC2Q: 0.458, 9.469%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.121, 100.000%

Path2

Path Summary:

Slack	-0.479
Data Arrival Time	5.412
Data Required Time	4.934
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/u_IDES8
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.572	0.242	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
1.030	0.458	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.366	0.336	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
2.465	1.099	tINS	RF	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
5.412	2.947	tNET	FF	8	IOB23[B]	dut/u_tdc/u_IDES8/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk
4.894	2.394	tCL	RR	2	PLL_L	Gowin_PLL/rpll_inst/CLKOUT
5.009	0.115	tNET	RR	1	IOB23[B]	dut/u_tdc/u_IDES8/FCLK
4.979	-0.030	tUnc				dut/u_tdc/u_IDES8
4.934	-0.045	tSu		1	IOB23[B]	dut/u_tdc/u_IDES8

Path Statistics:

Clock Skew	1.937
Setup Relationship	2.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 1.099, 22.705%; route: 3.283, 67.825%; tC2Q: 0.458, 9.469%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.115, 100.000%

Path3

Path Summary:

Slack	0.714
Data Arrival Time	9.814
Data Required Time	10.529
From	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[F]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	1	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK
6.045	0.458	tC2Q	FF	48	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q
9.814	3.769	tNET	FF	1	R25C13[0][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R25C13[0][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
10.529	-0.043	tSu		1	R25C13[0][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	-0.015
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.769, 89.158%; tC2Q: 0.458, 10.842%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path4

Path Summary:

Slack	0.714
Data Arrival Time	9.814
Data Required Time	10.529
From	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[F]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	1	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK
6.045	0.458	tC2Q	FF	48	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q
9.814	3.769	tNET	FF	1	R25C13[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R25C13[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
10.529	-0.043	tSu		1	R25C13[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	-0.015
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.769, 89.158%; tC2Q: 0.458, 10.842%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path5

Path Summary:

Slack	0.714
Data Arrival Time	9.814
Data Required Time	10.529
From	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[F]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	1	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK
6.045	0.458	tC2Q	FF	48	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q
9.814	3.769	tNET	FF	1	R25C13[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R25C13[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
10.529	-0.043	tSu		1	R25C13[2][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	-0.015
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.769, 89.158%; tC2Q: 0.458, 10.842%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path6

Path Summary:

Slack	0.873
Data Arrival Time	9.656
Data Required Time	10.529
From	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[F]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	1	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK
6.045	0.458	tC2Q	FF	48	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q
9.656	3.611	tNET	FF	1	R24C13[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R24C13[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
10.529	-0.043	tSu		1	R24C13[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-0.015
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.611, 88.736%; tC2Q: 0.458, 11.264%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path7

Path Summary:

Slack	1.693
Data Arrival Time	8.836
Data Required Time	10.529
From	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[F]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	1	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK
6.045	0.458	tC2Q	FF	48	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q
8.836	2.791	tNET	FF	1	R25C14[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R25C14[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
10.529	-0.043	tSu		1	R25C14[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	-0.015
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.791, 85.893%; tC2Q: 0.458, 14.107%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path8

Path Summary:

Slack	1.693
Data Arrival Time	8.836
Data Required Time	10.529
From	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[F]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	1	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK
6.045	0.458	tC2Q	FF	48	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q
8.836	2.791	tNET	FF	1	R25C14[1][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R25C14[1][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
10.529	-0.043	tSu		1	R25C14[1][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	-0.015
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.791, 85.893%; tC2Q: 0.458, 14.107%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path9

Path Summary:

Slack	1.693
Data Arrival Time	8.836
Data Required Time	10.529
From	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[F]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	1	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK
6.045	0.458	tC2Q	FF	48	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q
8.836	2.791	tNET	FF	1	R25C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R25C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
10.529	-0.043	tSu		1	R25C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	-0.015
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.791, 85.893%; tC2Q: 0.458, 14.107%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path10

Path Summary:

Slack	1.693
Data Arrival Time	8.836
Data Required Time	10.529
From	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[F]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	1	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK
6.045	0.458	tC2Q	FF	48	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q
8.836	2.791	tNET	FF	1	R24C14[0][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R24C14[0][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
10.529	-0.043	tSu		1	R24C14[0][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	-0.015
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.791, 85.893%; tC2Q: 0.458, 14.107%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path11

Path Summary:

Slack	1.693
Data Arrival Time	8.836
Data Required Time	10.529
From	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[F]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	1	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK
6.045	0.458	tC2Q	FF	48	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q
8.836	2.791	tNET	FF	1	R24C14[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R24C14[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
10.529	-0.043	tSu		1	R24C14[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	-0.015
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.791, 85.893%; tC2Q: 0.458, 14.107%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path12

Path Summary:

Slack	1.694
Data Arrival Time	8.835
Data Required Time	10.529
From	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[F]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	1	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK
6.045	0.458	tC2Q	FF	48	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q
8.835	2.789	tNET	FF	1	R15C6[0][A]	gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R15C6[0][A]	gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
10.529	-0.043	tSu		1	R15C6[0][A]	gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	-0.015
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.789, 85.888%; tC2Q: 0.458, 14.112%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path13

Path Summary:

Slack	2.169
Data Arrival Time	8.360
Data Required Time	10.529
From	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[F]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	1	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK
6.045	0.458	tC2Q	FF	48	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q
8.360	2.315	tNET	FF	1	R17C8[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R17C8[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLK
10.529	-0.043	tSu		1	R17C8[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0

Path Statistics:

Clock Skew	-0.015
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.315, 83.472%; tC2Q: 0.458, 16.528%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path14

Path Summary:

Slack	2.169
Data Arrival Time	8.360
Data Required Time	10.529
From	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[F]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	1	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK
6.045	0.458	tC2Q	FF	48	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q
8.360	2.315	tNET	FF	1	R17C8[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R17C8[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
10.529	-0.043	tSu		1	R17C8[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew	-0.015
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.315, 83.472%; tC2Q: 0.458, 16.528%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path15

Path Summary:

Slack	2.169
Data Arrival Time	8.360
Data Required Time	10.529
From	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[F]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	1	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK
6.045	0.458	tC2Q	FF	48	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q
8.360	2.315	tNET	FF	1	R17C8[0][B]	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R17C8[0][B]	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
10.529	-0.043	tSu		1	R17C8[0][B]	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew	-0.015
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.315, 83.472%; tC2Q: 0.458, 16.528%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path16

Path Summary:

Slack	2.169
Data Arrival Time	8.360
Data Required Time	10.529
From	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[F]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	1	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK
6.045	0.458	tC2Q	FF	48	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q
8.360	2.315	tNET	FF	1	R16C9[1][A]	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R16C9[1][A]	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
10.529	-0.043	tSu		1	R16C9[1][A]	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	-0.015
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.315, 83.472%; tC2Q: 0.458, 16.528%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path17

Path Summary:

Slack	2.169
Data Arrival Time	8.360
Data Required Time	10.529
From	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[F]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	1	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK
6.045	0.458	tC2Q	FF	48	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q
8.360	2.315	tNET	FF	1	R16C9[2][B]	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R16C9[2][B]	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
10.529	-0.043	tSu		1	R16C9[2][B]	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	-0.015
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.315, 83.472%; tC2Q: 0.458, 16.528%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path18

Path Summary:

Slack	2.169
Data Arrival Time	8.360
Data Required Time	10.529
From	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[F]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	1	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK
6.045	0.458	tC2Q	FF	48	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q
8.360	2.315	tNET	FF	1	R16C9[2][A]	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R16C9[2][A]	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
10.529	-0.043	tSu		1	R16C9[2][A]	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	-0.015
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.315, 83.472%; tC2Q: 0.458, 16.528%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path19

Path Summary:

Slack	2.178
Data Arrival Time	8.350
Data Required Time	10.529
From	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[F]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	1	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK
6.045	0.458	tC2Q	FF	48	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q
8.350	2.305	tNET	FF	1	R16C7[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R16C7[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
10.529	-0.043	tSu		1	R16C7[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	-0.015
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.305, 83.413%; tC2Q: 0.458, 16.587%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path20

Path Summary:

Slack	2.178
Data Arrival Time	8.350
Data Required Time	10.529
From	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[F]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	1	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK
6.045	0.458	tC2Q	FF	48	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q
8.350	2.305	tNET	FF	1	R18C7[2][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R18C7[2][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
10.529	-0.043	tSu		1	R18C7[2][B]	gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	-0.015
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.305, 83.413%; tC2Q: 0.458, 16.587%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path21

Path Summary:

Slack	2.178
Data Arrival Time	8.350
Data Required Time	10.529
From	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[F]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	1	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK
6.045	0.458	tC2Q	FF	48	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q
8.350	2.305	tNET	FF	1	R17C7[0][A]	gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R17C7[0][A]	gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
10.529	-0.043	tSu		1	R17C7[0][A]	gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	-0.015
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.305, 83.413%; tC2Q: 0.458, 16.587%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path22

Path Summary:

Slack	2.182
Data Arrival Time	8.347
Data Required Time	10.529
From	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[F]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	1	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK
6.045	0.458	tC2Q	FF	48	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q
8.347	2.302	tNET	FF	1	R23C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R23C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
10.529	-0.043	tSu		1	R23C14[1][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-0.015
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.302, 83.393%; tC2Q: 0.458, 16.607%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path23

Path Summary:

Slack	2.182
Data Arrival Time	8.347
Data Required Time	10.529
From	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_gvio_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[F]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	1	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK
6.045	0.458	tC2Q	FF	48	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q
8.347	2.302	tNET	FF	1	R23C14[0][A]	gw_gao_gvio_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R23C14[0][A]	gw_gao_gvio_inst_0/u_la0_top/capture_end_dly_s0/CLK
10.529	-0.043	tSu		1	R23C14[0][A]	gw_gao_gvio_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew	-0.015
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.302, 83.393%; tC2Q: 0.458, 16.607%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path24

Path Summary:

Slack	2.349
Data Arrival Time	8.180
Data Required Time	10.529
From	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[F]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	1	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK
6.045	0.458	tC2Q	FF	48	R16C15[0][A]	gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q
8.180	2.134	tNET	FF	1	R21C13[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	R21C13[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
10.529	-0.043	tSu		1	R21C13[0][A]	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-0.015
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.257, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.134, 82.321%; tC2Q: 0.458, 17.679%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path25

Path Summary:

Slack	5.115
Data Arrival Time	5.412
Data Required Time	10.527
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/u_IDES8
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.572	0.242	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
1.030	0.458	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.366	0.336	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
2.465	1.099	tINS	RF	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
5.412	2.947	tNET	FF	8	IOB23[B]	dut/u_tdc/u_IDES8/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
10.572	0.242	tNET	RR	1	IOB23[B]	dut/u_tdc/u_IDES8/PCLK
10.527	-0.045	tSu		1	IOB23[B]	dut/u_tdc/u_IDES8

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 1.099, 22.705%; route: 3.283, 67.825%; tC2Q: 0.458, 9.469%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.113
Data Arrival Time	3.634
Data Required Time	2.521
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/u_IDES8
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	8	IOB23[B]	dut/u_tdc/u_IDES8/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk
2.394	2.394	tCL	RR	2	PLL_L	Gowin_PLL/rpll_inst/CLKOUT
2.478	0.085	tNET	RR	1	IOB23[B]	dut/u_tdc/u_IDES8/FCLK
2.508	0.030	tUnc				dut/u_tdc/u_IDES8
2.521	0.012	tHld		1	IOB23[B]	dut/u_tdc/u_IDES8

Path Statistics:

Clock Skew	1.965
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.085, 100.000%

Path2

Path Summary:

Slack	2.357
Data Arrival Time	3.634
Data Required Time	1.277
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/u_IDES8
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	8	IOB23[B]	dut/u_tdc/u_IDES8/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-1.250	-1.250					active clock edge time
-1.250	0.000					Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk
1.144	2.394	tCL	FF	2	PLL_L	Gowin_PLL/rpll_inst/CLKOUT
1.234	0.090	tNET	FF	1	IOB23[B]	dut/u_tdc/u_IDES8/FCLK
1.264	0.030	tUnc				dut/u_tdc/u_IDES8
1.277	0.012	tHld		1	IOB23[B]	dut/u_tdc/u_IDES8

Path Statistics:

Clock Skew	1.971
Hold Relationship	-1.250
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.090, 100.000%

Path3

Path Summary:

Slack	3.109
Data Arrival Time	3.634
Data Required Time	0.526
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/u_IDES8
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	8	IOB23[B]	dut/u_tdc/u_IDES8/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	IOB23[B]	dut/u_tdc/u_IDES8/PCLK
0.526	0.012	tHld		1	IOB23[B]	dut/u_tdc/u_IDES8

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path4

Path Summary:

Slack	3.109
Data Arrival Time	3.634
Data Required Time	0.526
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/count_tmp_0_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	1	R22C22[0][A]	dut/u_tdc/count_tmp_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C22[0][A]	dut/u_tdc/count_tmp_0_s1/CLK
0.526	0.012	tHld		1	R22C22[0][A]	dut/u_tdc/count_tmp_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path5

Path Summary:

Slack	3.109
Data Arrival Time	3.634
Data Required Time	0.526
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/count_tmp_1_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	1	R18C22[2][B]	dut/u_tdc/count_tmp_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R18C22[2][B]	dut/u_tdc/count_tmp_1_s1/CLK
0.526	0.012	tHld		1	R18C22[2][B]	dut/u_tdc/count_tmp_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path6

Path Summary:

Slack	3.109
Data Arrival Time	3.634
Data Required Time	0.526
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/count_tmp_2_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	1	R17C23[0][B]	dut/u_tdc/count_tmp_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R17C23[0][B]	dut/u_tdc/count_tmp_2_s1/CLK
0.526	0.012	tHld		1	R17C23[0][B]	dut/u_tdc/count_tmp_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path7

Path Summary:

Slack	3.109
Data Arrival Time	3.634
Data Required Time	0.526
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/count_tmp_3_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	1	R17C23[1][A]	dut/u_tdc/count_tmp_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R17C23[1][A]	dut/u_tdc/count_tmp_3_s1/CLK
0.526	0.012	tHld		1	R17C23[1][A]	dut/u_tdc/count_tmp_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path8

Path Summary:

Slack	3.109
Data Arrival Time	3.634
Data Required Time	0.526
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/count_tmp_4_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	1	R18C23[0][A]	dut/u_tdc/count_tmp_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R18C23[0][A]	dut/u_tdc/count_tmp_4_s1/CLK
0.526	0.012	tHld		1	R18C23[0][A]	dut/u_tdc/count_tmp_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path9

Path Summary:

Slack	3.109
Data Arrival Time	3.634
Data Required Time	0.526
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/count_tmp_5_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	1	R18C23[1][B]	dut/u_tdc/count_tmp_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R18C23[1][B]	dut/u_tdc/count_tmp_5_s1/CLK
0.526	0.012	tHld		1	R18C23[1][B]	dut/u_tdc/count_tmp_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path10

Path Summary:

Slack	3.109
Data Arrival Time	3.634
Data Required Time	0.526
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/count_tmp_6_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	1	R17C22[0][B]	dut/u_tdc/count_tmp_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R17C22[0][B]	dut/u_tdc/count_tmp_6_s1/CLK
0.526	0.012	tHld		1	R17C22[0][B]	dut/u_tdc/count_tmp_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path11

Path Summary:

Slack	3.109
Data Arrival Time	3.634
Data Required Time	0.526
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/count_tmp_7_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	1	R16C22[0][B]	dut/u_tdc/count_tmp_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R16C22[0][B]	dut/u_tdc/count_tmp_7_s1/CLK
0.526	0.012	tHld		1	R16C22[0][B]	dut/u_tdc/count_tmp_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path12

Path Summary:

Slack	3.109
Data Arrival Time	3.634
Data Required Time	0.526
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/count_tmp_8_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	1	R16C22[1][A]	dut/u_tdc/count_tmp_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R16C22[1][A]	dut/u_tdc/count_tmp_8_s1/CLK
0.526	0.012	tHld		1	R16C22[1][A]	dut/u_tdc/count_tmp_8_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path13

Path Summary:

Slack	3.109
Data Arrival Time	3.634
Data Required Time	0.526
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/count_tmp_9_s1
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	1	R16C23[1][A]	dut/u_tdc/count_tmp_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R16C23[1][A]	dut/u_tdc/count_tmp_9_s1/CLK
0.526	0.012	tHld		1	R16C23[1][A]	dut/u_tdc/count_tmp_9_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path14

Path Summary:

Slack	3.109
Data Arrival Time	3.634
Data Required Time	0.526
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/start_d1_s0
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	1	R20C23[0][A]	dut/u_tdc/start_d1_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R20C23[0][A]	dut/u_tdc/start_d1_s0/CLK
0.526	0.012	tHld		1	R20C23[0][A]	dut/u_tdc/start_d1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path15

Path Summary:

Slack	3.109
Data Arrival Time	3.634
Data Required Time	0.526
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/start_d0_s0
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	1	R17C22[1][A]	dut/u_tdc/start_d0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R17C22[1][A]	dut/u_tdc/start_d0_s0/CLK
0.526	0.012	tHld		1	R17C22[1][A]	dut/u_tdc/start_d0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path16

Path Summary:

Slack	3.109
Data Arrival Time	3.634
Data Required Time	0.526
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/c_state_0_s0
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	1	R22C23[0][B]	dut/u_tdc/c_state_0_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C23[0][B]	dut/u_tdc/c_state_0_s0/CLK
0.526	0.012	tHld		1	R22C23[0][B]	dut/u_tdc/c_state_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path17

Path Summary:

Slack	3.109
Data Arrival Time	3.634
Data Required Time	0.526
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/c_state_1_s0
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	1	R25C23[2][A]	dut/u_tdc/c_state_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R25C23[2][A]	dut/u_tdc/c_state_1_s0/CLK
0.526	0.012	tHld		1	R25C23[2][A]	dut/u_tdc/c_state_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path18

Path Summary:

Slack	3.109
Data Arrival Time	3.634
Data Required Time	0.526
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/c_state_2_s0
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	1	R23C23[2][A]	dut/u_tdc/c_state_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R23C23[2][A]	dut/u_tdc/c_state_2_s0/CLK
0.526	0.012	tHld		1	R23C23[2][A]	dut/u_tdc/c_state_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path19

Path Summary:

Slack	3.109
Data Arrival Time	3.634
Data Required Time	0.526
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/c_state_3_s0
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	1	R25C23[0][A]	dut/u_tdc/c_state_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R25C23[0][A]	dut/u_tdc/c_state_3_s0/CLK
0.526	0.012	tHld		1	R25C23[0][A]	dut/u_tdc/c_state_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path20

Path Summary:

Slack	3.109
Data Arrival Time	3.634
Data Required Time	0.526
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/q_d_0_s0
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	1	R22C22[1][B]	dut/u_tdc/q_d_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C22[1][B]	dut/u_tdc/q_d_0_s0/CLK
0.526	0.012	tHld		1	R22C22[1][B]	dut/u_tdc/q_d_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path21

Path Summary:

Slack	3.109
Data Arrival Time	3.634
Data Required Time	0.526
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/q_d_1_s0
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	1	R23C22[0][B]	dut/u_tdc/q_d_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R23C22[0][B]	dut/u_tdc/q_d_1_s0/CLK
0.526	0.012	tHld		1	R23C22[0][B]	dut/u_tdc/q_d_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path22

Path Summary:

Slack	3.109
Data Arrival Time	3.634
Data Required Time	0.526
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/q_d_2_s0
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	1	R22C22[1][A]	dut/u_tdc/q_d_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C22[1][A]	dut/u_tdc/q_d_2_s0/CLK
0.526	0.012	tHld		1	R22C22[1][A]	dut/u_tdc/q_d_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path23

Path Summary:

Slack	3.109
Data Arrival Time	3.634
Data Required Time	0.526
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/q_d_3_s0
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	1	R23C22[1][A]	dut/u_tdc/q_d_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R23C22[1][A]	dut/u_tdc/q_d_3_s0/CLK
0.526	0.012	tHld		1	R23C22[1][A]	dut/u_tdc/q_d_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path24

Path Summary:

Slack	3.109
Data Arrival Time	3.634
Data Required Time	0.526
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/q_d_4_s0
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	1	R23C22[0][A]	dut/u_tdc/q_d_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R23C22[0][A]	dut/u_tdc/q_d_4_s0/CLK
0.526	0.012	tHld		1	R23C22[0][A]	dut/u_tdc/q_d_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path25

Path Summary:

Slack	3.109
Data Arrival Time	3.634
Data Required Time	0.526
From	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0
To	dut/u_tdc/q_d_5_s0
Launch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]
Latch Clk	u_CLKDIV/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R22C21[1][A]	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg2_0_s0/Q
1.083	0.236	tNET	RR	1	R22C21[3][A]	dut/u_tdc/n16_s1/I0
1.807	0.724	tINS	RR	25	R22C21[3][A]	dut/u_tdc/n16_s1/F
3.634	1.827	tNET	RR	1	R23C23[1][B]	dut/u_tdc/q_d_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_CLKDIV/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	120	BOTTOMSIDE[0]	u_CLKDIV/CLKOUT
0.513	0.183	tNET	RR	1	R23C23[1][B]	dut/u_tdc/q_d_5_s0/CLK
0.526	0.012	tHld		1	R23C23[1][B]	dut/u_tdc/q_d_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 23.197%; route: 2.064, 66.123%; tC2Q: 0.333, 10.680%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.676
Actual Width:	4.926
Required Width:	1.250
Type:	Low Pulse Width
Clock:	u_CLKDIV/CLKOUT.default_gen_clk
Objects:	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg1_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg1_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	u_CLKDIV/CLKOUT
10.513	0.183	tNET	RR	gw_gao_gvio_inst_0/u_gvio0_top/probe_out0_reg1_0_s0/CLK

MPW2

MPW Summary:

Slack:	3.676
Actual Width:	4.926
Required Width:	1.250
Type:	Low Pulse Width
Clock:	u_CLKDIV/CLKOUT.default_gen_clk
Objects:	gw_gao_gvio_inst_0/u_gvio0_top/probe_out1_reg1_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	gw_gao_gvio_inst_0/u_gvio0_top/probe_out1_reg1_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	u_CLKDIV/CLKOUT
10.513	0.183	tNET	RR	gw_gao_gvio_inst_0/u_gvio0_top/probe_out1_reg1_0_s0/CLK

MPW3

MPW Summary:

Slack:	3.676
Actual Width:	4.926
Required Width:	1.250
Type:	Low Pulse Width
Clock:	u_CLKDIV/CLKOUT.default_gen_clk
Objects:	gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	u_CLKDIV/CLKOUT
10.513	0.183	tNET	RR	gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK

MPW4

MPW Summary:

Slack:	3.676
Actual Width:	4.926
Required Width:	1.250
Type:	Low Pulse Width
Clock:	u_CLKDIV/CLKOUT.default_gen_clk
Objects:	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	u_CLKDIV/CLKOUT
10.513	0.183	tNET	RR	gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK

MPW5

MPW Summary:

Slack:	3.676
Actual Width:	4.926
Required Width:	1.250
Type:	Low Pulse Width
Clock:	u_CLKDIV/CLKOUT.default_gen_clk
Objects:	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_6_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_6_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	u_CLKDIV/CLKOUT
10.513	0.183	tNET	RR	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_6_s0/CLK

MPW6

MPW Summary:

Slack:	3.676
Actual Width:	4.926
Required Width:	1.250
Type:	Low Pulse Width
Clock:	u_CLKDIV/CLKOUT.default_gen_clk
Objects:	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	u_CLKDIV/CLKOUT
10.513	0.183	tNET	RR	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK

MPW7

MPW Summary:

Slack:	3.676
Actual Width:	4.926
Required Width:	1.250
Type:	Low Pulse Width
Clock:	u_CLKDIV/CLKOUT.default_gen_clk
Objects:	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	u_CLKDIV/CLKOUT
10.513	0.183	tNET	RR	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK

MPW8

MPW Summary:

Slack:	3.676
Actual Width:	4.926
Required Width:	1.250
Type:	Low Pulse Width
Clock:	u_CLKDIV/CLKOUT.default_gen_clk
Objects:	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_7_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_7_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	u_CLKDIV/CLKOUT
10.513	0.183	tNET	RR	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_7_s0/CLK

MPW9

MPW Summary:

Slack:	3.676
Actual Width:	4.926
Required Width:	1.250
Type:	Low Pulse Width
Clock:	u_CLKDIV/CLKOUT.default_gen_clk
Objects:	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	u_CLKDIV/CLKOUT
10.513	0.183	tNET	RR	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK

MPW10

MPW Summary:

Slack:	3.676
Actual Width:	4.926
Required Width:	1.250
Type:	Low Pulse Width
Clock:	u_CLKDIV/CLKOUT.default_gen_clk
Objects:	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			u_CLKDIV/CLKOUT.default_gen_clk
5.330	0.330	tCL	FF	u_CLKDIV/CLKOUT
5.587	0.257	tNET	FF	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			u_CLKDIV/CLKOUT.default_gen_clk
10.330	0.330	tCL	RR	u_CLKDIV/CLKOUT
10.513	0.183	tNET	RR	gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
304	gw_gao_gvio_inst_0/gao_control0[0]	-2.662	1.726
120	pclk_d	-1.722	0.659
48	gw_gao_gvio_inst_0/u_la0_top/rst_ao	0.714	3.769
38	gw_gao_gvio_inst_0/u_la0_top/op_reg_en	40.457	1.828
37	gw_gao_gvio_inst_0/u_gvio0_top/n16_3	43.995	1.826
37	gw_gao_gvio_inst_0/u_la0_top/n20_3	43.895	1.525
32	gw_gao_gvio_inst_0/u_la0_top/u_ao_crc32/crc_28_7	40.056	1.801
30	gw_gao_gvio_inst_0/u_la0_top/n594_18	39.909	1.841
25	dut/u_tdc/n16_5	-1.722	2.947
24	gw_gao_gvio_inst_0/u_gvio0_top/bit_ct_rst	41.095	1.687

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C3	100.00%
R2C5	100.00%
R2C7	100.00%
R2C8	100.00%
R2C24	100.00%
R3C10	100.00%
R4C28	100.00%
R7C21	100.00%
R13C39	100.00%
R25C33	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command