Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\work\work\Confidential_IP\code\TDC\Gowin_TDC_RefDesign\project\src\gowin_rpll\gowin_rpll.v
E:\work\work\Confidential_IP\code\TDC\Gowin_TDC_RefDesign\project\src\tdc\tdc.v
E:\work\work\Confidential_IP\code\TDC\Gowin_TDC_RefDesign\project\src\top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\gw_jtag.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GVIO\GW_GVIO_0\gw_gvio_ao_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GVIO\GW_GVIO_CON\gw_gvio_con_top.v
E:\work\work\Confidential_IP\code\TDC\Gowin_TDC_RefDesign\project\impl\gwsynthesis\GVIO\gw_gao_gvio_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW1N-LV9QN88C6/I5
Device GW1N-9
Device Version C
Created Time Mon Jul 14 10:07:10 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.262s, Peak memory usage = 183.996MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 183.996MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 183.996MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 183.996MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 183.996MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 183.996MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 183.996MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 183.996MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 183.996MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 183.996MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 183.996MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 213.496MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.071s, Peak memory usage = 213.496MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 213.496MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 213.496MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 20
I/O Buf 20
    IBUF 6
    OBUF 14
Register 420
    DFF 47
    DFFE 18
    DFFR 1
    DFFRE 2
    DFFP 5
    DFFPE 33
    DFFC 44
    DFFCE 270
LUT 529
    LUT2 92
    LUT3 126
    LUT4 311
MUX 3
    MUX2 1
    MUX16 2
ALU 11
    ALU 11
INV 4
    INV 4
IOLOGIC 1
    IDES8 1
BSRAM 1
    SDPB 1
CLOCK 2
    CLKDIV 1
    rPLL 1
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 561(550 LUT, 11 ALU) / 8640 7%
Register 420 / 6693 7%
  --Register as Latch 0 / 6693 0%
  --Register as FF 420 / 6693 7%
BSRAM 1 / 26 4%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 20.000 50.000 0.000 10.000 clk_ibuf/I
2 Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk Generated 2.500 400.000 0.000 1.250 clk_ibuf/I clk Gowin_PLL/rpll_inst/CLKOUT
3 Gowin_PLL/rpll_inst/CLKOUTP.default_gen_clk Generated 2.500 400.000 0.000 1.250 clk_ibuf/I clk Gowin_PLL/rpll_inst/CLKOUTP
4 Gowin_PLL/rpll_inst/CLKOUTD.default_gen_clk Generated 5.000 200.000 0.000 2.500 clk_ibuf/I clk Gowin_PLL/rpll_inst/CLKOUTD
5 Gowin_PLL/rpll_inst/CLKOUTD3.default_gen_clk Generated 7.500 133.333 0.000 3.750 clk_ibuf/I clk Gowin_PLL/rpll_inst/CLKOUTD3
6 u_CLKDIV/CLKOUT.default_gen_clk Generated 10.000 100.000 0.000 5.000 Gowin_PLL/rpll_inst/CLKOUT Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk u_CLKDIV/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 u_CLKDIV/CLKOUT.default_gen_clk 100.000(MHz) 83.013(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -2.046
Data Arrival Time 13.099
Data Required Time 11.053
From dut/u_tdc/q_d_0_s0
To dut/u_tdc/count_tmp_5_s1
Launch Clk u_CLKDIV/CLKOUT.default_gen_clk[R]
Latch Clk u_CLKDIV/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_CLKDIV/CLKOUT.default_gen_clk
0.727 0.727 tCL RR 120 u_CLKDIV/CLKOUT
1.453 0.726 tNET RR 1 dut/u_tdc/q_d_0_s0/CLK
1.911 0.458 tC2Q RF 2 dut/u_tdc/q_d_0_s0/Q
2.871 0.960 tNET FF 1 dut/u_tdc/n176_s4/I1
3.970 1.099 tINS FF 3 dut/u_tdc/n176_s4/F
4.930 0.960 tNET FF 1 dut/u_tdc/n175_s6/I1
6.029 1.099 tINS FF 5 dut/u_tdc/n175_s6/F
6.989 0.960 tNET FF 1 dut/u_tdc/n174_s3/I1
8.088 1.099 tINS FF 4 dut/u_tdc/n174_s3/F
9.048 0.960 tNET FF 1 dut/u_tdc/n172_s4/I0
10.080 1.032 tINS FF 2 dut/u_tdc/n172_s4/F
11.040 0.960 tNET FF 1 dut/u_tdc/n171_s2/I1
12.139 1.099 tINS FF 1 dut/u_tdc/n171_s2/F
13.099 0.960 tNET FF 1 dut/u_tdc/count_tmp_5_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 u_CLKDIV/CLKOUT.default_gen_clk
10.727 0.727 tCL RR 120 u_CLKDIV/CLKOUT
11.453 0.726 tNET RR 1 dut/u_tdc/count_tmp_5_s1/CLK
11.053 -0.400 tSu 1 dut/u_tdc/count_tmp_5_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 5.428, 46.607%; route: 5.760, 49.458%; tC2Q: 0.458, 3.935%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 2

Path Summary:
Slack -2.046
Data Arrival Time 13.099
Data Required Time 11.053
From dut/u_tdc/q_d_0_s0
To dut/u_tdc/count_tmp_6_s1
Launch Clk u_CLKDIV/CLKOUT.default_gen_clk[R]
Latch Clk u_CLKDIV/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_CLKDIV/CLKOUT.default_gen_clk
0.727 0.727 tCL RR 120 u_CLKDIV/CLKOUT
1.453 0.726 tNET RR 1 dut/u_tdc/q_d_0_s0/CLK
1.911 0.458 tC2Q RF 2 dut/u_tdc/q_d_0_s0/Q
2.871 0.960 tNET FF 1 dut/u_tdc/n176_s4/I1
3.970 1.099 tINS FF 3 dut/u_tdc/n176_s4/F
4.930 0.960 tNET FF 1 dut/u_tdc/n175_s6/I1
6.029 1.099 tINS FF 5 dut/u_tdc/n175_s6/F
6.989 0.960 tNET FF 1 dut/u_tdc/n174_s3/I1
8.088 1.099 tINS FF 4 dut/u_tdc/n174_s3/F
9.048 0.960 tNET FF 1 dut/u_tdc/n170_s3/I0
10.080 1.032 tINS FF 4 dut/u_tdc/n170_s3/F
11.040 0.960 tNET FF 1 dut/u_tdc/n170_s10/I1
12.139 1.099 tINS FF 1 dut/u_tdc/n170_s10/F
13.099 0.960 tNET FF 1 dut/u_tdc/count_tmp_6_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 u_CLKDIV/CLKOUT.default_gen_clk
10.727 0.727 tCL RR 120 u_CLKDIV/CLKOUT
11.453 0.726 tNET RR 1 dut/u_tdc/count_tmp_6_s1/CLK
11.053 -0.400 tSu 1 dut/u_tdc/count_tmp_6_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 5.428, 46.607%; route: 5.760, 49.458%; tC2Q: 0.458, 3.935%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 3

Path Summary:
Slack -1.979
Data Arrival Time 13.032
Data Required Time 11.053
From dut/u_tdc/q_d_0_s0
To dut/u_tdc/count_tmp_7_s1
Launch Clk u_CLKDIV/CLKOUT.default_gen_clk[R]
Latch Clk u_CLKDIV/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_CLKDIV/CLKOUT.default_gen_clk
0.727 0.727 tCL RR 120 u_CLKDIV/CLKOUT
1.453 0.726 tNET RR 1 dut/u_tdc/q_d_0_s0/CLK
1.911 0.458 tC2Q RF 2 dut/u_tdc/q_d_0_s0/Q
2.871 0.960 tNET FF 1 dut/u_tdc/n176_s4/I1
3.970 1.099 tINS FF 3 dut/u_tdc/n176_s4/F
4.930 0.960 tNET FF 1 dut/u_tdc/n175_s6/I1
6.029 1.099 tINS FF 5 dut/u_tdc/n175_s6/F
6.989 0.960 tNET FF 1 dut/u_tdc/n170_s6/I0
8.021 1.032 tINS FF 5 dut/u_tdc/n170_s6/F
8.981 0.960 tNET FF 1 dut/u_tdc/n170_s4/I0
10.013 1.032 tINS FF 1 dut/u_tdc/n170_s4/F
10.973 0.960 tNET FF 1 dut/u_tdc/n169_s2/I1
12.072 1.099 tINS FF 1 dut/u_tdc/n169_s2/F
13.032 0.960 tNET FF 1 dut/u_tdc/count_tmp_7_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 u_CLKDIV/CLKOUT.default_gen_clk
10.727 0.727 tCL RR 120 u_CLKDIV/CLKOUT
11.453 0.726 tNET RR 1 dut/u_tdc/count_tmp_7_s1/CLK
11.053 -0.400 tSu 1 dut/u_tdc/count_tmp_7_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 5.361, 46.298%; route: 5.760, 49.744%; tC2Q: 0.458, 3.958%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 4

Path Summary:
Slack -1.979
Data Arrival Time 13.032
Data Required Time 11.053
From dut/u_tdc/q_d_0_s0
To dut/u_tdc/count_tmp_8_s1
Launch Clk u_CLKDIV/CLKOUT.default_gen_clk[R]
Latch Clk u_CLKDIV/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_CLKDIV/CLKOUT.default_gen_clk
0.727 0.727 tCL RR 120 u_CLKDIV/CLKOUT
1.453 0.726 tNET RR 1 dut/u_tdc/q_d_0_s0/CLK
1.911 0.458 tC2Q RF 2 dut/u_tdc/q_d_0_s0/Q
2.871 0.960 tNET FF 1 dut/u_tdc/n176_s4/I1
3.970 1.099 tINS FF 3 dut/u_tdc/n176_s4/F
4.930 0.960 tNET FF 1 dut/u_tdc/n175_s6/I1
6.029 1.099 tINS FF 5 dut/u_tdc/n175_s6/F
6.989 0.960 tNET FF 1 dut/u_tdc/n174_s3/I1
8.088 1.099 tINS FF 4 dut/u_tdc/n174_s3/F
9.048 0.960 tNET FF 1 dut/u_tdc/n170_s3/I0
10.080 1.032 tINS FF 4 dut/u_tdc/n170_s3/F
11.040 0.960 tNET FF 1 dut/u_tdc/n168_s2/I0
12.072 1.032 tINS FF 1 dut/u_tdc/n168_s2/F
13.032 0.960 tNET FF 1 dut/u_tdc/count_tmp_8_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 u_CLKDIV/CLKOUT.default_gen_clk
10.727 0.727 tCL RR 120 u_CLKDIV/CLKOUT
11.453 0.726 tNET RR 1 dut/u_tdc/count_tmp_8_s1/CLK
11.053 -0.400 tSu 1 dut/u_tdc/count_tmp_8_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 5.361, 46.298%; route: 5.760, 49.744%; tC2Q: 0.458, 3.958%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 5

Path Summary:
Slack -1.979
Data Arrival Time 13.032
Data Required Time 11.053
From dut/u_tdc/q_d_0_s0
To dut/u_tdc/count_tmp_9_s1
Launch Clk u_CLKDIV/CLKOUT.default_gen_clk[R]
Latch Clk u_CLKDIV/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_CLKDIV/CLKOUT.default_gen_clk
0.727 0.727 tCL RR 120 u_CLKDIV/CLKOUT
1.453 0.726 tNET RR 1 dut/u_tdc/q_d_0_s0/CLK
1.911 0.458 tC2Q RF 2 dut/u_tdc/q_d_0_s0/Q
2.871 0.960 tNET FF 1 dut/u_tdc/n176_s4/I1
3.970 1.099 tINS FF 3 dut/u_tdc/n176_s4/F
4.930 0.960 tNET FF 1 dut/u_tdc/n175_s6/I1
6.029 1.099 tINS FF 5 dut/u_tdc/n175_s6/F
6.989 0.960 tNET FF 1 dut/u_tdc/n174_s3/I1
8.088 1.099 tINS FF 4 dut/u_tdc/n174_s3/F
9.048 0.960 tNET FF 1 dut/u_tdc/n170_s3/I0
10.080 1.032 tINS FF 4 dut/u_tdc/n170_s3/F
11.040 0.960 tNET FF 1 dut/u_tdc/n167_s2/I0
12.072 1.032 tINS FF 1 dut/u_tdc/n167_s2/F
13.032 0.960 tNET FF 1 dut/u_tdc/count_tmp_9_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 u_CLKDIV/CLKOUT.default_gen_clk
10.727 0.727 tCL RR 120 u_CLKDIV/CLKOUT
11.453 0.726 tNET RR 1 dut/u_tdc/count_tmp_9_s1/CLK
11.053 -0.400 tSu 1 dut/u_tdc/count_tmp_9_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 5.361, 46.298%; route: 5.760, 49.744%; tC2Q: 0.458, 3.958%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%