Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\AHB2APB_SyncDown\data\ahb_to_apb_sync_down_top.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\AHB2APB_SyncDown\data\ahb_to_apb_sync_down.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.01 (64-bit)
Part Number GW5AST-LV138FPG676AC1/I0
Device GW5AST-138
Device Version B
Created Time Wed Feb 26 11:20:38 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module AHB_to_APB_Sync_Down_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.214s, Peak memory usage = 107.102MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 107.102MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 107.102MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 107.102MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 107.102MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 107.102MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 107.102MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 107.102MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 107.102MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 107.102MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 107.102MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 107.102MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.235s, Peak memory usage = 128.480MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 128.480MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 128.480MB
Total Time and Memory Usage CPU time = 0h 0m 0.358s, Elapsed time = 0h 0m 0.49s, Peak memory usage = 128.480MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 190
I/O Buf 186
    IBUF 93
    OBUF 93
Register 57
    DFFCE 57
LUT 57
    LUT2 4
    LUT3 8
    LUT4 45
INV 2
    INV 2

Resource Utilization Summary

Resource Usage Utilization
Logic 59(59 LUT, 0 ALU) / 138240 <1%
Register 57 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 57 / 139140 <1%
BSRAM 0 / 340 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 HCLK Base 10.000 100.000 0.000 5.000 HCLK_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 HCLK 100.000(MHz) 268.908(MHz) 4 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 6.281
Data Arrival Time 3.820
Data Required Time 10.101
From u_ahb_to_apb_sync_down/state_reg_2_s0
To u_ahb_to_apb_sync_down/rwdata_reg_0_s1
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.000 0.000 tINS RR 57 HCLK_ibuf/O
0.413 0.413 tNET RR 1 u_ahb_to_apb_sync_down/state_reg_2_s0/CLK
0.795 0.382 tC2Q RR 8 u_ahb_to_apb_sync_down/state_reg_2_s0/Q
1.207 0.413 tNET RR 1 u_ahb_to_apb_sync_down/PSEL_d_s/I0
1.786 0.579 tINS RR 3 u_ahb_to_apb_sync_down/PSEL_d_s/F
2.199 0.413 tNET RR 1 u_ahb_to_apb_sync_down/next_state_1_s14/I3
2.487 0.289 tINS RR 3 u_ahb_to_apb_sync_down/next_state_1_s14/F
2.900 0.413 tNET RR 1 u_ahb_to_apb_sync_down/rwdata_reg_31_s4/I2
3.408 0.507 tINS RR 32 u_ahb_to_apb_sync_down/rwdata_reg_31_s4/F
3.820 0.413 tNET RR 1 u_ahb_to_apb_sync_down/rwdata_reg_0_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.000 0.000 tINS RR 57 HCLK_ibuf/O
10.413 0.413 tNET RR 1 u_ahb_to_apb_sync_down/rwdata_reg_0_s1/CLK
10.101 -0.311 tSu 1 u_ahb_to_apb_sync_down/rwdata_reg_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 1.375, 40.352%; route: 1.650, 48.423%; tC2Q: 0.382, 11.225%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack 6.281
Data Arrival Time 3.820
Data Required Time 10.101
From u_ahb_to_apb_sync_down/state_reg_2_s0
To u_ahb_to_apb_sync_down/rwdata_reg_1_s1
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.000 0.000 tINS RR 57 HCLK_ibuf/O
0.413 0.413 tNET RR 1 u_ahb_to_apb_sync_down/state_reg_2_s0/CLK
0.795 0.382 tC2Q RR 8 u_ahb_to_apb_sync_down/state_reg_2_s0/Q
1.207 0.413 tNET RR 1 u_ahb_to_apb_sync_down/PSEL_d_s/I0
1.786 0.579 tINS RR 3 u_ahb_to_apb_sync_down/PSEL_d_s/F
2.199 0.413 tNET RR 1 u_ahb_to_apb_sync_down/next_state_1_s14/I3
2.487 0.289 tINS RR 3 u_ahb_to_apb_sync_down/next_state_1_s14/F
2.900 0.413 tNET RR 1 u_ahb_to_apb_sync_down/rwdata_reg_31_s4/I2
3.408 0.507 tINS RR 32 u_ahb_to_apb_sync_down/rwdata_reg_31_s4/F
3.820 0.413 tNET RR 1 u_ahb_to_apb_sync_down/rwdata_reg_1_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.000 0.000 tINS RR 57 HCLK_ibuf/O
10.413 0.413 tNET RR 1 u_ahb_to_apb_sync_down/rwdata_reg_1_s1/CLK
10.101 -0.311 tSu 1 u_ahb_to_apb_sync_down/rwdata_reg_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 1.375, 40.352%; route: 1.650, 48.423%; tC2Q: 0.382, 11.225%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack 6.281
Data Arrival Time 3.820
Data Required Time 10.101
From u_ahb_to_apb_sync_down/state_reg_2_s0
To u_ahb_to_apb_sync_down/rwdata_reg_2_s1
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.000 0.000 tINS RR 57 HCLK_ibuf/O
0.413 0.413 tNET RR 1 u_ahb_to_apb_sync_down/state_reg_2_s0/CLK
0.795 0.382 tC2Q RR 8 u_ahb_to_apb_sync_down/state_reg_2_s0/Q
1.207 0.413 tNET RR 1 u_ahb_to_apb_sync_down/PSEL_d_s/I0
1.786 0.579 tINS RR 3 u_ahb_to_apb_sync_down/PSEL_d_s/F
2.199 0.413 tNET RR 1 u_ahb_to_apb_sync_down/next_state_1_s14/I3
2.487 0.289 tINS RR 3 u_ahb_to_apb_sync_down/next_state_1_s14/F
2.900 0.413 tNET RR 1 u_ahb_to_apb_sync_down/rwdata_reg_31_s4/I2
3.408 0.507 tINS RR 32 u_ahb_to_apb_sync_down/rwdata_reg_31_s4/F
3.820 0.413 tNET RR 1 u_ahb_to_apb_sync_down/rwdata_reg_2_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.000 0.000 tINS RR 57 HCLK_ibuf/O
10.413 0.413 tNET RR 1 u_ahb_to_apb_sync_down/rwdata_reg_2_s1/CLK
10.101 -0.311 tSu 1 u_ahb_to_apb_sync_down/rwdata_reg_2_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 1.375, 40.352%; route: 1.650, 48.423%; tC2Q: 0.382, 11.225%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack 6.281
Data Arrival Time 3.820
Data Required Time 10.101
From u_ahb_to_apb_sync_down/state_reg_2_s0
To u_ahb_to_apb_sync_down/rwdata_reg_3_s1
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.000 0.000 tINS RR 57 HCLK_ibuf/O
0.413 0.413 tNET RR 1 u_ahb_to_apb_sync_down/state_reg_2_s0/CLK
0.795 0.382 tC2Q RR 8 u_ahb_to_apb_sync_down/state_reg_2_s0/Q
1.207 0.413 tNET RR 1 u_ahb_to_apb_sync_down/PSEL_d_s/I0
1.786 0.579 tINS RR 3 u_ahb_to_apb_sync_down/PSEL_d_s/F
2.199 0.413 tNET RR 1 u_ahb_to_apb_sync_down/next_state_1_s14/I3
2.487 0.289 tINS RR 3 u_ahb_to_apb_sync_down/next_state_1_s14/F
2.900 0.413 tNET RR 1 u_ahb_to_apb_sync_down/rwdata_reg_31_s4/I2
3.408 0.507 tINS RR 32 u_ahb_to_apb_sync_down/rwdata_reg_31_s4/F
3.820 0.413 tNET RR 1 u_ahb_to_apb_sync_down/rwdata_reg_3_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.000 0.000 tINS RR 57 HCLK_ibuf/O
10.413 0.413 tNET RR 1 u_ahb_to_apb_sync_down/rwdata_reg_3_s1/CLK
10.101 -0.311 tSu 1 u_ahb_to_apb_sync_down/rwdata_reg_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 1.375, 40.352%; route: 1.650, 48.423%; tC2Q: 0.382, 11.225%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack 6.281
Data Arrival Time 3.820
Data Required Time 10.101
From u_ahb_to_apb_sync_down/state_reg_2_s0
To u_ahb_to_apb_sync_down/rwdata_reg_4_s1
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.000 0.000 tINS RR 57 HCLK_ibuf/O
0.413 0.413 tNET RR 1 u_ahb_to_apb_sync_down/state_reg_2_s0/CLK
0.795 0.382 tC2Q RR 8 u_ahb_to_apb_sync_down/state_reg_2_s0/Q
1.207 0.413 tNET RR 1 u_ahb_to_apb_sync_down/PSEL_d_s/I0
1.786 0.579 tINS RR 3 u_ahb_to_apb_sync_down/PSEL_d_s/F
2.199 0.413 tNET RR 1 u_ahb_to_apb_sync_down/next_state_1_s14/I3
2.487 0.289 tINS RR 3 u_ahb_to_apb_sync_down/next_state_1_s14/F
2.900 0.413 tNET RR 1 u_ahb_to_apb_sync_down/rwdata_reg_31_s4/I2
3.408 0.507 tINS RR 32 u_ahb_to_apb_sync_down/rwdata_reg_31_s4/F
3.820 0.413 tNET RR 1 u_ahb_to_apb_sync_down/rwdata_reg_4_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.000 0.000 tINS RR 57 HCLK_ibuf/O
10.413 0.413 tNET RR 1 u_ahb_to_apb_sync_down/rwdata_reg_4_s1/CLK
10.101 -0.311 tSu 1 u_ahb_to_apb_sync_down/rwdata_reg_4_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 1.375, 40.352%; route: 1.650, 48.423%; tC2Q: 0.382, 11.225%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%