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AHB to APB Sync Down IP FPGA Reference Design Read Me File
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Includes
    RiscV_AE350_SOC.
    AHB to APB Sync Down.
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Frequency
    CORE clock        : 800MHz
    DDR clock         : 50MHz (for test)
    AHB clock         : 50MHz (for test)
    APB clock         : 50MHz (for test)
    RTC clock         : 10MHz
    DDR3 memory clock : 200MHz (for test)
    DDR3 input clock  : 50MHz
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Platform
    DK_START_GW5AST-LV138FPG676A_V1.0
        GW5AST-LV138FPG676AC1/I0
        GW5AST-138
        B
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Configuration
    RiscV_AE350_SOC
      - SPI Flash Instruction Memory
      - DDR3 Data Memory
      - RTC
      - UART2
      - Extended AHB Slave
    AHB to APB Sync Down
      - Address Width: 8MB
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FPGA IDE
    Version tested: Gowin_V1.9.11.01 (64-bit).
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