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                                            AHB to APB Sync Down IP Reference Design Read Me File
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Object Target
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DK_START_GW5AST-LV138FPG676A_V1.0
    GW5AST-LV138FPG676AC1/I0
    GW5AST-138
    B

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Software Version
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Version tested:
    Gowin_V1.9.11.01 (64-bit)
    AE350_RDS V1.3

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File List
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.
|-- doc                                           -->  Documents
|   `-- ReadMe.txt                                -->  Read me file (this file)
|   `-- ReleaseNote.txt                           -->  Release note file
|-- ref_design                                    -->  Reference design
|   |-- FPGA_RefDesign                            -->  FPGA reference design
|       `-- ReadMe.txt                            -->  Read me file
|       |-- DK_START_GW5AST138_V1.0               -->  FPGA reference design for DK_START_GW5AST-LV138FPG676A_V1.0
|       |   `-- ReadMe.txt                        -->  Read me file
|       |   |-- ahb_to_apb_sync_down              -->  FPGA reference design
|   |-- MCU_RefDesign                             -->  MCU reference design
|       `-- ReadMe.txt                            -->  Read me file
|       |-- ahb_to_apb_sync_down                  -->  MCU reference design

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HOW TO OPEN A PROJECT IN Gowin
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1. Unzip the respective design files.
2. Launch Gowin and select "File -> Open -> Project".
3. In the Open Project dialog, enter the Project location -- "ahb_to_apb_sync_down", select the project "ahb_to_apb_sync_down.gprj".
4. Click Finish. Now the project is successfully loaded.

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HOW TO OPEN A PROJECT IN RDS
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1. Unzip the respective design files.
2. Launch RDS and select "File -> Import...".
3. In the Open Project dialog, enter the Project location -- "ahb_to_apb_sync_down".
4. Click Finish. Now the project is successfully loaded.

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HOW TO RUN SYNTHESIZE, PLACE AND ROUTE, IP CORE GENERATOR, AND TIMING ANALYSIS IN Gowin
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1. Click the Process tab in the process panel of the Gowin dashboard.
   Double click on Synthsize(GowinSynthesis). This will bring the design through synthesis.
2. Click the Process tab in the process panel of the Gowin dashboard.
   Double click on Place & Route. This will bring the design through mapping, place and route.
3. Once Place & Route is done, user can double click on Timing Analysis Report to get the timing analysis result.

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HOW TO DOWNLOAD
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For example 5A-138K series devices:
1. Launch Programmer.
2. "exFlash Erase,Program 5A" to download FPGA bitstreafm file.
   Start address is 0x000000.
3. "exFlash C Bin Erase,Program 5A" to download MCU binary file.
   Start address is 0x600000.

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HOW TO GENERATE IP CORE
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1. Click the IP Core Generator tab in the Window panel of the Gowin dashboard.
   Double click on "Soft IP Core > Microprocessor System > Bus Interconnect > AHB to APB Sync Down".
   This will generate the 'AHB to APB Sync Down' IP.
2. Click the IP Core Generator tab in the Window panel of the Gowin dashboard.
   Double click on "Soft IP Core > Microprocessor System > Hard-Core-MCU > RiscV AE350 SOC".
   This will generate the 'RiscV AE350 SOC' IP.
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