Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.11_x64\IDE\ipcore\TSE_MAC\data\eth_mac_top.v D:\Gowin\Gowin_V1.9.11_x64\IDE\ipcore\TSE_MAC\data\eth_mac.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11 (64-bit) |
| Part Number | GW5A-LV25UG324ES |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Mon Dec 9 10:37:54 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Triple_Speed_Ethernet_MAC_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.401s, Peak memory usage = 83.203MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 83.203MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.088s, Peak memory usage = 83.203MB Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 83.203MB Optimizing Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.103s, Peak memory usage = 83.203MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 83.203MB Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 83.203MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 83.203MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 83.203MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.073s, Peak memory usage = 83.203MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 83.203MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 83.203MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 110.547MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.242s, Peak memory usage = 110.547MB Generate output files: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.184s, Peak memory usage = 110.547MB |
| Total Time and Memory Usage | CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 110.547MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 248 |
| I/O Buf | 248 |
| IBUF | 130 |
| OBUF | 118 |
| Register | 1189 |
| DFFPE | 80 |
| DFFCE | 1109 |
| LUT | 1026 |
| LUT2 | 172 |
| LUT3 | 236 |
| LUT4 | 618 |
| ALU | 6 |
| ALU | 6 |
| INV | 7 |
| INV | 7 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1039(1033 LUT, 6 ALU) / 23040 | 5% |
| Register | 1189 / 23685 | 6% |
| --Register as Latch | 0 / 23685 | 0% |
| --Register as FF | 1189 / 23685 | 6% |
| BSRAM | 0 / 56 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | mii_rx_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | mii_rx_clk_ibuf/I | ||
| 2 | mii_tx_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | mii_tx_clk_ibuf/I | ||
| 3 | clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | mii_rx_clk | 100.000(MHz) | 186.220(MHz) | 6 | TOP |
| 2 | mii_tx_clk | 100.000(MHz) | 182.149(MHz) | 6 | TOP |
| 3 | clk | 100.000(MHz) | 195.456(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 4.510 |
| Data Arrival Time | 5.554 |
| Data Required Time | 10.064 |
| From | u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3 |
| To | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_fcs_s6 |
| Launch Clk | mii_tx_clk[R] |
| Latch Clk | mii_tx_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | mii_tx_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | mii_tx_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 558 | mii_tx_clk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3/CLK |
| 0.757 | 0.382 | tC2Q | RR | 25 | u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3/Q |
| 1.132 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/late_col_s8/I0 |
| 1.659 | 0.526 | tINS | RR | 3 | u_triple_speed_mac/u_mac_tx_ctrl/late_col_s8/F |
| 2.034 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s17/I1 |
| 2.550 | 0.516 | tINS | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s17/F |
| 2.925 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s6/I1 |
| 3.441 | 0.516 | tINS | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s6/F |
| 3.816 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/I0 |
| 4.343 | 0.526 | tINS | RR | 2 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/F |
| 4.718 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/I2 |
| 5.179 | 0.461 | tINS | RR | 8 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/F |
| 5.554 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_fcs_s6/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | mii_tx_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | mii_tx_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 558 | mii_tx_clk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_fcs_s6/CLK |
| 10.064 | -0.311 | tSu | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_fcs_s6 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 2.546, 49.167%; route: 2.250, 43.447%; tC2Q: 0.382, 7.386% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:| Slack | 4.510 |
| Data Arrival Time | 5.554 |
| Data Required Time | 10.064 |
| From | u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3 |
| To | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pad_s8 |
| Launch Clk | mii_tx_clk[R] |
| Latch Clk | mii_tx_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | mii_tx_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | mii_tx_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 558 | mii_tx_clk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3/CLK |
| 0.757 | 0.382 | tC2Q | RR | 25 | u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3/Q |
| 1.132 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/late_col_s8/I0 |
| 1.659 | 0.526 | tINS | RR | 3 | u_triple_speed_mac/u_mac_tx_ctrl/late_col_s8/F |
| 2.034 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s17/I1 |
| 2.550 | 0.516 | tINS | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s17/F |
| 2.925 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s6/I1 |
| 3.441 | 0.516 | tINS | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s6/F |
| 3.816 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/I0 |
| 4.343 | 0.526 | tINS | RR | 2 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/F |
| 4.718 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/I2 |
| 5.179 | 0.461 | tINS | RR | 8 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/F |
| 5.554 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pad_s8/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | mii_tx_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | mii_tx_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 558 | mii_tx_clk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pad_s8/CLK |
| 10.064 | -0.311 | tSu | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pad_s8 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 2.546, 49.167%; route: 2.250, 43.447%; tC2Q: 0.382, 7.386% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:| Slack | 4.510 |
| Data Arrival Time | 5.554 |
| Data Required Time | 10.064 |
| From | u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3 |
| To | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_jam_s4 |
| Launch Clk | mii_tx_clk[R] |
| Latch Clk | mii_tx_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | mii_tx_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | mii_tx_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 558 | mii_tx_clk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3/CLK |
| 0.757 | 0.382 | tC2Q | RR | 25 | u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3/Q |
| 1.132 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/late_col_s8/I0 |
| 1.659 | 0.526 | tINS | RR | 3 | u_triple_speed_mac/u_mac_tx_ctrl/late_col_s8/F |
| 2.034 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s17/I1 |
| 2.550 | 0.516 | tINS | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s17/F |
| 2.925 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s6/I1 |
| 3.441 | 0.516 | tINS | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s6/F |
| 3.816 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/I0 |
| 4.343 | 0.526 | tINS | RR | 2 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/F |
| 4.718 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/I2 |
| 5.179 | 0.461 | tINS | RR | 8 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/F |
| 5.554 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_jam_s4/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | mii_tx_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | mii_tx_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 558 | mii_tx_clk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_jam_s4/CLK |
| 10.064 | -0.311 | tSu | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_jam_s4 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 2.546, 49.167%; route: 2.250, 43.447%; tC2Q: 0.382, 7.386% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:| Slack | 4.510 |
| Data Arrival Time | 5.554 |
| Data Required Time | 10.064 |
| From | u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3 |
| To | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_data_s12 |
| Launch Clk | mii_tx_clk[R] |
| Latch Clk | mii_tx_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | mii_tx_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | mii_tx_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 558 | mii_tx_clk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3/CLK |
| 0.757 | 0.382 | tC2Q | RR | 25 | u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3/Q |
| 1.132 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/late_col_s8/I0 |
| 1.659 | 0.526 | tINS | RR | 3 | u_triple_speed_mac/u_mac_tx_ctrl/late_col_s8/F |
| 2.034 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s17/I1 |
| 2.550 | 0.516 | tINS | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s17/F |
| 2.925 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s6/I1 |
| 3.441 | 0.516 | tINS | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s6/F |
| 3.816 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/I0 |
| 4.343 | 0.526 | tINS | RR | 2 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/F |
| 4.718 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/I2 |
| 5.179 | 0.461 | tINS | RR | 8 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/F |
| 5.554 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_data_s12/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | mii_tx_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | mii_tx_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 558 | mii_tx_clk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_data_s12/CLK |
| 10.064 | -0.311 | tSu | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_data_s12 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 2.546, 49.167%; route: 2.250, 43.447%; tC2Q: 0.382, 7.386% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:| Slack | 4.510 |
| Data Arrival Time | 5.554 |
| Data Required Time | 10.064 |
| From | u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3 |
| To | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_preamble_s14 |
| Launch Clk | mii_tx_clk[R] |
| Latch Clk | mii_tx_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | mii_tx_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | mii_tx_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 558 | mii_tx_clk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3/CLK |
| 0.757 | 0.382 | tC2Q | RR | 25 | u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3/Q |
| 1.132 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/late_col_s8/I0 |
| 1.659 | 0.526 | tINS | RR | 3 | u_triple_speed_mac/u_mac_tx_ctrl/late_col_s8/F |
| 2.034 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s17/I1 |
| 2.550 | 0.516 | tINS | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s17/F |
| 2.925 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s6/I1 |
| 3.441 | 0.516 | tINS | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s6/F |
| 3.816 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/I0 |
| 4.343 | 0.526 | tINS | RR | 2 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/F |
| 4.718 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/I2 |
| 5.179 | 0.461 | tINS | RR | 8 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/F |
| 5.554 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_preamble_s14/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | mii_tx_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | mii_tx_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 558 | mii_tx_clk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_preamble_s14/CLK |
| 10.064 | -0.311 | tSu | 1 | u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_preamble_s14 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 2.546, 49.167%; route: 2.250, 43.447%; tC2Q: 0.382, 7.386% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |