Timing Messages
| Report Title | Timing Analysis Report |
| Design File | E:\myWork\IP\releaseVerify\version\1.9.11\Gowin_MII_to_RMII_RefDesign\project\impl\gwsynthesis\fpga_project.vg |
| Physical Constraints File | --- |
| Timing Constraint File | E:\myWork\IP\releaseVerify\version\1.9.11\Gowin_MII_to_RMII_RefDesign\project\src\fpga_project.sdc |
| Tool Version | V1.9.11 (64-bit) |
| Part Number | GW5A-LV25UG324ES |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Wed Dec 25 14:21:37 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
| Setup Delay Model | Slow 0.855V 0C ES |
| Hold Delay Model | Fast 0.945V 85C ES |
| Numbers of Paths Analyzed | 3061 |
| Numbers of Endpoints Analyzed | 4024 |
| Numbers of Falling Endpoints | 0 |
| Numbers of Setup Violated Endpoints | 0 |
| Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
|---|---|---|---|---|---|---|---|---|---|
| 1 | refclk | Base | 10.000 | 100.000 | 0.000 | 5.000 | refclk | ||
| 2 | tx_mac_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | tx_mac_clk |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | refclk | 100.000(MHz) | 257.815(MHz) | 5 | TOP |
| 2 | tx_mac_clk | 100.000(MHz) | 117.902(MHz) | 6 | TOP |
Total Negative Slack Summary:
| Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
|---|---|---|---|
| refclk | Setup | 0.000 | 0 |
| refclk | Hold | 0.000 | 0 |
| tx_mac_clk | Setup | 0.000 | 0 |
| tx_mac_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 1.518 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pad_s8/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | 0.005 | 8.165 |
| 2 | 1.518 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_fcs_s6/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | 0.005 | 8.165 |
| 3 | 1.903 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_preamble_s14/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | 0.000 | 7.785 |
| 4 | 1.913 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_jam_s4/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | -0.009 | 7.785 |
| 5 | 2.108 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pause_s12/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | -0.014 | 7.595 |
| 6 | 2.291 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_data_s12/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | -0.005 | 7.403 |
| 7 | 2.630 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s2/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | -0.014 | 7.073 |
| 8 | 2.630 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_idle_s16/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | -0.014 | 7.073 |
| 9 | 3.162 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s2/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | -0.014 | 6.789 |
| 10 | 3.223 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clr_retrans_cnt_s0/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | -0.014 | 6.728 |
| 11 | 3.455 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_11_s1/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | -0.005 | 6.239 |
| 12 | 3.455 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_10_s1/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | -0.005 | 6.239 |
| 13 | 3.488 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_2_s1/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | 0.002 | 6.199 |
| 14 | 3.541 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_back_off_s0/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | -0.008 | 6.403 |
| 15 | 3.687 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_6_s1/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | -0.008 | 6.009 |
| 16 | 3.687 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_5_s1/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | -0.008 | 6.009 |
| 17 | 3.687 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_3_s1/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | -0.008 | 6.009 |
| 18 | 3.687 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_1_s1/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | -0.008 | 6.009 |
| 19 | 3.687 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_0_s1/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | -0.008 | 6.009 |
| 20 | 3.864 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_28_s1/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | 0.002 | 5.822 |
| 21 | 3.864 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_23_s1/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | 0.002 | 5.822 |
| 22 | 3.864 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_15_s1/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | 0.002 | 5.822 |
| 23 | 3.864 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_12_s1/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | 0.002 | 5.822 |
| 24 | 3.864 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_s1/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | 0.002 | 5.822 |
| 25 | 3.920 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_4_s1/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 10.000 | -0.008 | 5.777 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.275 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_o_tmp_14_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_o_14_s0/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.222 |
| 2 | 0.275 | u_mac_rx_model/rx_data_cnt_last_s4/Q | u_mac_rx_model/rx_data_cnt_last_s4/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 3 | 0.275 | u_mac_rx_model/shift_reg_9_s1/Q | u_mac_rx_model/shift_reg_9_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 4 | 0.275 | u_mac_rx_model/shift_reg_13_s1/Q | u_mac_rx_model/shift_reg_13_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 5 | 0.275 | u_mac_rx_model/shift_reg_23_s1/Q | u_mac_rx_model/shift_reg_23_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 6 | 0.275 | u_mac_rx_model/shift_reg_28_s1/Q | u_mac_rx_model/shift_reg_28_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 7 | 0.275 | u_mac_rx_model/shift_reg_32_s1/Q | u_mac_rx_model/shift_reg_32_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 8 | 0.275 | u_mac_rx_model/shift_reg_44_s1/Q | u_mac_rx_model/shift_reg_44_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 9 | 0.275 | u_mac_rx_model/shift_reg_47_s1/Q | u_mac_rx_model/shift_reg_47_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 10 | 0.275 | u_mac_rx_model/shift_reg_48_s1/Q | u_mac_rx_model/shift_reg_48_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 11 | 0.275 | u_mac_rx_model/shift_reg_49_s1/Q | u_mac_rx_model/shift_reg_49_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 12 | 0.275 | u_mac_rx_model/shift_reg_53_s1/Q | u_mac_rx_model/shift_reg_53_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 13 | 0.275 | u_mac_rx_model/shift_reg_55_s1/Q | u_mac_rx_model/shift_reg_55_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 14 | 0.275 | u_mac_rx_model/shift_reg_56_s1/Q | u_mac_rx_model/shift_reg_56_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 15 | 0.275 | u_mac_rx_model/shift_reg_63_s1/Q | u_mac_rx_model/shift_reg_63_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 16 | 0.275 | u_mac_rx_model/shift_reg_65_s1/Q | u_mac_rx_model/shift_reg_65_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 17 | 0.275 | u_mac_rx_model/shift_reg_69_s1/Q | u_mac_rx_model/shift_reg_69_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 18 | 0.275 | u_mac_rx_model/shift_reg_84_s1/Q | u_mac_rx_model/shift_reg_84_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 19 | 0.275 | u_mac_rx_model/shift_reg_92_s1/Q | u_mac_rx_model/shift_reg_92_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 20 | 0.275 | u_mac_rx_model/shift_reg_95_s1/Q | u_mac_rx_model/shift_reg_95_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 21 | 0.275 | u_mac_rx_model/shift_reg_101_s1/Q | u_mac_rx_model/shift_reg_101_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 22 | 0.275 | u_mac_rx_model/shift_reg_108_s1/Q | u_mac_rx_model/shift_reg_108_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 23 | 0.275 | u_mac_rx_model/rx_frm_cnt_3_s1/Q | u_mac_rx_model/rx_frm_cnt_3_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 24 | 0.275 | u_mac_rx_model/rx_frm_cnt_5_s1/Q | u_mac_rx_model/rx_frm_cnt_5_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 25 | 0.275 | u_mac_rx_model/rx_frm_cnt_11_s1/Q | u_mac_rx_model/rx_frm_cnt_11_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 6.811 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/rmii_rxd_d1_0_s0/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.060 | 2.902 |
| 2 | 6.811 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/rmii_rxd_d1_1_s0/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.060 | 2.902 |
| 3 | 6.815 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/mii_txd_tmp_3_s0/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.015 | 2.853 |
| 4 | 6.821 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/rmii_txd_0_s2/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.070 | 2.902 |
| 5 | 6.821 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/rmii_txd_1_s3/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.070 | 2.902 |
| 6 | 6.821 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/rmii_tx_en_s2/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.070 | 2.902 |
| 7 | 6.822 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/rmii_rx_crs_dv_d1_s0/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.057 | 2.888 |
| 8 | 6.824 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rxd_0_s1/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.031 | 2.859 |
| 9 | 6.824 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rxd_1_s1/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.031 | 2.859 |
| 10 | 6.824 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rxd_3_s2/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.025 | 2.853 |
| 11 | 6.824 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/di_bits_data_0_s0/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.031 | 2.859 |
| 12 | 6.824 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/di_bits_data_1_s0/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.031 | 2.859 |
| 13 | 6.824 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/di_bits_data_2_s0/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.031 | 2.859 |
| 14 | 6.824 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/di_bits_data_3_s0/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.031 | 2.859 |
| 15 | 6.824 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/mii_txd_tmp_1_s0/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.025 | 2.853 |
| 16 | 6.824 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.019 | 2.847 |
| 17 | 6.824 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_4_s0/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.019 | 2.847 |
| 18 | 6.824 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_0_s0/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.025 | 2.853 |
| 19 | 6.824 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_1_s0/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.025 | 2.853 |
| 20 | 6.824 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_2_s0/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.019 | 2.847 |
| 21 | 6.824 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_3_s0/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.019 | 2.847 |
| 22 | 6.827 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/mii_tx_en_tmp_s0/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.048 | 2.873 |
| 23 | 6.827 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/mii_txd_tmp_0_s0/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.040 | 2.866 |
| 24 | 6.828 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rx_dv_s2/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.037 | 2.861 |
| 25 | 6.828 | rstn_ip_s0/Q | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rxd_2_s1/CLEAR | refclk:[R] | refclk:[R] | 10.000 | -0.037 | 2.861 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 1.162 | rstn_ip_s0/Q | u_mac_rx_model/rx_cnt_19_s0/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.003 | 1.147 |
| 2 | 1.162 | rstn_ip_s0/Q | u_mac_rx_model/rx_cnt_20_s0/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.003 | 1.147 |
| 3 | 1.162 | rstn_ip_s0/Q | u_mac_rx_model/rx_cnt_21_s0/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.003 | 1.147 |
| 4 | 1.162 | rstn_ip_s0/Q | u_mac_rx_model/rx_cnt_22_s0/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.003 | 1.147 |
| 5 | 1.162 | rstn_ip_s0/Q | u_mac_rx_model/rx_cnt_23_s0/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.003 | 1.147 |
| 6 | 1.162 | rstn_ip_s0/Q | u_mac_rx_model/rx_cnt_24_s0/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.003 | 1.147 |
| 7 | 1.162 | rstn_ip_s0/Q | u_mac_rx_model/rx_statistics_length_check_64_s0/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.003 | 1.147 |
| 8 | 1.162 | rstn_ip_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_latch_18_s3/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.003 | 1.147 |
| 9 | 1.162 | rstn_ip_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg2_18_s0/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.003 | 1.147 |
| 10 | 1.162 | rstn_ip_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg1_18_s0/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.003 | 1.147 |
| 11 | 1.166 | rstn_ip_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_6_s0/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.013 | 1.161 |
| 12 | 1.166 | rstn_ip_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_3_s0/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.013 | 1.161 |
| 13 | 1.166 | rstn_ip_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_2_s0/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.013 | 1.161 |
| 14 | 1.166 | rstn_ip_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_1_s0/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.013 | 1.161 |
| 15 | 1.166 | rstn_ip_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_3_s1/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.013 | 1.161 |
| 16 | 1.166 | rstn_ip_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_2_s1/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.013 | 1.161 |
| 17 | 1.166 | rstn_ip_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_15_s4/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.013 | 1.161 |
| 18 | 1.166 | rstn_ip_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_4_s3/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.013 | 1.161 |
| 19 | 1.166 | rstn_ip_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg1_40_s0/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.013 | 1.161 |
| 20 | 1.166 | rstn_ip_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_val_reg1_8_s0/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.013 | 1.161 |
| 21 | 1.166 | rstn_ip_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg2_40_s0/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.013 | 1.161 |
| 22 | 1.166 | rstn_ip_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_val_reg2_8_s0/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.013 | 1.161 |
| 23 | 1.166 | rstn_ip_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/jam_cnt_1_s0/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.013 | 1.161 |
| 24 | 1.166 | rstn_ip_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/jam_cnt_0_s0/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.013 | 1.161 |
| 25 | 1.166 | rstn_ip_s0/Q | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pad_s8/CLEAR | refclk:[R] | tx_mac_clk:[R] | 0.000 | -0.013 | 1.161 |
Minimum Pulse Width Table:
| Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
|---|---|---|---|---|---|---|
| 1 | 2.890 | 3.140 | 0.250 | Low Pulse Width | tx_mac_clk | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_21_s1 |
| 2 | 2.890 | 3.140 | 0.250 | Low Pulse Width | tx_mac_clk | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_13_s1 |
| 3 | 2.890 | 3.140 | 0.250 | Low Pulse Width | tx_mac_clk | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_3_s1 |
| 4 | 2.890 | 3.140 | 0.250 | Low Pulse Width | tx_mac_clk | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_2_s1 |
| 5 | 2.890 | 3.140 | 0.250 | Low Pulse Width | tx_mac_clk | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_lfsr/z_reg_14_s0 |
| 6 | 2.890 | 3.140 | 0.250 | Low Pulse Width | tx_mac_clk | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_lfsr/z_reg_2_s0 |
| 7 | 2.890 | 3.140 | 0.250 | Low Pulse Width | tx_mac_clk | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_lfsr/z_reg_9_s0 |
| 8 | 2.890 | 3.140 | 0.250 | Low Pulse Width | tx_mac_clk | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_lfsr/z_reg_5_s0 |
| 9 | 2.890 | 3.140 | 0.250 | Low Pulse Width | tx_mac_clk | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_1_s1 |
| 10 | 2.890 | 3.140 | 0.250 | Low Pulse Width | tx_mac_clk | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_31_s1 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 1.518 |
| Data Arrival Time | 11.442 |
| Data Required Time | 12.961 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pad_s8 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.342 | 2.683 | tNET | RR | 1 | R7C22[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s15/I0 |
| 6.858 | 0.516 | tINS | RR | 1 | R7C22[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s15/F |
| 7.016 | 0.157 | tNET | RR | 1 | R7C23[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s12/I3 |
| 7.477 | 0.461 | tINS | RR | 1 | R7C23[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s12/F |
| 7.480 | 0.003 | tNET | RR | 1 | R7C23[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s8/I2 |
| 7.742 | 0.262 | tINS | RR | 1 | R7C23[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s8/F |
| 7.745 | 0.003 | tNET | RR | 1 | R7C23[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/I3 |
| 8.266 | 0.521 | tINS | RR | 2 | R7C23[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/F |
| 9.288 | 1.023 | tNET | RR | 1 | R4C28[3][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/I2 |
| 9.810 | 0.521 | tINS | RR | 8 | R4C28[3][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/F |
| 11.442 | 1.632 | tNET | RR | 1 | R9C21[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pad_s8/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.272 | 3.272 | tNET | RR | 1 | R9C21[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pad_s8/CLK |
| 12.961 | -0.311 | tSu | 1 | R9C21[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pad_s8 |
Path Statistics:
| Clock Skew | -0.005 |
| Setup Relationship | 10.000 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 2.283, 27.954%; route: 5.500, 67.362%; tC2Q: 0.382, 4.684% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.272, 100.000% |
Path2
Path Summary:
| Slack | 1.518 |
| Data Arrival Time | 11.442 |
| Data Required Time | 12.961 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_fcs_s6 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.342 | 2.683 | tNET | RR | 1 | R7C22[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s15/I0 |
| 6.858 | 0.516 | tINS | RR | 1 | R7C22[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s15/F |
| 7.016 | 0.157 | tNET | RR | 1 | R7C23[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s12/I3 |
| 7.477 | 0.461 | tINS | RR | 1 | R7C23[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s12/F |
| 7.480 | 0.003 | tNET | RR | 1 | R7C23[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s8/I2 |
| 7.742 | 0.262 | tINS | RR | 1 | R7C23[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s8/F |
| 7.745 | 0.003 | tNET | RR | 1 | R7C23[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/I3 |
| 8.266 | 0.521 | tINS | RR | 2 | R7C23[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/F |
| 9.288 | 1.023 | tNET | RR | 1 | R4C28[3][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/I2 |
| 9.810 | 0.521 | tINS | RR | 8 | R4C28[3][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/F |
| 11.442 | 1.632 | tNET | RR | 1 | R9C21[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_fcs_s6/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.272 | 3.272 | tNET | RR | 1 | R9C21[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_fcs_s6/CLK |
| 12.961 | -0.311 | tSu | 1 | R9C21[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_fcs_s6 |
Path Statistics:
| Clock Skew | -0.005 |
| Setup Relationship | 10.000 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 2.283, 27.954%; route: 5.500, 67.362%; tC2Q: 0.382, 4.684% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.272, 100.000% |
Path3
Path Summary:
| Slack | 1.903 |
| Data Arrival Time | 11.062 |
| Data Required Time | 12.966 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_preamble_s14 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.342 | 2.683 | tNET | RR | 1 | R7C22[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s15/I0 |
| 6.858 | 0.516 | tINS | RR | 1 | R7C22[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s15/F |
| 7.016 | 0.157 | tNET | RR | 1 | R7C23[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s12/I3 |
| 7.477 | 0.461 | tINS | RR | 1 | R7C23[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s12/F |
| 7.480 | 0.003 | tNET | RR | 1 | R7C23[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s8/I2 |
| 7.742 | 0.262 | tINS | RR | 1 | R7C23[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s8/F |
| 7.745 | 0.003 | tNET | RR | 1 | R7C23[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/I3 |
| 8.266 | 0.521 | tINS | RR | 2 | R7C23[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/F |
| 9.288 | 1.023 | tNET | RR | 1 | R4C28[3][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/I2 |
| 9.810 | 0.521 | tINS | RR | 8 | R4C28[3][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/F |
| 11.062 | 1.253 | tNET | RR | 1 | R7C20[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_preamble_s14/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.277 | 3.277 | tNET | RR | 1 | R7C20[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_preamble_s14/CLK |
| 12.966 | -0.311 | tSu | 1 | R7C20[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_preamble_s14 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 10.000 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 2.283, 29.318%; route: 5.120, 65.769%; tC2Q: 0.382, 4.913% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
Path4
Path Summary:
| Slack | 1.913 |
| Data Arrival Time | 11.062 |
| Data Required Time | 12.975 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_jam_s4 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.342 | 2.683 | tNET | RR | 1 | R7C22[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s15/I0 |
| 6.858 | 0.516 | tINS | RR | 1 | R7C22[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s15/F |
| 7.016 | 0.157 | tNET | RR | 1 | R7C23[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s12/I3 |
| 7.477 | 0.461 | tINS | RR | 1 | R7C23[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s12/F |
| 7.480 | 0.003 | tNET | RR | 1 | R7C23[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s8/I2 |
| 7.742 | 0.262 | tINS | RR | 1 | R7C23[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s8/F |
| 7.745 | 0.003 | tNET | RR | 1 | R7C23[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/I3 |
| 8.266 | 0.521 | tINS | RR | 2 | R7C23[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/F |
| 9.288 | 1.023 | tNET | RR | 1 | R4C28[3][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/I2 |
| 9.810 | 0.521 | tINS | RR | 8 | R4C28[3][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/F |
| 11.062 | 1.253 | tNET | RR | 1 | R7C21[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_jam_s4/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.286 | 3.286 | tNET | RR | 1 | R7C21[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_jam_s4/CLK |
| 12.975 | -0.311 | tSu | 1 | R7C21[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_jam_s4 |
Path Statistics:
| Clock Skew | 0.009 |
| Setup Relationship | 10.000 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 2.283, 29.318%; route: 5.120, 65.769%; tC2Q: 0.382, 4.913% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.286, 100.000% |
Path5
Path Summary:
| Slack | 2.108 |
| Data Arrival Time | 10.872 |
| Data Required Time | 12.980 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pause_s12 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.342 | 2.683 | tNET | RR | 1 | R7C22[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s15/I0 |
| 6.858 | 0.516 | tINS | RR | 1 | R7C22[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s15/F |
| 7.016 | 0.157 | tNET | RR | 1 | R7C23[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s12/I3 |
| 7.477 | 0.461 | tINS | RR | 1 | R7C23[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s12/F |
| 7.480 | 0.003 | tNET | RR | 1 | R7C23[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s8/I2 |
| 7.742 | 0.262 | tINS | RR | 1 | R7C23[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s8/F |
| 7.745 | 0.003 | tNET | RR | 1 | R7C23[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/I3 |
| 8.266 | 0.521 | tINS | RR | 2 | R7C23[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/F |
| 9.288 | 1.023 | tNET | RR | 1 | R4C28[3][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/I2 |
| 9.810 | 0.521 | tINS | RR | 8 | R4C28[3][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/F |
| 10.872 | 1.063 | tNET | RR | 1 | R5C21[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pause_s12/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.291 | 3.291 | tNET | RR | 1 | R5C21[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pause_s12/CLK |
| 12.980 | -0.311 | tSu | 1 | R5C21[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pause_s12 |
Path Statistics:
| Clock Skew | 0.014 |
| Setup Relationship | 10.000 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 2.283, 30.051%; route: 4.930, 64.913%; tC2Q: 0.382, 5.036% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.291, 100.000% |
Path6
Path Summary:
| Slack | 2.291 |
| Data Arrival Time | 10.680 |
| Data Required Time | 12.971 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_data_s12 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.342 | 2.683 | tNET | RR | 1 | R7C22[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s15/I0 |
| 6.858 | 0.516 | tINS | RR | 1 | R7C22[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s15/F |
| 7.016 | 0.157 | tNET | RR | 1 | R7C23[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s12/I3 |
| 7.477 | 0.461 | tINS | RR | 1 | R7C23[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s12/F |
| 7.480 | 0.003 | tNET | RR | 1 | R7C23[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s8/I2 |
| 7.742 | 0.262 | tINS | RR | 1 | R7C23[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s8/F |
| 7.745 | 0.003 | tNET | RR | 1 | R7C23[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/I3 |
| 8.266 | 0.521 | tINS | RR | 2 | R7C23[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/F |
| 9.288 | 1.023 | tNET | RR | 1 | R4C28[3][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/I2 |
| 9.810 | 0.521 | tINS | RR | 8 | R4C28[3][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/F |
| 10.680 | 0.870 | tNET | RR | 1 | R5C22[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_data_s12/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.282 | 3.282 | tNET | RR | 1 | R5C22[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_data_s12/CLK |
| 12.971 | -0.311 | tSu | 1 | R5C22[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_data_s12 |
Path Statistics:
| Clock Skew | 0.005 |
| Setup Relationship | 10.000 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 2.283, 30.833%; route: 4.738, 64.000%; tC2Q: 0.382, 5.167% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.282, 100.000% |
Path7
Path Summary:
| Slack | 2.630 |
| Data Arrival Time | 10.350 |
| Data Required Time | 12.980 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s2 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.342 | 2.683 | tNET | RR | 1 | R7C22[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s15/I0 |
| 6.858 | 0.516 | tINS | RR | 1 | R7C22[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s15/F |
| 7.016 | 0.157 | tNET | RR | 1 | R7C23[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s12/I3 |
| 7.477 | 0.461 | tINS | RR | 1 | R7C23[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s12/F |
| 7.480 | 0.003 | tNET | RR | 1 | R7C23[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s8/I2 |
| 7.742 | 0.262 | tINS | RR | 1 | R7C23[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s8/F |
| 7.745 | 0.003 | tNET | RR | 1 | R7C23[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/I3 |
| 8.266 | 0.521 | tINS | RR | 2 | R7C23[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/F |
| 9.288 | 1.023 | tNET | RR | 1 | R4C28[3][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/I2 |
| 9.810 | 0.521 | tINS | RR | 8 | R4C28[3][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/F |
| 10.350 | 0.540 | tNET | RR | 1 | R5C25[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s2/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.291 | 3.291 | tNET | RR | 1 | R5C25[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s2/CLK |
| 12.980 | -0.311 | tSu | 1 | R5C25[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s2 |
Path Statistics:
| Clock Skew | 0.014 |
| Setup Relationship | 10.000 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 2.283, 32.271%; route: 4.408, 62.321%; tC2Q: 0.382, 5.408% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.291, 100.000% |
Path8
Path Summary:
| Slack | 2.630 |
| Data Arrival Time | 10.350 |
| Data Required Time | 12.980 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_idle_s16 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.342 | 2.683 | tNET | RR | 1 | R7C22[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s15/I0 |
| 6.858 | 0.516 | tINS | RR | 1 | R7C22[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s15/F |
| 7.016 | 0.157 | tNET | RR | 1 | R7C23[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s12/I3 |
| 7.477 | 0.461 | tINS | RR | 1 | R7C23[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s12/F |
| 7.480 | 0.003 | tNET | RR | 1 | R7C23[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s8/I2 |
| 7.742 | 0.262 | tINS | RR | 1 | R7C23[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s8/F |
| 7.745 | 0.003 | tNET | RR | 1 | R7C23[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/I3 |
| 8.266 | 0.521 | tINS | RR | 2 | R7C23[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/F |
| 9.288 | 1.023 | tNET | RR | 1 | R4C28[3][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/I2 |
| 9.810 | 0.521 | tINS | RR | 8 | R4C28[3][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/F |
| 10.350 | 0.540 | tNET | RR | 1 | R5C25[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_idle_s16/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.291 | 3.291 | tNET | RR | 1 | R5C25[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_idle_s16/CLK |
| 12.980 | -0.311 | tSu | 1 | R5C25[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_idle_s16 |
Path Statistics:
| Clock Skew | 0.014 |
| Setup Relationship | 10.000 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 2.283, 32.271%; route: 4.408, 62.321%; tC2Q: 0.382, 5.408% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.291, 100.000% |
Path9
Path Summary:
| Slack | 3.162 |
| Data Arrival Time | 10.066 |
| Data Required Time | 13.227 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s2 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.342 | 2.683 | tNET | RR | 1 | R7C22[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n795_s3/I0 |
| 6.858 | 0.516 | tINS | RR | 6 | R7C22[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n795_s3/F |
| 7.541 | 0.682 | tNET | RR | 1 | R6C25[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n_state.s_ifg_s42/I3 |
| 8.002 | 0.461 | tINS | RR | 1 | R6C25[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n_state.s_ifg_s42/F |
| 8.422 | 0.420 | tNET | RR | 1 | R6C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n_state.s_ifg_s41/I3 |
| 8.938 | 0.516 | tINS | RR | 2 | R6C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n_state.s_ifg_s41/F |
| 10.066 | 1.127 | tNET | RR | 1 | R5C25[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s2/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.291 | 3.291 | tNET | RR | 1 | R5C25[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s2/CLK |
| 13.227 | -0.064 | tSu | 1 | R5C25[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s2 |
Path Statistics:
| Clock Skew | 0.014 |
| Setup Relationship | 10.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 1.494, 22.002%; route: 4.913, 72.364%; tC2Q: 0.382, 5.634% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.291, 100.000% |
Path10
Path Summary:
| Slack | 3.223 |
| Data Arrival Time | 10.005 |
| Data Required Time | 13.227 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clr_retrans_cnt_s0 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.342 | 2.683 | tNET | RR | 1 | R7C22[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n795_s3/I0 |
| 6.858 | 0.516 | tINS | RR | 6 | R7C22[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n795_s3/F |
| 7.541 | 0.682 | tNET | RR | 1 | R6C25[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n_state.s_ifg_s42/I3 |
| 8.002 | 0.461 | tINS | RR | 1 | R6C25[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n_state.s_ifg_s42/F |
| 8.422 | 0.420 | tNET | RR | 1 | R6C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n_state.s_ifg_s41/I3 |
| 8.938 | 0.516 | tINS | RR | 2 | R6C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n_state.s_ifg_s41/F |
| 9.478 | 0.540 | tNET | RR | 1 | R5C25[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1279_s1/I2 |
| 10.005 | 0.526 | tINS | RR | 1 | R5C25[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1279_s1/F |
| 10.005 | 0.000 | tNET | RR | 1 | R5C25[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clr_retrans_cnt_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.291 | 3.291 | tNET | RR | 1 | R5C25[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clr_retrans_cnt_s0/CLK |
| 13.227 | -0.064 | tSu | 1 | R5C25[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clr_retrans_cnt_s0 |
Path Statistics:
| Clock Skew | 0.014 |
| Setup Relationship | 10.000 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 2.020, 30.025%; route: 4.325, 64.290%; tC2Q: 0.382, 5.685% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.291, 100.000% |
Path11
Path Summary:
| Slack | 3.455 |
| Data Arrival Time | 9.516 |
| Data Required Time | 12.971 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_11_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.342 | 2.683 | tNET | RR | 1 | R7C22[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n795_s3/I0 |
| 6.858 | 0.516 | tINS | RR | 6 | R7C22[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n795_s3/F |
| 7.788 | 0.930 | tNET | RR | 1 | R4C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s1/I1 |
| 8.051 | 0.262 | tINS | RR | 1 | R4C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s1/F |
| 8.053 | 0.003 | tNET | RR | 1 | R4C28[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s0/I0 |
| 8.580 | 0.526 | tINS | RR | 16 | R4C28[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s0/F |
| 9.516 | 0.936 | tNET | RR | 1 | R5C28[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_11_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.282 | 3.282 | tNET | RR | 1 | R5C28[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_11_s1/CLK |
| 12.971 | -0.311 | tSu | 1 | R5C28[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_11_s1 |
Path Statistics:
| Clock Skew | 0.005 |
| Setup Relationship | 10.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 1.305, 20.917%; route: 4.552, 72.953%; tC2Q: 0.382, 6.131% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.282, 100.000% |
Path12
Path Summary:
| Slack | 3.455 |
| Data Arrival Time | 9.516 |
| Data Required Time | 12.971 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_10_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.342 | 2.683 | tNET | RR | 1 | R7C22[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n795_s3/I0 |
| 6.858 | 0.516 | tINS | RR | 6 | R7C22[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n795_s3/F |
| 7.788 | 0.930 | tNET | RR | 1 | R4C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s1/I1 |
| 8.051 | 0.262 | tINS | RR | 1 | R4C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s1/F |
| 8.053 | 0.003 | tNET | RR | 1 | R4C28[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s0/I0 |
| 8.580 | 0.526 | tINS | RR | 16 | R4C28[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s0/F |
| 9.516 | 0.936 | tNET | RR | 1 | R5C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_10_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.282 | 3.282 | tNET | RR | 1 | R5C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_10_s1/CLK |
| 12.971 | -0.311 | tSu | 1 | R5C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_10_s1 |
Path Statistics:
| Clock Skew | 0.005 |
| Setup Relationship | 10.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 1.305, 20.917%; route: 4.552, 72.953%; tC2Q: 0.382, 6.131% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.282, 100.000% |
Path13
Path Summary:
| Slack | 3.488 |
| Data Arrival Time | 9.476 |
| Data Required Time | 12.964 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_2_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.342 | 2.683 | tNET | RR | 1 | R7C22[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n795_s3/I0 |
| 6.858 | 0.516 | tINS | RR | 6 | R7C22[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n795_s3/F |
| 7.788 | 0.930 | tNET | RR | 1 | R4C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s1/I1 |
| 8.051 | 0.262 | tINS | RR | 1 | R4C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s1/F |
| 8.053 | 0.003 | tNET | RR | 1 | R4C28[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s0/I0 |
| 8.580 | 0.526 | tINS | RR | 16 | R4C28[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s0/F |
| 9.476 | 0.896 | tNET | RR | 1 | R4C31[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_2_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.275 | 3.275 | tNET | RR | 1 | R4C31[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_2_s1/CLK |
| 12.964 | -0.311 | tSu | 1 | R4C31[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_2_s1 |
Path Statistics:
| Clock Skew | -0.002 |
| Setup Relationship | 10.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 1.305, 21.052%; route: 4.512, 72.778%; tC2Q: 0.382, 6.170% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.275, 100.000% |
Path14
Path Summary:
| Slack | 3.541 |
| Data Arrival Time | 9.680 |
| Data Required Time | 13.221 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_back_off_s0 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.342 | 2.683 | tNET | RR | 1 | R7C22[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s15/I0 |
| 6.858 | 0.516 | tINS | RR | 1 | R7C22[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s15/F |
| 7.016 | 0.157 | tNET | RR | 1 | R7C23[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s12/I3 |
| 7.477 | 0.461 | tINS | RR | 1 | R7C23[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s12/F |
| 7.480 | 0.003 | tNET | RR | 1 | R7C23[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s8/I2 |
| 7.742 | 0.262 | tINS | RR | 1 | R7C23[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s8/F |
| 7.745 | 0.003 | tNET | RR | 1 | R7C23[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/I3 |
| 8.266 | 0.521 | tINS | RR | 2 | R7C23[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/F |
| 9.153 | 0.887 | tNET | RR | 1 | R4C28[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n_state.s_back_off_s18/I1 |
| 9.680 | 0.526 | tINS | RR | 1 | R4C28[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n_state.s_back_off_s18/F |
| 9.680 | 0.000 | tNET | RR | 1 | R4C28[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_back_off_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.284 | 3.284 | tNET | RR | 1 | R4C28[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_back_off_s0/CLK |
| 13.221 | -0.064 | tSu | 1 | R4C28[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_back_off_s0 |
Path Statistics:
| Clock Skew | 0.008 |
| Setup Relationship | 10.000 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 2.287, 35.726%; route: 3.733, 58.300%; tC2Q: 0.382, 5.974% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.284, 100.000% |
Path15
Path Summary:
| Slack | 3.687 |
| Data Arrival Time | 9.286 |
| Data Required Time | 12.973 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_6_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.342 | 2.683 | tNET | RR | 1 | R7C22[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n795_s3/I0 |
| 6.858 | 0.516 | tINS | RR | 6 | R7C22[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n795_s3/F |
| 7.788 | 0.930 | tNET | RR | 1 | R4C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s1/I1 |
| 8.051 | 0.262 | tINS | RR | 1 | R4C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s1/F |
| 8.053 | 0.003 | tNET | RR | 1 | R4C28[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s0/I0 |
| 8.580 | 0.526 | tINS | RR | 16 | R4C28[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s0/F |
| 9.286 | 0.706 | tNET | RR | 1 | R4C30[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_6_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.284 | 3.284 | tNET | RR | 1 | R4C30[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_6_s1/CLK |
| 12.973 | -0.311 | tSu | 1 | R4C30[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_6_s1 |
Path Statistics:
| Clock Skew | 0.008 |
| Setup Relationship | 10.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 1.305, 21.717%; route: 4.322, 71.917%; tC2Q: 0.382, 6.365% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.284, 100.000% |
Path16
Path Summary:
| Slack | 3.687 |
| Data Arrival Time | 9.286 |
| Data Required Time | 12.973 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_5_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.342 | 2.683 | tNET | RR | 1 | R7C22[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n795_s3/I0 |
| 6.858 | 0.516 | tINS | RR | 6 | R7C22[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n795_s3/F |
| 7.788 | 0.930 | tNET | RR | 1 | R4C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s1/I1 |
| 8.051 | 0.262 | tINS | RR | 1 | R4C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s1/F |
| 8.053 | 0.003 | tNET | RR | 1 | R4C28[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s0/I0 |
| 8.580 | 0.526 | tINS | RR | 16 | R4C28[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s0/F |
| 9.286 | 0.706 | tNET | RR | 1 | R4C30[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_5_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.284 | 3.284 | tNET | RR | 1 | R4C30[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_5_s1/CLK |
| 12.973 | -0.311 | tSu | 1 | R4C30[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_5_s1 |
Path Statistics:
| Clock Skew | 0.008 |
| Setup Relationship | 10.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 1.305, 21.717%; route: 4.322, 71.917%; tC2Q: 0.382, 6.365% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.284, 100.000% |
Path17
Path Summary:
| Slack | 3.687 |
| Data Arrival Time | 9.286 |
| Data Required Time | 12.973 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_3_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.342 | 2.683 | tNET | RR | 1 | R7C22[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n795_s3/I0 |
| 6.858 | 0.516 | tINS | RR | 6 | R7C22[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n795_s3/F |
| 7.788 | 0.930 | tNET | RR | 1 | R4C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s1/I1 |
| 8.051 | 0.262 | tINS | RR | 1 | R4C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s1/F |
| 8.053 | 0.003 | tNET | RR | 1 | R4C28[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s0/I0 |
| 8.580 | 0.526 | tINS | RR | 16 | R4C28[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s0/F |
| 9.286 | 0.706 | tNET | RR | 1 | R4C30[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_3_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.284 | 3.284 | tNET | RR | 1 | R4C30[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_3_s1/CLK |
| 12.973 | -0.311 | tSu | 1 | R4C30[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_3_s1 |
Path Statistics:
| Clock Skew | 0.008 |
| Setup Relationship | 10.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 1.305, 21.717%; route: 4.322, 71.917%; tC2Q: 0.382, 6.365% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.284, 100.000% |
Path18
Path Summary:
| Slack | 3.687 |
| Data Arrival Time | 9.286 |
| Data Required Time | 12.973 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_1_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.342 | 2.683 | tNET | RR | 1 | R7C22[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n795_s3/I0 |
| 6.858 | 0.516 | tINS | RR | 6 | R7C22[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n795_s3/F |
| 7.788 | 0.930 | tNET | RR | 1 | R4C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s1/I1 |
| 8.051 | 0.262 | tINS | RR | 1 | R4C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s1/F |
| 8.053 | 0.003 | tNET | RR | 1 | R4C28[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s0/I0 |
| 8.580 | 0.526 | tINS | RR | 16 | R4C28[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s0/F |
| 9.286 | 0.706 | tNET | RR | 1 | R4C30[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_1_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.284 | 3.284 | tNET | RR | 1 | R4C30[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_1_s1/CLK |
| 12.973 | -0.311 | tSu | 1 | R4C30[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_1_s1 |
Path Statistics:
| Clock Skew | 0.008 |
| Setup Relationship | 10.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 1.305, 21.717%; route: 4.322, 71.917%; tC2Q: 0.382, 6.365% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.284, 100.000% |
Path19
Path Summary:
| Slack | 3.687 |
| Data Arrival Time | 9.286 |
| Data Required Time | 12.973 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_0_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.342 | 2.683 | tNET | RR | 1 | R7C22[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n795_s3/I0 |
| 6.858 | 0.516 | tINS | RR | 6 | R7C22[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n795_s3/F |
| 7.788 | 0.930 | tNET | RR | 1 | R4C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s1/I1 |
| 8.051 | 0.262 | tINS | RR | 1 | R4C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s1/F |
| 8.053 | 0.003 | tNET | RR | 1 | R4C28[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s0/I0 |
| 8.580 | 0.526 | tINS | RR | 16 | R4C28[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s0/F |
| 9.286 | 0.706 | tNET | RR | 1 | R4C30[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_0_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.284 | 3.284 | tNET | RR | 1 | R4C30[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_0_s1/CLK |
| 12.973 | -0.311 | tSu | 1 | R4C30[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_0_s1 |
Path Statistics:
| Clock Skew | 0.008 |
| Setup Relationship | 10.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 1.305, 21.717%; route: 4.322, 71.917%; tC2Q: 0.382, 6.365% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.284, 100.000% |
Path20
Path Summary:
| Slack | 3.864 |
| Data Arrival Time | 9.099 |
| Data Required Time | 12.964 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_28_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.352 | 2.692 | tNET | RR | 1 | R4C20[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_30_s4/I2 |
| 6.868 | 0.516 | tINS | RR | 28 | R4C20[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_30_s4/F |
| 7.818 | 0.950 | tNET | RR | 1 | R2C22[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_30_s5/I3 |
| 8.344 | 0.526 | tINS | RR | 32 | R2C22[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_30_s5/F |
| 9.099 | 0.755 | tNET | RR | 1 | R4C23[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_28_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.275 | 3.275 | tNET | RR | 1 | R4C23[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_28_s1/CLK |
| 12.964 | -0.311 | tSu | 1 | R4C23[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_28_s1 |
Path Statistics:
| Clock Skew | -0.002 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 1.043, 17.905%; route: 4.398, 75.526%; tC2Q: 0.382, 6.569% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.275, 100.000% |
Path21
Path Summary:
| Slack | 3.864 |
| Data Arrival Time | 9.099 |
| Data Required Time | 12.964 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_23_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.352 | 2.692 | tNET | RR | 1 | R4C20[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_30_s4/I2 |
| 6.868 | 0.516 | tINS | RR | 28 | R4C20[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_30_s4/F |
| 7.818 | 0.950 | tNET | RR | 1 | R2C22[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_30_s5/I3 |
| 8.344 | 0.526 | tINS | RR | 32 | R2C22[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_30_s5/F |
| 9.099 | 0.755 | tNET | RR | 1 | R4C23[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_23_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.275 | 3.275 | tNET | RR | 1 | R4C23[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_23_s1/CLK |
| 12.964 | -0.311 | tSu | 1 | R4C23[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_23_s1 |
Path Statistics:
| Clock Skew | -0.002 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 1.043, 17.905%; route: 4.398, 75.526%; tC2Q: 0.382, 6.569% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.275, 100.000% |
Path22
Path Summary:
| Slack | 3.864 |
| Data Arrival Time | 9.099 |
| Data Required Time | 12.964 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_15_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.352 | 2.692 | tNET | RR | 1 | R4C20[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_30_s4/I2 |
| 6.868 | 0.516 | tINS | RR | 28 | R4C20[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_30_s4/F |
| 7.818 | 0.950 | tNET | RR | 1 | R2C22[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_30_s5/I3 |
| 8.344 | 0.526 | tINS | RR | 32 | R2C22[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_30_s5/F |
| 9.099 | 0.755 | tNET | RR | 1 | R4C23[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_15_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.275 | 3.275 | tNET | RR | 1 | R4C23[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_15_s1/CLK |
| 12.964 | -0.311 | tSu | 1 | R4C23[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_15_s1 |
Path Statistics:
| Clock Skew | -0.002 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 1.043, 17.905%; route: 4.398, 75.526%; tC2Q: 0.382, 6.569% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.275, 100.000% |
Path23
Path Summary:
| Slack | 3.864 |
| Data Arrival Time | 9.099 |
| Data Required Time | 12.964 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_12_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.352 | 2.692 | tNET | RR | 1 | R4C20[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_30_s4/I2 |
| 6.868 | 0.516 | tINS | RR | 28 | R4C20[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_30_s4/F |
| 7.818 | 0.950 | tNET | RR | 1 | R2C22[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_30_s5/I3 |
| 8.344 | 0.526 | tINS | RR | 32 | R2C22[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_30_s5/F |
| 9.099 | 0.755 | tNET | RR | 1 | R4C23[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_12_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.275 | 3.275 | tNET | RR | 1 | R4C23[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_12_s1/CLK |
| 12.964 | -0.311 | tSu | 1 | R4C23[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_12_s1 |
Path Statistics:
| Clock Skew | -0.002 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 1.043, 17.905%; route: 4.398, 75.526%; tC2Q: 0.382, 6.569% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.275, 100.000% |
Path24
Path Summary:
| Slack | 3.864 |
| Data Arrival Time | 9.099 |
| Data Required Time | 12.964 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.352 | 2.692 | tNET | RR | 1 | R4C20[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_30_s4/I2 |
| 6.868 | 0.516 | tINS | RR | 28 | R4C20[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_30_s4/F |
| 7.818 | 0.950 | tNET | RR | 1 | R2C22[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_30_s5/I3 |
| 8.344 | 0.526 | tINS | RR | 32 | R2C22[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_30_s5/F |
| 9.099 | 0.755 | tNET | RR | 1 | R4C23[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.275 | 3.275 | tNET | RR | 1 | R4C23[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_s1/CLK |
| 12.964 | -0.311 | tSu | 1 | R4C23[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_s1 |
Path Statistics:
| Clock Skew | -0.002 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 1.043, 17.905%; route: 4.398, 75.526%; tC2Q: 0.382, 6.569% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.275, 100.000% |
Path25
Path Summary:
| Slack | 3.920 |
| Data Arrival Time | 9.053 |
| Data Required Time | 12.973 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_4_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 3.277 | 3.277 | tNET | RR | 1 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 3.659 | 0.382 | tC2Q | RR | 70 | R7C22[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/clk_ena_s0/Q |
| 6.342 | 2.683 | tNET | RR | 1 | R7C22[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n795_s3/I0 |
| 6.858 | 0.516 | tINS | RR | 6 | R7C22[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n795_s3/F |
| 7.788 | 0.930 | tNET | RR | 1 | R4C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s1/I1 |
| 8.051 | 0.262 | tINS | RR | 1 | R4C28[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s1/F |
| 8.053 | 0.003 | tNET | RR | 1 | R4C28[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s0/I0 |
| 8.580 | 0.526 | tINS | RR | 16 | R4C28[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/n1016_s0/F |
| 9.053 | 0.474 | tNET | RR | 1 | R4C28[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_4_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | tx_mac_clk | ||||
| 10.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 13.284 | 3.284 | tNET | RR | 1 | R4C28[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_4_s1/CLK |
| 12.973 | -0.311 | tSu | 1 | R4C28[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/back_cnt_4_s1 |
Path Statistics:
| Clock Skew | 0.008 |
| Setup Relationship | 10.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.277, 100.000% |
| Arrival Data Path Delay | cell: 1.305, 22.591%; route: 4.089, 70.787%; tC2Q: 0.382, 6.622% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.284, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.568 |
| Data Required Time | 1.293 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_o_tmp_14_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_o_14_s0 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.346 | 1.346 | tNET | RR | 1 | R12C14[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_o_tmp_14_s0/CLK |
| 1.490 | 0.144 | tC2Q | RR | 1 | R12C14[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_o_tmp_14_s0/Q |
| 1.568 | 0.078 | tNET | RR | 1 | R12C14[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_o_14_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.346 | 1.346 | tNET | RR | 1 | R12C14[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_o_14_s0/CLK |
| 1.293 | -0.053 | tHld | 1 | R12C14[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_o_14_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.346, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.346, 100.000% |
Path2
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.675 |
| Data Required Time | 1.400 |
| From | u_mac_rx_model/rx_data_cnt_last_s4 |
| To | u_mac_rx_model/rx_data_cnt_last_s4 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.375 | 1.375 | tNET | RR | 1 | R7C8[0][A] | u_mac_rx_model/rx_data_cnt_last_s4/CLK |
| 1.516 | 0.141 | tC2Q | RF | 2 | R7C8[0][A] | u_mac_rx_model/rx_data_cnt_last_s4/Q |
| 1.522 | 0.006 | tNET | FF | 1 | R7C8[0][A] | u_mac_rx_model/n947_s4/I1 |
| 1.675 | 0.153 | tINS | FF | 1 | R7C8[0][A] | u_mac_rx_model/n947_s4/F |
| 1.675 | 0.000 | tNET | FF | 1 | R7C8[0][A] | u_mac_rx_model/rx_data_cnt_last_s4/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.375 | 1.375 | tNET | RR | 1 | R7C8[0][A] | u_mac_rx_model/rx_data_cnt_last_s4/CLK |
| 1.400 | 0.025 | tHld | 1 | R7C8[0][A] | u_mac_rx_model/rx_data_cnt_last_s4 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.375, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.375, 100.000% |
Path3
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.680 |
| Data Required Time | 1.405 |
| From | u_mac_rx_model/shift_reg_9_s1 |
| To | u_mac_rx_model/shift_reg_9_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.380 | 1.380 | tNET | RR | 1 | R2C7[0][A] | u_mac_rx_model/shift_reg_9_s1/CLK |
| 1.521 | 0.141 | tC2Q | RF | 2 | R2C7[0][A] | u_mac_rx_model/shift_reg_9_s1/Q |
| 1.527 | 0.006 | tNET | FF | 1 | R2C7[0][A] | u_mac_rx_model/n672_s2/I0 |
| 1.680 | 0.153 | tINS | FF | 1 | R2C7[0][A] | u_mac_rx_model/n672_s2/F |
| 1.680 | 0.000 | tNET | FF | 1 | R2C7[0][A] | u_mac_rx_model/shift_reg_9_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.380 | 1.380 | tNET | RR | 1 | R2C7[0][A] | u_mac_rx_model/shift_reg_9_s1/CLK |
| 1.405 | 0.025 | tHld | 1 | R2C7[0][A] | u_mac_rx_model/shift_reg_9_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.380, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.380, 100.000% |
Path4
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.678 |
| Data Required Time | 1.403 |
| From | u_mac_rx_model/shift_reg_13_s1 |
| To | u_mac_rx_model/shift_reg_13_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.378 | 1.378 | tNET | RR | 1 | R3C7[0][A] | u_mac_rx_model/shift_reg_13_s1/CLK |
| 1.519 | 0.141 | tC2Q | RF | 2 | R3C7[0][A] | u_mac_rx_model/shift_reg_13_s1/Q |
| 1.525 | 0.006 | tNET | FF | 1 | R3C7[0][A] | u_mac_rx_model/n668_s2/I0 |
| 1.678 | 0.153 | tINS | FF | 1 | R3C7[0][A] | u_mac_rx_model/n668_s2/F |
| 1.678 | 0.000 | tNET | FF | 1 | R3C7[0][A] | u_mac_rx_model/shift_reg_13_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.378 | 1.378 | tNET | RR | 1 | R3C7[0][A] | u_mac_rx_model/shift_reg_13_s1/CLK |
| 1.403 | 0.025 | tHld | 1 | R3C7[0][A] | u_mac_rx_model/shift_reg_13_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.378, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.378, 100.000% |
Path5
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.666 |
| Data Required Time | 1.391 |
| From | u_mac_rx_model/shift_reg_23_s1 |
| To | u_mac_rx_model/shift_reg_23_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.366 | 1.366 | tNET | RR | 1 | R8C7[0][A] | u_mac_rx_model/shift_reg_23_s1/CLK |
| 1.507 | 0.141 | tC2Q | RF | 2 | R8C7[0][A] | u_mac_rx_model/shift_reg_23_s1/Q |
| 1.513 | 0.006 | tNET | FF | 1 | R8C7[0][A] | u_mac_rx_model/n658_s2/I0 |
| 1.666 | 0.153 | tINS | FF | 1 | R8C7[0][A] | u_mac_rx_model/n658_s2/F |
| 1.666 | 0.000 | tNET | FF | 1 | R8C7[0][A] | u_mac_rx_model/shift_reg_23_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.366 | 1.366 | tNET | RR | 1 | R8C7[0][A] | u_mac_rx_model/shift_reg_23_s1/CLK |
| 1.391 | 0.025 | tHld | 1 | R8C7[0][A] | u_mac_rx_model/shift_reg_23_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.366, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.366, 100.000% |
Path6
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.683 |
| Data Required Time | 1.408 |
| From | u_mac_rx_model/shift_reg_28_s1 |
| To | u_mac_rx_model/shift_reg_28_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.383 | 1.383 | tNET | RR | 1 | R5C5[1][A] | u_mac_rx_model/shift_reg_28_s1/CLK |
| 1.524 | 0.141 | tC2Q | RF | 2 | R5C5[1][A] | u_mac_rx_model/shift_reg_28_s1/Q |
| 1.530 | 0.006 | tNET | FF | 1 | R5C5[1][A] | u_mac_rx_model/n653_s1/I0 |
| 1.683 | 0.153 | tINS | FF | 1 | R5C5[1][A] | u_mac_rx_model/n653_s1/F |
| 1.683 | 0.000 | tNET | FF | 1 | R5C5[1][A] | u_mac_rx_model/shift_reg_28_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.383 | 1.383 | tNET | RR | 1 | R5C5[1][A] | u_mac_rx_model/shift_reg_28_s1/CLK |
| 1.408 | 0.025 | tHld | 1 | R5C5[1][A] | u_mac_rx_model/shift_reg_28_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.383, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.383, 100.000% |
Path7
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.684 |
| Data Required Time | 1.409 |
| From | u_mac_rx_model/shift_reg_32_s1 |
| To | u_mac_rx_model/shift_reg_32_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.384 | 1.384 | tNET | RR | 1 | R2C8[1][A] | u_mac_rx_model/shift_reg_32_s1/CLK |
| 1.525 | 0.141 | tC2Q | RF | 2 | R2C8[1][A] | u_mac_rx_model/shift_reg_32_s1/Q |
| 1.531 | 0.006 | tNET | FF | 1 | R2C8[1][A] | u_mac_rx_model/n649_s2/I0 |
| 1.684 | 0.153 | tINS | FF | 1 | R2C8[1][A] | u_mac_rx_model/n649_s2/F |
| 1.684 | 0.000 | tNET | FF | 1 | R2C8[1][A] | u_mac_rx_model/shift_reg_32_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.384 | 1.384 | tNET | RR | 1 | R2C8[1][A] | u_mac_rx_model/shift_reg_32_s1/CLK |
| 1.409 | 0.025 | tHld | 1 | R2C8[1][A] | u_mac_rx_model/shift_reg_32_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.384, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.384, 100.000% |
Path8
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.683 |
| Data Required Time | 1.408 |
| From | u_mac_rx_model/shift_reg_44_s1 |
| To | u_mac_rx_model/shift_reg_44_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.383 | 1.383 | tNET | RR | 1 | R5C5[0][A] | u_mac_rx_model/shift_reg_44_s1/CLK |
| 1.524 | 0.141 | tC2Q | RF | 2 | R5C5[0][A] | u_mac_rx_model/shift_reg_44_s1/Q |
| 1.530 | 0.006 | tNET | FF | 1 | R5C5[0][A] | u_mac_rx_model/n637_s1/I0 |
| 1.683 | 0.153 | tINS | FF | 1 | R5C5[0][A] | u_mac_rx_model/n637_s1/F |
| 1.683 | 0.000 | tNET | FF | 1 | R5C5[0][A] | u_mac_rx_model/shift_reg_44_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.383 | 1.383 | tNET | RR | 1 | R5C5[0][A] | u_mac_rx_model/shift_reg_44_s1/CLK |
| 1.408 | 0.025 | tHld | 1 | R5C5[0][A] | u_mac_rx_model/shift_reg_44_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.383, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.383, 100.000% |
Path9
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.681 |
| Data Required Time | 1.406 |
| From | u_mac_rx_model/shift_reg_47_s1 |
| To | u_mac_rx_model/shift_reg_47_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.381 | 1.381 | tNET | RR | 1 | R6C5[0][A] | u_mac_rx_model/shift_reg_47_s1/CLK |
| 1.522 | 0.141 | tC2Q | RF | 2 | R6C5[0][A] | u_mac_rx_model/shift_reg_47_s1/Q |
| 1.528 | 0.006 | tNET | FF | 1 | R6C5[0][A] | u_mac_rx_model/n634_s2/I0 |
| 1.681 | 0.153 | tINS | FF | 1 | R6C5[0][A] | u_mac_rx_model/n634_s2/F |
| 1.681 | 0.000 | tNET | FF | 1 | R6C5[0][A] | u_mac_rx_model/shift_reg_47_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.381 | 1.381 | tNET | RR | 1 | R6C5[0][A] | u_mac_rx_model/shift_reg_47_s1/CLK |
| 1.406 | 0.025 | tHld | 1 | R6C5[0][A] | u_mac_rx_model/shift_reg_47_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.381, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.381, 100.000% |
Path10
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.684 |
| Data Required Time | 1.409 |
| From | u_mac_rx_model/shift_reg_48_s1 |
| To | u_mac_rx_model/shift_reg_48_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.384 | 1.384 | tNET | RR | 1 | R2C8[0][A] | u_mac_rx_model/shift_reg_48_s1/CLK |
| 1.525 | 0.141 | tC2Q | RF | 2 | R2C8[0][A] | u_mac_rx_model/shift_reg_48_s1/Q |
| 1.531 | 0.006 | tNET | FF | 1 | R2C8[0][A] | u_mac_rx_model/n633_s1/I0 |
| 1.684 | 0.153 | tINS | FF | 1 | R2C8[0][A] | u_mac_rx_model/n633_s1/F |
| 1.684 | 0.000 | tNET | FF | 1 | R2C8[0][A] | u_mac_rx_model/shift_reg_48_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.384 | 1.384 | tNET | RR | 1 | R2C8[0][A] | u_mac_rx_model/shift_reg_48_s1/CLK |
| 1.409 | 0.025 | tHld | 1 | R2C8[0][A] | u_mac_rx_model/shift_reg_48_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.384, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.384, 100.000% |
Path11
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.684 |
| Data Required Time | 1.409 |
| From | u_mac_rx_model/shift_reg_49_s1 |
| To | u_mac_rx_model/shift_reg_49_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.384 | 1.384 | tNET | RR | 1 | R2C6[1][A] | u_mac_rx_model/shift_reg_49_s1/CLK |
| 1.525 | 0.141 | tC2Q | RF | 2 | R2C6[1][A] | u_mac_rx_model/shift_reg_49_s1/Q |
| 1.531 | 0.006 | tNET | FF | 1 | R2C6[1][A] | u_mac_rx_model/n632_s2/I0 |
| 1.684 | 0.153 | tINS | FF | 1 | R2C6[1][A] | u_mac_rx_model/n632_s2/F |
| 1.684 | 0.000 | tNET | FF | 1 | R2C6[1][A] | u_mac_rx_model/shift_reg_49_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.384 | 1.384 | tNET | RR | 1 | R2C6[1][A] | u_mac_rx_model/shift_reg_49_s1/CLK |
| 1.409 | 0.025 | tHld | 1 | R2C6[1][A] | u_mac_rx_model/shift_reg_49_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.384, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.384, 100.000% |
Path12
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.682 |
| Data Required Time | 1.407 |
| From | u_mac_rx_model/shift_reg_53_s1 |
| To | u_mac_rx_model/shift_reg_53_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.382 | 1.382 | tNET | RR | 1 | R3C6[1][A] | u_mac_rx_model/shift_reg_53_s1/CLK |
| 1.523 | 0.141 | tC2Q | RF | 2 | R3C6[1][A] | u_mac_rx_model/shift_reg_53_s1/Q |
| 1.529 | 0.006 | tNET | FF | 1 | R3C6[1][A] | u_mac_rx_model/n628_s2/I0 |
| 1.682 | 0.153 | tINS | FF | 1 | R3C6[1][A] | u_mac_rx_model/n628_s2/F |
| 1.682 | 0.000 | tNET | FF | 1 | R3C6[1][A] | u_mac_rx_model/shift_reg_53_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.382 | 1.382 | tNET | RR | 1 | R3C6[1][A] | u_mac_rx_model/shift_reg_53_s1/CLK |
| 1.407 | 0.025 | tHld | 1 | R3C6[1][A] | u_mac_rx_model/shift_reg_53_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.382, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.382, 100.000% |
Path13
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.676 |
| Data Required Time | 1.401 |
| From | u_mac_rx_model/shift_reg_55_s1 |
| To | u_mac_rx_model/shift_reg_55_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.376 | 1.376 | tNET | RR | 1 | R4C7[0][A] | u_mac_rx_model/shift_reg_55_s1/CLK |
| 1.517 | 0.141 | tC2Q | RF | 2 | R4C7[0][A] | u_mac_rx_model/shift_reg_55_s1/Q |
| 1.523 | 0.006 | tNET | FF | 1 | R4C7[0][A] | u_mac_rx_model/n626_s1/I0 |
| 1.676 | 0.153 | tINS | FF | 1 | R4C7[0][A] | u_mac_rx_model/n626_s1/F |
| 1.676 | 0.000 | tNET | FF | 1 | R4C7[0][A] | u_mac_rx_model/shift_reg_55_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.376 | 1.376 | tNET | RR | 1 | R4C7[0][A] | u_mac_rx_model/shift_reg_55_s1/CLK |
| 1.401 | 0.025 | tHld | 1 | R4C7[0][A] | u_mac_rx_model/shift_reg_55_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.376, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.376, 100.000% |
Path14
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.682 |
| Data Required Time | 1.407 |
| From | u_mac_rx_model/shift_reg_56_s1 |
| To | u_mac_rx_model/shift_reg_56_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.382 | 1.382 | tNET | RR | 1 | R3C8[0][A] | u_mac_rx_model/shift_reg_56_s1/CLK |
| 1.523 | 0.141 | tC2Q | RF | 2 | R3C8[0][A] | u_mac_rx_model/shift_reg_56_s1/Q |
| 1.529 | 0.006 | tNET | FF | 1 | R3C8[0][A] | u_mac_rx_model/n625_s1/I0 |
| 1.682 | 0.153 | tINS | FF | 1 | R3C8[0][A] | u_mac_rx_model/n625_s1/F |
| 1.682 | 0.000 | tNET | FF | 1 | R3C8[0][A] | u_mac_rx_model/shift_reg_56_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.382 | 1.382 | tNET | RR | 1 | R3C8[0][A] | u_mac_rx_model/shift_reg_56_s1/CLK |
| 1.407 | 0.025 | tHld | 1 | R3C8[0][A] | u_mac_rx_model/shift_reg_56_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.382, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.382, 100.000% |
Path15
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.666 |
| Data Required Time | 1.391 |
| From | u_mac_rx_model/shift_reg_63_s1 |
| To | u_mac_rx_model/shift_reg_63_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.366 | 1.366 | tNET | RR | 1 | R8C7[1][A] | u_mac_rx_model/shift_reg_63_s1/CLK |
| 1.507 | 0.141 | tC2Q | RF | 2 | R8C7[1][A] | u_mac_rx_model/shift_reg_63_s1/Q |
| 1.513 | 0.006 | tNET | FF | 1 | R8C7[1][A] | u_mac_rx_model/n618_s1/I0 |
| 1.666 | 0.153 | tINS | FF | 1 | R8C7[1][A] | u_mac_rx_model/n618_s1/F |
| 1.666 | 0.000 | tNET | FF | 1 | R8C7[1][A] | u_mac_rx_model/shift_reg_63_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.366 | 1.366 | tNET | RR | 1 | R8C7[1][A] | u_mac_rx_model/shift_reg_63_s1/CLK |
| 1.391 | 0.025 | tHld | 1 | R8C7[1][A] | u_mac_rx_model/shift_reg_63_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.366, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.366, 100.000% |
Path16
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.684 |
| Data Required Time | 1.409 |
| From | u_mac_rx_model/shift_reg_65_s1 |
| To | u_mac_rx_model/shift_reg_65_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.384 | 1.384 | tNET | RR | 1 | R2C6[0][A] | u_mac_rx_model/shift_reg_65_s1/CLK |
| 1.525 | 0.141 | tC2Q | RF | 2 | R2C6[0][A] | u_mac_rx_model/shift_reg_65_s1/Q |
| 1.531 | 0.006 | tNET | FF | 1 | R2C6[0][A] | u_mac_rx_model/n616_s1/I0 |
| 1.684 | 0.153 | tINS | FF | 1 | R2C6[0][A] | u_mac_rx_model/n616_s1/F |
| 1.684 | 0.000 | tNET | FF | 1 | R2C6[0][A] | u_mac_rx_model/shift_reg_65_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.384 | 1.384 | tNET | RR | 1 | R2C6[0][A] | u_mac_rx_model/shift_reg_65_s1/CLK |
| 1.409 | 0.025 | tHld | 1 | R2C6[0][A] | u_mac_rx_model/shift_reg_65_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.384, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.384, 100.000% |
Path17
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.682 |
| Data Required Time | 1.407 |
| From | u_mac_rx_model/shift_reg_69_s1 |
| To | u_mac_rx_model/shift_reg_69_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.382 | 1.382 | tNET | RR | 1 | R3C6[0][A] | u_mac_rx_model/shift_reg_69_s1/CLK |
| 1.523 | 0.141 | tC2Q | RF | 2 | R3C6[0][A] | u_mac_rx_model/shift_reg_69_s1/Q |
| 1.529 | 0.006 | tNET | FF | 1 | R3C6[0][A] | u_mac_rx_model/n612_s1/I0 |
| 1.682 | 0.153 | tINS | FF | 1 | R3C6[0][A] | u_mac_rx_model/n612_s1/F |
| 1.682 | 0.000 | tNET | FF | 1 | R3C6[0][A] | u_mac_rx_model/shift_reg_69_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.382 | 1.382 | tNET | RR | 1 | R3C6[0][A] | u_mac_rx_model/shift_reg_69_s1/CLK |
| 1.407 | 0.025 | tHld | 1 | R3C6[0][A] | u_mac_rx_model/shift_reg_69_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.382, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.382, 100.000% |
Path18
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.681 |
| Data Required Time | 1.406 |
| From | u_mac_rx_model/shift_reg_84_s1 |
| To | u_mac_rx_model/shift_reg_84_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.381 | 1.381 | tNET | RR | 1 | R6C5[1][A] | u_mac_rx_model/shift_reg_84_s1/CLK |
| 1.522 | 0.141 | tC2Q | RF | 2 | R6C5[1][A] | u_mac_rx_model/shift_reg_84_s1/Q |
| 1.528 | 0.006 | tNET | FF | 1 | R6C5[1][A] | u_mac_rx_model/n597_s1/I0 |
| 1.681 | 0.153 | tINS | FF | 1 | R6C5[1][A] | u_mac_rx_model/n597_s1/F |
| 1.681 | 0.000 | tNET | FF | 1 | R6C5[1][A] | u_mac_rx_model/shift_reg_84_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.381 | 1.381 | tNET | RR | 1 | R6C5[1][A] | u_mac_rx_model/shift_reg_84_s1/CLK |
| 1.406 | 0.025 | tHld | 1 | R6C5[1][A] | u_mac_rx_model/shift_reg_84_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.381, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.381, 100.000% |
Path19
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.680 |
| Data Required Time | 1.405 |
| From | u_mac_rx_model/shift_reg_92_s1 |
| To | u_mac_rx_model/shift_reg_92_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.380 | 1.380 | tNET | RR | 1 | R4C6[1][A] | u_mac_rx_model/shift_reg_92_s1/CLK |
| 1.521 | 0.141 | tC2Q | RF | 2 | R4C6[1][A] | u_mac_rx_model/shift_reg_92_s1/Q |
| 1.527 | 0.006 | tNET | FF | 1 | R4C6[1][A] | u_mac_rx_model/n589_s2/I0 |
| 1.680 | 0.153 | tINS | FF | 1 | R4C6[1][A] | u_mac_rx_model/n589_s2/F |
| 1.680 | 0.000 | tNET | FF | 1 | R4C6[1][A] | u_mac_rx_model/shift_reg_92_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.380 | 1.380 | tNET | RR | 1 | R4C6[1][A] | u_mac_rx_model/shift_reg_92_s1/CLK |
| 1.405 | 0.025 | tHld | 1 | R4C6[1][A] | u_mac_rx_model/shift_reg_92_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.380, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.380, 100.000% |
Path20
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.676 |
| Data Required Time | 1.401 |
| From | u_mac_rx_model/shift_reg_95_s1 |
| To | u_mac_rx_model/shift_reg_95_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.376 | 1.376 | tNET | RR | 1 | R4C7[1][A] | u_mac_rx_model/shift_reg_95_s1/CLK |
| 1.517 | 0.141 | tC2Q | RF | 2 | R4C7[1][A] | u_mac_rx_model/shift_reg_95_s1/Q |
| 1.523 | 0.006 | tNET | FF | 1 | R4C7[1][A] | u_mac_rx_model/n586_s1/I0 |
| 1.676 | 0.153 | tINS | FF | 1 | R4C7[1][A] | u_mac_rx_model/n586_s1/F |
| 1.676 | 0.000 | tNET | FF | 1 | R4C7[1][A] | u_mac_rx_model/shift_reg_95_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.376 | 1.376 | tNET | RR | 1 | R4C7[1][A] | u_mac_rx_model/shift_reg_95_s1/CLK |
| 1.401 | 0.025 | tHld | 1 | R4C7[1][A] | u_mac_rx_model/shift_reg_95_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.376, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.376, 100.000% |
Path21
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.678 |
| Data Required Time | 1.403 |
| From | u_mac_rx_model/shift_reg_101_s1 |
| To | u_mac_rx_model/shift_reg_101_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.378 | 1.378 | tNET | RR | 1 | R3C7[1][A] | u_mac_rx_model/shift_reg_101_s1/CLK |
| 1.519 | 0.141 | tC2Q | RF | 2 | R3C7[1][A] | u_mac_rx_model/shift_reg_101_s1/Q |
| 1.525 | 0.006 | tNET | FF | 1 | R3C7[1][A] | u_mac_rx_model/n580_s2/I0 |
| 1.678 | 0.153 | tINS | FF | 1 | R3C7[1][A] | u_mac_rx_model/n580_s2/F |
| 1.678 | 0.000 | tNET | FF | 1 | R3C7[1][A] | u_mac_rx_model/shift_reg_101_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.378 | 1.378 | tNET | RR | 1 | R3C7[1][A] | u_mac_rx_model/shift_reg_101_s1/CLK |
| 1.403 | 0.025 | tHld | 1 | R3C7[1][A] | u_mac_rx_model/shift_reg_101_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.378, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.378, 100.000% |
Path22
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.680 |
| Data Required Time | 1.405 |
| From | u_mac_rx_model/shift_reg_108_s1 |
| To | u_mac_rx_model/shift_reg_108_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.380 | 1.380 | tNET | RR | 1 | R4C6[0][A] | u_mac_rx_model/shift_reg_108_s1/CLK |
| 1.521 | 0.141 | tC2Q | RF | 2 | R4C6[0][A] | u_mac_rx_model/shift_reg_108_s1/Q |
| 1.527 | 0.006 | tNET | FF | 1 | R4C6[0][A] | u_mac_rx_model/n573_s1/I0 |
| 1.680 | 0.153 | tINS | FF | 1 | R4C6[0][A] | u_mac_rx_model/n573_s1/F |
| 1.680 | 0.000 | tNET | FF | 1 | R4C6[0][A] | u_mac_rx_model/shift_reg_108_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.380 | 1.380 | tNET | RR | 1 | R4C6[0][A] | u_mac_rx_model/shift_reg_108_s1/CLK |
| 1.405 | 0.025 | tHld | 1 | R4C6[0][A] | u_mac_rx_model/shift_reg_108_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.380, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.380, 100.000% |
Path23
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.670 |
| Data Required Time | 1.395 |
| From | u_mac_rx_model/rx_frm_cnt_3_s1 |
| To | u_mac_rx_model/rx_frm_cnt_3_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.370 | 1.370 | tNET | RR | 1 | R8C4[1][A] | u_mac_rx_model/rx_frm_cnt_3_s1/CLK |
| 1.511 | 0.141 | tC2Q | RF | 5 | R8C4[1][A] | u_mac_rx_model/rx_frm_cnt_3_s1/Q |
| 1.517 | 0.006 | tNET | FF | 1 | R8C4[1][A] | u_mac_rx_model/n268_s6/I3 |
| 1.670 | 0.153 | tINS | FF | 1 | R8C4[1][A] | u_mac_rx_model/n268_s6/F |
| 1.670 | 0.000 | tNET | FF | 1 | R8C4[1][A] | u_mac_rx_model/rx_frm_cnt_3_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.370 | 1.370 | tNET | RR | 1 | R8C4[1][A] | u_mac_rx_model/rx_frm_cnt_3_s1/CLK |
| 1.395 | 0.025 | tHld | 1 | R8C4[1][A] | u_mac_rx_model/rx_frm_cnt_3_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.370, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.370, 100.000% |
Path24
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.674 |
| Data Required Time | 1.399 |
| From | u_mac_rx_model/rx_frm_cnt_5_s1 |
| To | u_mac_rx_model/rx_frm_cnt_5_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.374 | 1.374 | tNET | RR | 1 | R8C5[1][A] | u_mac_rx_model/rx_frm_cnt_5_s1/CLK |
| 1.515 | 0.141 | tC2Q | RF | 3 | R8C5[1][A] | u_mac_rx_model/rx_frm_cnt_5_s1/Q |
| 1.521 | 0.006 | tNET | FF | 1 | R8C5[1][A] | u_mac_rx_model/n266_s6/I3 |
| 1.674 | 0.153 | tINS | FF | 1 | R8C5[1][A] | u_mac_rx_model/n266_s6/F |
| 1.674 | 0.000 | tNET | FF | 1 | R8C5[1][A] | u_mac_rx_model/rx_frm_cnt_5_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.374 | 1.374 | tNET | RR | 1 | R8C5[1][A] | u_mac_rx_model/rx_frm_cnt_5_s1/CLK |
| 1.399 | 0.025 | tHld | 1 | R8C5[1][A] | u_mac_rx_model/rx_frm_cnt_5_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.374, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.374, 100.000% |
Path25
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.670 |
| Data Required Time | 1.395 |
| From | u_mac_rx_model/rx_frm_cnt_11_s1 |
| To | u_mac_rx_model/rx_frm_cnt_11_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.370 | 1.370 | tNET | RR | 1 | R8C6[1][A] | u_mac_rx_model/rx_frm_cnt_11_s1/CLK |
| 1.511 | 0.141 | tC2Q | RF | 3 | R8C6[1][A] | u_mac_rx_model/rx_frm_cnt_11_s1/Q |
| 1.517 | 0.006 | tNET | FF | 1 | R8C6[1][A] | u_mac_rx_model/n260_s6/I3 |
| 1.670 | 0.153 | tINS | FF | 1 | R8C6[1][A] | u_mac_rx_model/n260_s6/F |
| 1.670 | 0.000 | tNET | FF | 1 | R8C6[1][A] | u_mac_rx_model/rx_frm_cnt_11_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.370 | 1.370 | tNET | RR | 1 | R8C6[1][A] | u_mac_rx_model/rx_frm_cnt_11_s1/CLK |
| 1.395 | 0.025 | tHld | 1 | R8C6[1][A] | u_mac_rx_model/rx_frm_cnt_11_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.370, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.370, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 6.811 |
| Data Arrival Time | 5.483 |
| Data Required Time | 12.294 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/rmii_rxd_d1_0_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.483 | 2.534 | tNET | FF | 1 | IOT9[B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/rmii_rxd_d1_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.641 | 1.959 | tNET | RR | 1 | IOT9[B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/rmii_rxd_d1_0_s0/CLK |
| 12.294 | -0.347 | tSu | 1 | IOT9[B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/rmii_rxd_d1_0_s0 |
Path Statistics:
| Clock Skew | 0.060 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.534, 87.334%; tC2Q: 0.368, 12.666% |
| Required Clock Path Delay | cell: 0.683, 25.840%; route: 1.959, 74.160% |
Path2
Path Summary:
| Slack | 6.811 |
| Data Arrival Time | 5.483 |
| Data Required Time | 12.294 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/rmii_rxd_d1_1_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.483 | 2.534 | tNET | FF | 1 | IOT21[B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/rmii_rxd_d1_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.641 | 1.959 | tNET | RR | 1 | IOT21[B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/rmii_rxd_d1_1_s0/CLK |
| 12.294 | -0.347 | tSu | 1 | IOT21[B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/rmii_rxd_d1_1_s0 |
Path Statistics:
| Clock Skew | 0.060 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.534, 87.334%; tC2Q: 0.368, 12.666% |
| Required Clock Path Delay | cell: 0.683, 25.840%; route: 1.959, 74.160% |
Path3
Path Summary:
| Slack | 6.815 |
| Data Arrival Time | 5.434 |
| Data Required Time | 12.249 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/mii_txd_tmp_3_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.434 | 2.485 | tNET | FF | 1 | R13C19[0][A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/mii_txd_tmp_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.596 | 1.914 | tNET | RR | 1 | R13C19[0][A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/mii_txd_tmp_3_s0/CLK |
| 12.249 | -0.347 | tSu | 1 | R13C19[0][A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/mii_txd_tmp_3_s0 |
Path Statistics:
| Clock Skew | 0.015 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.485, 87.118%; tC2Q: 0.368, 12.882% |
| Required Clock Path Delay | cell: 0.683, 26.288%; route: 1.914, 73.712% |
Path4
Path Summary:
| Slack | 6.821 |
| Data Arrival Time | 5.483 |
| Data Required Time | 12.303 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/rmii_txd_0_s2 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.483 | 2.534 | tNET | FF | 1 | IOT9[A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/rmii_txd_0_s2/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.651 | 1.968 | tNET | RR | 1 | IOT9[A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/rmii_txd_0_s2/CLK |
| 12.303 | -0.347 | tSu | 1 | IOT9[A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/rmii_txd_0_s2 |
Path Statistics:
| Clock Skew | 0.070 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.534, 87.334%; tC2Q: 0.368, 12.666% |
| Required Clock Path Delay | cell: 0.683, 25.749%; route: 1.968, 74.251% |
Path5
Path Summary:
| Slack | 6.821 |
| Data Arrival Time | 5.483 |
| Data Required Time | 12.303 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/rmii_txd_1_s3 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.483 | 2.534 | tNET | FF | 1 | IOT21[A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/rmii_txd_1_s3/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.651 | 1.968 | tNET | RR | 1 | IOT21[A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/rmii_txd_1_s3/CLK |
| 12.303 | -0.347 | tSu | 1 | IOT21[A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/rmii_txd_1_s3 |
Path Statistics:
| Clock Skew | 0.070 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.534, 87.334%; tC2Q: 0.368, 12.666% |
| Required Clock Path Delay | cell: 0.683, 25.749%; route: 1.968, 74.251% |
Path6
Path Summary:
| Slack | 6.821 |
| Data Arrival Time | 5.483 |
| Data Required Time | 12.303 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/rmii_tx_en_s2 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.483 | 2.534 | tNET | FF | 1 | IOT33[A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/rmii_tx_en_s2/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.651 | 1.968 | tNET | RR | 1 | IOT33[A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/rmii_tx_en_s2/CLK |
| 12.303 | -0.347 | tSu | 1 | IOT33[A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/rmii_tx_en_s2 |
Path Statistics:
| Clock Skew | 0.070 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.534, 87.334%; tC2Q: 0.368, 12.666% |
| Required Clock Path Delay | cell: 0.683, 25.749%; route: 1.968, 74.251% |
Path7
Path Summary:
| Slack | 6.822 |
| Data Arrival Time | 5.468 |
| Data Required Time | 12.291 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/rmii_rx_crs_dv_d1_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.468 | 2.520 | tNET | FF | 1 | IOL5[B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/rmii_rx_crs_dv_d1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.638 | 1.956 | tNET | RR | 1 | IOL5[B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/rmii_rx_crs_dv_d1_s0/CLK |
| 12.291 | -0.347 | tSu | 1 | IOL5[B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/rmii_rx_crs_dv_d1_s0 |
Path Statistics:
| Clock Skew | 0.057 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.520, 87.273%; tC2Q: 0.368, 12.727% |
| Required Clock Path Delay | cell: 0.683, 25.871%; route: 1.956, 74.129% |
Path8
Path Summary:
| Slack | 6.824 |
| Data Arrival Time | 5.440 |
| Data Required Time | 12.264 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rxd_0_s1 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.440 | 2.491 | tNET | FF | 1 | R14C20[0][A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rxd_0_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.612 | 1.929 | tNET | RR | 1 | R14C20[0][A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rxd_0_s1/CLK |
| 12.264 | -0.347 | tSu | 1 | R14C20[0][A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rxd_0_s1 |
Path Statistics:
| Clock Skew | 0.031 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.491, 87.145%; tC2Q: 0.368, 12.855% |
| Required Clock Path Delay | cell: 0.683, 26.134%; route: 1.929, 73.866% |
Path9
Path Summary:
| Slack | 6.824 |
| Data Arrival Time | 5.440 |
| Data Required Time | 12.264 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rxd_1_s1 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.440 | 2.491 | tNET | FF | 1 | R14C20[0][B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rxd_1_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.612 | 1.929 | tNET | RR | 1 | R14C20[0][B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rxd_1_s1/CLK |
| 12.264 | -0.347 | tSu | 1 | R14C20[0][B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rxd_1_s1 |
Path Statistics:
| Clock Skew | 0.031 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.491, 87.145%; tC2Q: 0.368, 12.855% |
| Required Clock Path Delay | cell: 0.683, 26.134%; route: 1.929, 73.866% |
Path10
Path Summary:
| Slack | 6.824 |
| Data Arrival Time | 5.434 |
| Data Required Time | 12.258 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rxd_3_s2 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.434 | 2.485 | tNET | FF | 1 | R13C20[1][A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rxd_3_s2/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.606 | 1.923 | tNET | RR | 1 | R13C20[1][A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rxd_3_s2/CLK |
| 12.258 | -0.347 | tSu | 1 | R13C20[1][A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rxd_3_s2 |
Path Statistics:
| Clock Skew | 0.025 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.485, 87.118%; tC2Q: 0.368, 12.882% |
| Required Clock Path Delay | cell: 0.683, 26.193%; route: 1.923, 73.807% |
Path11
Path Summary:
| Slack | 6.824 |
| Data Arrival Time | 5.440 |
| Data Required Time | 12.264 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/di_bits_data_0_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.440 | 2.491 | tNET | FF | 1 | R14C20[1][A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/di_bits_data_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.612 | 1.929 | tNET | RR | 1 | R14C20[1][A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/di_bits_data_0_s0/CLK |
| 12.264 | -0.347 | tSu | 1 | R14C20[1][A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/di_bits_data_0_s0 |
Path Statistics:
| Clock Skew | 0.031 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.491, 87.145%; tC2Q: 0.368, 12.855% |
| Required Clock Path Delay | cell: 0.683, 26.134%; route: 1.929, 73.866% |
Path12
Path Summary:
| Slack | 6.824 |
| Data Arrival Time | 5.440 |
| Data Required Time | 12.264 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/di_bits_data_1_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.440 | 2.491 | tNET | FF | 1 | R14C20[1][B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/di_bits_data_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.612 | 1.929 | tNET | RR | 1 | R14C20[1][B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/di_bits_data_1_s0/CLK |
| 12.264 | -0.347 | tSu | 1 | R14C20[1][B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/di_bits_data_1_s0 |
Path Statistics:
| Clock Skew | 0.031 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.491, 87.145%; tC2Q: 0.368, 12.855% |
| Required Clock Path Delay | cell: 0.683, 26.134%; route: 1.929, 73.866% |
Path13
Path Summary:
| Slack | 6.824 |
| Data Arrival Time | 5.440 |
| Data Required Time | 12.264 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/di_bits_data_2_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.440 | 2.491 | tNET | FF | 1 | R14C20[2][B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/di_bits_data_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.612 | 1.929 | tNET | RR | 1 | R14C20[2][B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/di_bits_data_2_s0/CLK |
| 12.264 | -0.347 | tSu | 1 | R14C20[2][B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/di_bits_data_2_s0 |
Path Statistics:
| Clock Skew | 0.031 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.491, 87.145%; tC2Q: 0.368, 12.855% |
| Required Clock Path Delay | cell: 0.683, 26.134%; route: 1.929, 73.866% |
Path14
Path Summary:
| Slack | 6.824 |
| Data Arrival Time | 5.440 |
| Data Required Time | 12.264 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/di_bits_data_3_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.440 | 2.491 | tNET | FF | 1 | R14C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/di_bits_data_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.612 | 1.929 | tNET | RR | 1 | R14C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/di_bits_data_3_s0/CLK |
| 12.264 | -0.347 | tSu | 1 | R14C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/di_bits_data_3_s0 |
Path Statistics:
| Clock Skew | 0.031 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.491, 87.145%; tC2Q: 0.368, 12.855% |
| Required Clock Path Delay | cell: 0.683, 26.134%; route: 1.929, 73.866% |
Path15
Path Summary:
| Slack | 6.824 |
| Data Arrival Time | 5.434 |
| Data Required Time | 12.258 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/mii_txd_tmp_1_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.434 | 2.485 | tNET | FF | 1 | R13C20[1][B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/mii_txd_tmp_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.606 | 1.923 | tNET | RR | 1 | R13C20[1][B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/mii_txd_tmp_1_s0/CLK |
| 12.258 | -0.347 | tSu | 1 | R13C20[1][B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/mii_txd_tmp_1_s0 |
Path Statistics:
| Clock Skew | 0.025 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.485, 87.118%; tC2Q: 0.368, 12.882% |
| Required Clock Path Delay | cell: 0.683, 26.193%; route: 1.923, 73.807% |
Path16
Path Summary:
| Slack | 6.824 |
| Data Arrival Time | 5.428 |
| Data Required Time | 12.252 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.428 | 2.479 | tNET | FF | 1 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.600 | 1.917 | tNET | RR | 1 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/CLK |
| 12.252 | -0.347 | tSu | 1 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3 |
Path Statistics:
| Clock Skew | 0.019 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.479, 87.091%; tC2Q: 0.368, 12.909% |
| Required Clock Path Delay | cell: 0.683, 26.253%; route: 1.917, 73.747% |
Path17
Path Summary:
| Slack | 6.824 |
| Data Arrival Time | 5.428 |
| Data Required Time | 12.252 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_4_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.428 | 2.479 | tNET | FF | 1 | R12C20[0][B] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_4_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.600 | 1.917 | tNET | RR | 1 | R12C20[0][B] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_4_s0/CLK |
| 12.252 | -0.347 | tSu | 1 | R12C20[0][B] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_4_s0 |
Path Statistics:
| Clock Skew | 0.019 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.479, 87.091%; tC2Q: 0.368, 12.909% |
| Required Clock Path Delay | cell: 0.683, 26.253%; route: 1.917, 73.747% |
Path18
Path Summary:
| Slack | 6.824 |
| Data Arrival Time | 5.434 |
| Data Required Time | 12.258 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_0_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.434 | 2.485 | tNET | FF | 1 | R13C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.606 | 1.923 | tNET | RR | 1 | R13C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_0_s0/CLK |
| 12.258 | -0.347 | tSu | 1 | R13C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_0_s0 |
Path Statistics:
| Clock Skew | 0.025 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.485, 87.118%; tC2Q: 0.368, 12.882% |
| Required Clock Path Delay | cell: 0.683, 26.193%; route: 1.923, 73.807% |
Path19
Path Summary:
| Slack | 6.824 |
| Data Arrival Time | 5.434 |
| Data Required Time | 12.258 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_1_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.434 | 2.485 | tNET | FF | 1 | R13C20[2][B] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.606 | 1.923 | tNET | RR | 1 | R13C20[2][B] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_1_s0/CLK |
| 12.258 | -0.347 | tSu | 1 | R13C20[2][B] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_1_s0 |
Path Statistics:
| Clock Skew | 0.025 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.485, 87.118%; tC2Q: 0.368, 12.882% |
| Required Clock Path Delay | cell: 0.683, 26.193%; route: 1.923, 73.807% |
Path20
Path Summary:
| Slack | 6.824 |
| Data Arrival Time | 5.428 |
| Data Required Time | 12.252 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_2_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.428 | 2.479 | tNET | FF | 1 | R12C20[1][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.600 | 1.917 | tNET | RR | 1 | R12C20[1][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_2_s0/CLK |
| 12.252 | -0.347 | tSu | 1 | R12C20[1][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_2_s0 |
Path Statistics:
| Clock Skew | 0.019 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.479, 87.091%; tC2Q: 0.368, 12.909% |
| Required Clock Path Delay | cell: 0.683, 26.253%; route: 1.917, 73.747% |
Path21
Path Summary:
| Slack | 6.824 |
| Data Arrival Time | 5.428 |
| Data Required Time | 12.252 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_3_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.428 | 2.479 | tNET | FF | 1 | R12C20[0][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.600 | 1.917 | tNET | RR | 1 | R12C20[0][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_3_s0/CLK |
| 12.252 | -0.347 | tSu | 1 | R12C20[0][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_cnt_3_s0 |
Path Statistics:
| Clock Skew | 0.019 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.479, 87.091%; tC2Q: 0.368, 12.909% |
| Required Clock Path Delay | cell: 0.683, 26.253%; route: 1.917, 73.747% |
Path22
Path Summary:
| Slack | 6.827 |
| Data Arrival Time | 5.454 |
| Data Required Time | 12.281 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/mii_tx_en_tmp_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.454 | 2.506 | tNET | FF | 1 | R8C21[0][B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/mii_tx_en_tmp_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.628 | 1.946 | tNET | RR | 1 | R8C21[0][B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/mii_tx_en_tmp_s0/CLK |
| 12.281 | -0.347 | tSu | 1 | R8C21[0][B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/mii_tx_en_tmp_s0 |
Path Statistics:
| Clock Skew | 0.048 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.506, 87.209%; tC2Q: 0.368, 12.791% |
| Required Clock Path Delay | cell: 0.683, 25.966%; route: 1.946, 74.034% |
Path23
Path Summary:
| Slack | 6.827 |
| Data Arrival Time | 5.447 |
| Data Required Time | 12.274 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/mii_txd_tmp_0_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.447 | 2.498 | tNET | FF | 1 | R9C19[0][A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/mii_txd_tmp_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.621 | 1.939 | tNET | RR | 1 | R9C19[0][A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/mii_txd_tmp_0_s0/CLK |
| 12.274 | -0.347 | tSu | 1 | R9C19[0][A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_tx/mii_txd_tmp_0_s0 |
Path Statistics:
| Clock Skew | 0.040 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.498, 87.177%; tC2Q: 0.368, 12.823% |
| Required Clock Path Delay | cell: 0.683, 26.037%; route: 1.939, 73.963% |
Path24
Path Summary:
| Slack | 6.828 |
| Data Arrival Time | 5.442 |
| Data Required Time | 12.270 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rx_dv_s2 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.442 | 2.493 | tNET | FF | 1 | R15C20[1][B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rx_dv_s2/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.618 | 1.935 | tNET | RR | 1 | R15C20[1][B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rx_dv_s2/CLK |
| 12.270 | -0.347 | tSu | 1 | R15C20[1][B] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rx_dv_s2 |
Path Statistics:
| Clock Skew | 0.037 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.493, 87.153%; tC2Q: 0.368, 12.847% |
| Required Clock Path Delay | cell: 0.683, 26.074%; route: 1.935, 73.925% |
Path25
Path Summary:
| Slack | 6.828 |
| Data Arrival Time | 5.442 |
| Data Required Time | 12.270 |
| From | rstn_ip_s0 |
| To | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rxd_2_s1 |
| Launch Clk | refclk:[R] |
| Latch Clk | refclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 2.581 | 1.898 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 2.948 | 0.368 | tC2Q | RF | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 5.442 | 2.493 | tNET | FF | 1 | R15C20[1][A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rxd_2_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | refclk | ||||
| 10.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 12.618 | 1.935 | tNET | RR | 1 | R15C20[1][A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rxd_2_s1/CLK |
| 12.270 | -0.347 | tSu | 1 | R15C20[1][A] | u_mii_to_rmii_top/u_rmii_txrx/u_rmii_rx/mii_rxd_2_s1 |
Path Statistics:
| Clock Skew | 0.037 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.493, 87.153%; tC2Q: 0.368, 12.847% |
| Required Clock Path Delay | cell: 0.683, 26.074%; route: 1.935, 73.925% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 1.162 |
| Data Arrival Time | 2.503 |
| Data Required Time | 1.341 |
| From | rstn_ip_s0 |
| To | u_mac_rx_model/rx_cnt_19_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.503 | 1.003 | tNET | RR | 1 | R11C9[0][A] | u_mac_rx_model/rx_cnt_19_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.359 | 1.359 | tNET | RR | 1 | R11C9[0][A] | u_mac_rx_model/rx_cnt_19_s0/CLK |
| 1.394 | 0.035 | tUnc | u_mac_rx_model/rx_cnt_19_s0 | |||
| 1.341 | -0.053 | tHld | 1 | R11C9[0][A] | u_mac_rx_model/rx_cnt_19_s0 |
Path Statistics:
| Clock Skew | 0.003 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.003, 87.446%; tC2Q: 0.144, 12.554% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.359, 100.000% |
Path2
Path Summary:
| Slack | 1.162 |
| Data Arrival Time | 2.503 |
| Data Required Time | 1.341 |
| From | rstn_ip_s0 |
| To | u_mac_rx_model/rx_cnt_20_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.503 | 1.003 | tNET | RR | 1 | R11C9[0][B] | u_mac_rx_model/rx_cnt_20_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.359 | 1.359 | tNET | RR | 1 | R11C9[0][B] | u_mac_rx_model/rx_cnt_20_s0/CLK |
| 1.394 | 0.035 | tUnc | u_mac_rx_model/rx_cnt_20_s0 | |||
| 1.341 | -0.053 | tHld | 1 | R11C9[0][B] | u_mac_rx_model/rx_cnt_20_s0 |
Path Statistics:
| Clock Skew | 0.003 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.003, 87.446%; tC2Q: 0.144, 12.554% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.359, 100.000% |
Path3
Path Summary:
| Slack | 1.162 |
| Data Arrival Time | 2.503 |
| Data Required Time | 1.341 |
| From | rstn_ip_s0 |
| To | u_mac_rx_model/rx_cnt_21_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.503 | 1.003 | tNET | RR | 1 | R11C9[1][A] | u_mac_rx_model/rx_cnt_21_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.359 | 1.359 | tNET | RR | 1 | R11C9[1][A] | u_mac_rx_model/rx_cnt_21_s0/CLK |
| 1.394 | 0.035 | tUnc | u_mac_rx_model/rx_cnt_21_s0 | |||
| 1.341 | -0.053 | tHld | 1 | R11C9[1][A] | u_mac_rx_model/rx_cnt_21_s0 |
Path Statistics:
| Clock Skew | 0.003 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.003, 87.446%; tC2Q: 0.144, 12.554% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.359, 100.000% |
Path4
Path Summary:
| Slack | 1.162 |
| Data Arrival Time | 2.503 |
| Data Required Time | 1.341 |
| From | rstn_ip_s0 |
| To | u_mac_rx_model/rx_cnt_22_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.503 | 1.003 | tNET | RR | 1 | R11C9[1][B] | u_mac_rx_model/rx_cnt_22_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.359 | 1.359 | tNET | RR | 1 | R11C9[1][B] | u_mac_rx_model/rx_cnt_22_s0/CLK |
| 1.394 | 0.035 | tUnc | u_mac_rx_model/rx_cnt_22_s0 | |||
| 1.341 | -0.053 | tHld | 1 | R11C9[1][B] | u_mac_rx_model/rx_cnt_22_s0 |
Path Statistics:
| Clock Skew | 0.003 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.003, 87.446%; tC2Q: 0.144, 12.554% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.359, 100.000% |
Path5
Path Summary:
| Slack | 1.162 |
| Data Arrival Time | 2.503 |
| Data Required Time | 1.341 |
| From | rstn_ip_s0 |
| To | u_mac_rx_model/rx_cnt_23_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.503 | 1.003 | tNET | RR | 1 | R11C9[2][A] | u_mac_rx_model/rx_cnt_23_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.359 | 1.359 | tNET | RR | 1 | R11C9[2][A] | u_mac_rx_model/rx_cnt_23_s0/CLK |
| 1.394 | 0.035 | tUnc | u_mac_rx_model/rx_cnt_23_s0 | |||
| 1.341 | -0.053 | tHld | 1 | R11C9[2][A] | u_mac_rx_model/rx_cnt_23_s0 |
Path Statistics:
| Clock Skew | 0.003 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.003, 87.446%; tC2Q: 0.144, 12.554% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.359, 100.000% |
Path6
Path Summary:
| Slack | 1.162 |
| Data Arrival Time | 2.503 |
| Data Required Time | 1.341 |
| From | rstn_ip_s0 |
| To | u_mac_rx_model/rx_cnt_24_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.503 | 1.003 | tNET | RR | 1 | R11C9[2][B] | u_mac_rx_model/rx_cnt_24_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.359 | 1.359 | tNET | RR | 1 | R11C9[2][B] | u_mac_rx_model/rx_cnt_24_s0/CLK |
| 1.394 | 0.035 | tUnc | u_mac_rx_model/rx_cnt_24_s0 | |||
| 1.341 | -0.053 | tHld | 1 | R11C9[2][B] | u_mac_rx_model/rx_cnt_24_s0 |
Path Statistics:
| Clock Skew | 0.003 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.003, 87.446%; tC2Q: 0.144, 12.554% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.359, 100.000% |
Path7
Path Summary:
| Slack | 1.162 |
| Data Arrival Time | 2.503 |
| Data Required Time | 1.341 |
| From | rstn_ip_s0 |
| To | u_mac_rx_model/rx_statistics_length_check_64_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.503 | 1.003 | tNET | RR | 1 | R11C13[3][A] | u_mac_rx_model/rx_statistics_length_check_64_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.359 | 1.359 | tNET | RR | 1 | R11C13[3][A] | u_mac_rx_model/rx_statistics_length_check_64_s0/CLK |
| 1.394 | 0.035 | tUnc | u_mac_rx_model/rx_statistics_length_check_64_s0 | |||
| 1.341 | -0.053 | tHld | 1 | R11C13[3][A] | u_mac_rx_model/rx_statistics_length_check_64_s0 |
Path Statistics:
| Clock Skew | 0.003 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.003, 87.446%; tC2Q: 0.144, 12.554% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.359, 100.000% |
Path8
Path Summary:
| Slack | 1.162 |
| Data Arrival Time | 2.503 |
| Data Required Time | 1.341 |
| From | rstn_ip_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_latch_18_s3 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.503 | 1.003 | tNET | RR | 1 | R11C29[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_latch_18_s3/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.359 | 1.359 | tNET | RR | 1 | R11C29[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_latch_18_s3/CLK |
| 1.394 | 0.035 | tUnc | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_latch_18_s3 | |||
| 1.341 | -0.053 | tHld | 1 | R11C29[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_latch_18_s3 |
Path Statistics:
| Clock Skew | 0.003 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.003, 87.446%; tC2Q: 0.144, 12.554% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.359, 100.000% |
Path9
Path Summary:
| Slack | 1.162 |
| Data Arrival Time | 2.503 |
| Data Required Time | 1.341 |
| From | rstn_ip_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg2_18_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.503 | 1.003 | tNET | RR | 1 | R11C29[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg2_18_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.359 | 1.359 | tNET | RR | 1 | R11C29[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg2_18_s0/CLK |
| 1.394 | 0.035 | tUnc | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg2_18_s0 | |||
| 1.341 | -0.053 | tHld | 1 | R11C29[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg2_18_s0 |
Path Statistics:
| Clock Skew | 0.003 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.003, 87.446%; tC2Q: 0.144, 12.554% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.359, 100.000% |
Path10
Path Summary:
| Slack | 1.162 |
| Data Arrival Time | 2.503 |
| Data Required Time | 1.341 |
| From | rstn_ip_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg1_18_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.503 | 1.003 | tNET | RR | 1 | R11C29[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg1_18_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.359 | 1.359 | tNET | RR | 1 | R11C29[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg1_18_s0/CLK |
| 1.394 | 0.035 | tUnc | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg1_18_s0 | |||
| 1.341 | -0.053 | tHld | 1 | R11C29[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg1_18_s0 |
Path Statistics:
| Clock Skew | 0.003 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.003, 87.446%; tC2Q: 0.144, 12.554% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.359, 100.000% |
Path11
Path Summary:
| Slack | 1.166 |
| Data Arrival Time | 2.517 |
| Data Required Time | 1.351 |
| From | rstn_ip_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_6_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.517 | 1.017 | tNET | RR | 1 | R9C13[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_6_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.369 | 1.369 | tNET | RR | 1 | R9C13[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_6_s0/CLK |
| 1.404 | 0.035 | tUnc | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_6_s0 | |||
| 1.351 | -0.053 | tHld | 1 | R9C13[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_6_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.017, 87.597%; tC2Q: 0.144, 12.403% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.369, 100.000% |
Path12
Path Summary:
| Slack | 1.166 |
| Data Arrival Time | 2.517 |
| Data Required Time | 1.351 |
| From | rstn_ip_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_3_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.517 | 1.017 | tNET | RR | 1 | R9C13[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.369 | 1.369 | tNET | RR | 1 | R9C13[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_3_s0/CLK |
| 1.404 | 0.035 | tUnc | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_3_s0 | |||
| 1.351 | -0.053 | tHld | 1 | R9C13[0][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_3_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.017, 87.597%; tC2Q: 0.144, 12.403% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.369, 100.000% |
Path13
Path Summary:
| Slack | 1.166 |
| Data Arrival Time | 2.517 |
| Data Required Time | 1.351 |
| From | rstn_ip_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_2_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.517 | 1.017 | tNET | RR | 1 | R9C13[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.369 | 1.369 | tNET | RR | 1 | R9C13[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_2_s0/CLK |
| 1.404 | 0.035 | tUnc | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_2_s0 | |||
| 1.351 | -0.053 | tHld | 1 | R9C13[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_2_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.017, 87.597%; tC2Q: 0.144, 12.403% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.369, 100.000% |
Path14
Path Summary:
| Slack | 1.166 |
| Data Arrival Time | 2.517 |
| Data Required Time | 1.351 |
| From | rstn_ip_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_1_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.517 | 1.017 | tNET | RR | 1 | R9C13[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.369 | 1.369 | tNET | RR | 1 | R9C13[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_1_s0/CLK |
| 1.404 | 0.035 | tUnc | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_1_s0 | |||
| 1.351 | -0.053 | tHld | 1 | R9C13[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_col_reg_1_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.017, 87.597%; tC2Q: 0.144, 12.403% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.369, 100.000% |
Path15
Path Summary:
| Slack | 1.166 |
| Data Arrival Time | 2.517 |
| Data Required Time | 1.351 |
| From | rstn_ip_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_3_s1 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.517 | 1.017 | tNET | RR | 1 | R9C17[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_3_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.369 | 1.369 | tNET | RR | 1 | R9C17[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_3_s1/CLK |
| 1.404 | 0.035 | tUnc | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_3_s1 | |||
| 1.351 | -0.053 | tHld | 1 | R9C17[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_3_s1 |
Path Statistics:
| Clock Skew | 0.013 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.017, 87.597%; tC2Q: 0.144, 12.403% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.369, 100.000% |
Path16
Path Summary:
| Slack | 1.166 |
| Data Arrival Time | 2.517 |
| Data Required Time | 1.351 |
| From | rstn_ip_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_2_s1 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.517 | 1.017 | tNET | RR | 1 | R9C17[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_2_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.369 | 1.369 | tNET | RR | 1 | R9C17[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_2_s1/CLK |
| 1.404 | 0.035 | tUnc | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_2_s1 | |||
| 1.351 | -0.053 | tHld | 1 | R9C17[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_2_s1 |
Path Statistics:
| Clock Skew | 0.013 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.017, 87.597%; tC2Q: 0.144, 12.403% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.369, 100.000% |
Path17
Path Summary:
| Slack | 1.166 |
| Data Arrival Time | 2.517 |
| Data Required Time | 1.351 |
| From | rstn_ip_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_15_s4 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.517 | 1.017 | tNET | RR | 1 | R9C17[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_15_s4/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.369 | 1.369 | tNET | RR | 1 | R9C17[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_15_s4/CLK |
| 1.404 | 0.035 | tUnc | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_15_s4 | |||
| 1.351 | -0.053 | tHld | 1 | R9C17[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_15_s4 |
Path Statistics:
| Clock Skew | 0.013 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.017, 87.597%; tC2Q: 0.144, 12.403% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.369, 100.000% |
Path18
Path Summary:
| Slack | 1.166 |
| Data Arrival Time | 2.517 |
| Data Required Time | 1.351 |
| From | rstn_ip_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_4_s3 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.517 | 1.017 | tNET | RR | 1 | R9C17[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_4_s3/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.369 | 1.369 | tNET | RR | 1 | R9C17[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_4_s3/CLK |
| 1.404 | 0.035 | tUnc | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_4_s3 | |||
| 1.351 | -0.053 | tHld | 1 | R9C17[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_rx_ctrl/rx_frm_lgt_reg_4_s3 |
Path Statistics:
| Clock Skew | 0.013 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.017, 87.597%; tC2Q: 0.144, 12.403% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.369, 100.000% |
Path19
Path Summary:
| Slack | 1.166 |
| Data Arrival Time | 2.517 |
| Data Required Time | 1.351 |
| From | rstn_ip_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg1_40_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.517 | 1.017 | tNET | RR | 1 | R9C25[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg1_40_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.369 | 1.369 | tNET | RR | 1 | R9C25[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg1_40_s0/CLK |
| 1.404 | 0.035 | tUnc | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg1_40_s0 | |||
| 1.351 | -0.053 | tHld | 1 | R9C25[1][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg1_40_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.017, 87.597%; tC2Q: 0.144, 12.403% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.369, 100.000% |
Path20
Path Summary:
| Slack | 1.166 |
| Data Arrival Time | 2.517 |
| Data Required Time | 1.351 |
| From | rstn_ip_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_val_reg1_8_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.517 | 1.017 | tNET | RR | 1 | R9C25[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_val_reg1_8_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.369 | 1.369 | tNET | RR | 1 | R9C25[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_val_reg1_8_s0/CLK |
| 1.404 | 0.035 | tUnc | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_val_reg1_8_s0 | |||
| 1.351 | -0.053 | tHld | 1 | R9C25[2][B] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_val_reg1_8_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.017, 87.597%; tC2Q: 0.144, 12.403% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.369, 100.000% |
Path21
Path Summary:
| Slack | 1.166 |
| Data Arrival Time | 2.517 |
| Data Required Time | 1.351 |
| From | rstn_ip_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg2_40_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.517 | 1.017 | tNET | RR | 1 | R9C25[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg2_40_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.369 | 1.369 | tNET | RR | 1 | R9C25[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg2_40_s0/CLK |
| 1.404 | 0.035 | tUnc | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg2_40_s0 | |||
| 1.351 | -0.053 | tHld | 1 | R9C25[2][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_source_addr_reg2_40_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.017, 87.597%; tC2Q: 0.144, 12.403% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.369, 100.000% |
Path22
Path Summary:
| Slack | 1.166 |
| Data Arrival Time | 2.517 |
| Data Required Time | 1.351 |
| From | rstn_ip_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_val_reg2_8_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.517 | 1.017 | tNET | RR | 1 | R9C25[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_val_reg2_8_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.369 | 1.369 | tNET | RR | 1 | R9C25[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_val_reg2_8_s0/CLK |
| 1.404 | 0.035 | tUnc | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_val_reg2_8_s0 | |||
| 1.351 | -0.053 | tHld | 1 | R9C25[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/tx_pause_val_reg2_8_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.017, 87.597%; tC2Q: 0.144, 12.403% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.369, 100.000% |
Path23
Path Summary:
| Slack | 1.166 |
| Data Arrival Time | 2.517 |
| Data Required Time | 1.351 |
| From | rstn_ip_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/jam_cnt_1_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.517 | 1.017 | tNET | RR | 1 | R9C21[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/jam_cnt_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.369 | 1.369 | tNET | RR | 1 | R9C21[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/jam_cnt_1_s0/CLK |
| 1.404 | 0.035 | tUnc | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/jam_cnt_1_s0 | |||
| 1.351 | -0.053 | tHld | 1 | R9C21[1][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/jam_cnt_1_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.017, 87.597%; tC2Q: 0.144, 12.403% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.369, 100.000% |
Path24
Path Summary:
| Slack | 1.166 |
| Data Arrival Time | 2.517 |
| Data Required Time | 1.351 |
| From | rstn_ip_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/jam_cnt_0_s0 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.517 | 1.017 | tNET | RR | 1 | R9C21[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/jam_cnt_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.369 | 1.369 | tNET | RR | 1 | R9C21[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/jam_cnt_0_s0/CLK |
| 1.404 | 0.035 | tUnc | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/jam_cnt_0_s0 | |||
| 1.351 | -0.053 | tHld | 1 | R9C21[3][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/jam_cnt_0_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.017, 87.597%; tC2Q: 0.144, 12.403% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.369, 100.000% |
Path25
Path Summary:
| Slack | 1.166 |
| Data Arrival Time | 2.517 |
| Data Required Time | 1.351 |
| From | rstn_ip_s0 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pad_s8 |
| Launch Clk | refclk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | refclk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL5[A] | refclk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 56 | IOL5[A] | refclk_ibuf/O |
| 1.356 | 0.681 | tNET | RR | 1 | R12C18[1][A] | rstn_ip_s0/CLK |
| 1.500 | 0.144 | tC2Q | RR | 1321 | R12C18[1][A] | rstn_ip_s0/Q |
| 2.517 | 1.017 | tNET | RR | 1 | R9C21[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pad_s8/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1284 | R12C20[2][A] | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 1.369 | 1.369 | tNET | RR | 1 | R9C21[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pad_s8/CLK |
| 1.404 | 0.035 | tUnc | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pad_s8 | |||
| 1.351 | -0.053 | tHld | 1 | R9C21[0][A] | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pad_s8 |
Path Statistics:
| Clock Skew | 0.013 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.017, 87.597%; tC2Q: 0.144, 12.403% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.369, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
| Slack: | 2.890 |
| Actual Width: | 3.140 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | tx_mac_clk |
| Objects: | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_21_s1 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | tx_mac_clk | ||
| 5.000 | 0.000 | tCL | FF | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 8.248 | 3.248 | tNET | FF | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_21_s1/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | tx_mac_clk | ||
| 10.000 | 0.000 | tCL | RR | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 11.388 | 1.388 | tNET | RR | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_21_s1/CLK |
MPW2
MPW Summary:
| Slack: | 2.890 |
| Actual Width: | 3.140 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | tx_mac_clk |
| Objects: | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_13_s1 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | tx_mac_clk | ||
| 5.000 | 0.000 | tCL | FF | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 8.248 | 3.248 | tNET | FF | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_13_s1/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | tx_mac_clk | ||
| 10.000 | 0.000 | tCL | RR | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 11.388 | 1.388 | tNET | RR | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_13_s1/CLK |
MPW3
MPW Summary:
| Slack: | 2.890 |
| Actual Width: | 3.140 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | tx_mac_clk |
| Objects: | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_3_s1 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | tx_mac_clk | ||
| 5.000 | 0.000 | tCL | FF | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 8.248 | 3.248 | tNET | FF | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_3_s1/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | tx_mac_clk | ||
| 10.000 | 0.000 | tCL | RR | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 11.388 | 1.388 | tNET | RR | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_3_s1/CLK |
MPW4
MPW Summary:
| Slack: | 2.890 |
| Actual Width: | 3.140 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | tx_mac_clk |
| Objects: | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_2_s1 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | tx_mac_clk | ||
| 5.000 | 0.000 | tCL | FF | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 8.248 | 3.248 | tNET | FF | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_2_s1/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | tx_mac_clk | ||
| 10.000 | 0.000 | tCL | RR | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 11.388 | 1.388 | tNET | RR | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_2_s1/CLK |
MPW5
MPW Summary:
| Slack: | 2.890 |
| Actual Width: | 3.140 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | tx_mac_clk |
| Objects: | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_lfsr/z_reg_14_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | tx_mac_clk | ||
| 5.000 | 0.000 | tCL | FF | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 8.248 | 3.248 | tNET | FF | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_lfsr/z_reg_14_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | tx_mac_clk | ||
| 10.000 | 0.000 | tCL | RR | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 11.388 | 1.388 | tNET | RR | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_lfsr/z_reg_14_s0/CLK |
MPW6
MPW Summary:
| Slack: | 2.890 |
| Actual Width: | 3.140 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | tx_mac_clk |
| Objects: | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_lfsr/z_reg_2_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | tx_mac_clk | ||
| 5.000 | 0.000 | tCL | FF | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 8.248 | 3.248 | tNET | FF | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_lfsr/z_reg_2_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | tx_mac_clk | ||
| 10.000 | 0.000 | tCL | RR | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 11.388 | 1.388 | tNET | RR | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_lfsr/z_reg_2_s0/CLK |
MPW7
MPW Summary:
| Slack: | 2.890 |
| Actual Width: | 3.140 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | tx_mac_clk |
| Objects: | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_lfsr/z_reg_9_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | tx_mac_clk | ||
| 5.000 | 0.000 | tCL | FF | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 8.248 | 3.248 | tNET | FF | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_lfsr/z_reg_9_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | tx_mac_clk | ||
| 10.000 | 0.000 | tCL | RR | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 11.388 | 1.388 | tNET | RR | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_lfsr/z_reg_9_s0/CLK |
MPW8
MPW Summary:
| Slack: | 2.890 |
| Actual Width: | 3.140 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | tx_mac_clk |
| Objects: | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_lfsr/z_reg_5_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | tx_mac_clk | ||
| 5.000 | 0.000 | tCL | FF | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 8.248 | 3.248 | tNET | FF | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_lfsr/z_reg_5_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | tx_mac_clk | ||
| 10.000 | 0.000 | tCL | RR | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 11.388 | 1.388 | tNET | RR | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_lfsr/z_reg_5_s0/CLK |
MPW9
MPW Summary:
| Slack: | 2.890 |
| Actual Width: | 3.140 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | tx_mac_clk |
| Objects: | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_1_s1 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | tx_mac_clk | ||
| 5.000 | 0.000 | tCL | FF | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 8.248 | 3.248 | tNET | FF | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_1_s1/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | tx_mac_clk | ||
| 10.000 | 0.000 | tCL | RR | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 11.388 | 1.388 | tNET | RR | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_1_s1/CLK |
MPW10
MPW Summary:
| Slack: | 2.890 |
| Actual Width: | 3.140 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | tx_mac_clk |
| Objects: | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_31_s1 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | tx_mac_clk | ||
| 5.000 | 0.000 | tCL | FF | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 8.248 | 3.248 | tNET | FF | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_31_s1/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | tx_mac_clk | ||
| 10.000 | 0.000 | tCL | RR | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 11.388 | 1.388 | tNET | RR | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_31_s1/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
| FANOUT | NET NAME | WORST SLACK | MAX DELAY |
|---|---|---|---|
| 1284 | tx_mac_clk | 1.518 | 3.299 |
| 125 | latch_data_end | 7.608 | 1.570 |
| 123 | rx_mac_valid_d1 | 6.325 | 1.830 |
| 81 | latch_data_end | 6.543 | 2.177 |
| 76 | hd_state_enable | 7.138 | 1.932 |
| 70 | clk_tx_ena_int | 1.518 | 2.712 |
| 67 | tx_pause_req_reg2 | 7.016 | 1.195 |
| 65 | shift_reg_111_10 | 5.966 | 1.420 |
| 56 | refclk_d | 6.121 | 1.969 |
| 56 | rx_dv_reg[0] | 6.493 | 2.646 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
| GRID LOC | ROUTE CONGESTIONS |
|---|---|
| R7C22 | 48.61% |
| R5C17 | 43.06% |
| R4C22 | 43.06% |
| R6C22 | 43.06% |
| R14C5 | 41.67% |
| R6C21 | 41.67% |
| R5C22 | 40.28% |
| R7C21 | 40.28% |
| R5C28 | 38.89% |
| R5C18 | 37.50% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
| SDC Command Type | State | Detail Command |
|---|---|---|
| TC_CLOCK | Actived | create_clock -name refclk -period 10 -waveform {0 5} [get_ports {refclk}] |
| TC_CLOCK | Actived | create_clock -name tx_mac_clk -period 10 -waveform {0 5} [get_nets {tx_mac_clk}] |