Attention, please: 
	1. to PSRAM simulation model,please contact to FAE.
	2. for quickly simulation, please select "Simulation",which in the IP Core Generator->PSRAM Memory Interface HS GUI
	3. if you reconfig the ip parameters,which reload the psram_memory_interface.ipc and re-generator. 
	   please attention bits width of the psram_syn_top.v ,psram_test.v and tb.v file. for example, in the tb.v:
	   	O_ck, O_ck_n, IO_rwds, IO_dq, O_reset, O_cs_n

	   int the psram_syn_top.v file:
		O_psram_cn,O_psram_ck_n,IO_psram_rwds,IO_psram_dq,O_psram_reset_n,O_psram_cs_n,
		wr_data,rd_data,addr,data_mask
	   in the psram_test.v file:
		rd_data,wr_data,addr,data_mask

../project/src/*.v : 
                        test design for PSRAM ip
../project/src/psram_memory_interface/psram_memory_interface.vo :
                        PSRAM IP
../tb/tb.v :
                        testbench for simulation
prim_sim.v:             simulation library, get from installation path of Gowin YunYuan software 
