Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.8.09\IDE\ipcore\PSRAM_HS_V2\data\PSRAM_TOP.v D:\Gowin\Gowin_V1.9.8.09\IDE\ipcore\PSRAM_HS_V2\data\psram_code.v |
| GowinSynthesis Constraints File | --- |
| Version | GowinSynthesis V1.9.8.09 |
| Part Number | GW2AR-LV18EQ144PC8/I7 |
| Device | GW2AR-18C |
| Created Time | Fri Oct 28 15:00:05 2022 |
| Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | PSRAM_Memory_Interface_HS_V2_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.629s, Peak memory usage = 50.793MB Running netlist conversion: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 50.793MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.097s, Peak memory usage = 50.793MB Optimizing Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.067s, Peak memory usage = 50.793MB Optimizing Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.101s, Peak memory usage = 50.793MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 50.793MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 50.793MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 50.793MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 50.793MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.096s, Peak memory usage = 50.793MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 50.793MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 50.793MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 63.813MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.178s, Peak memory usage = 63.813MB Generate output files: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 63.813MB |
| Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 63.813MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 167 |
| Embedded Port | 26 |
| I/O Buf | 191 |
| IBUF | 100 |
| OBUF | 71 |
| IOBUF | 18 |
| ELVDS_OBUF | 2 |
| Register | 505 |
| DFF | 1 |
| DFFP | 3 |
| DFFPE | 6 |
| DFFC | 285 |
| DFFCE | 210 |
| LUT | 862 |
| LUT2 | 214 |
| LUT3 | 318 |
| LUT4 | 330 |
| ALU | 26 |
| ALU | 26 |
| INV | 5 |
| INV | 5 |
| IOLOGIC | 54 |
| IDES4 | 16 |
| OSER4 | 22 |
| IODELAY | 16 |
| BSRAM | 2 |
| SDPX9B | 2 |
| CLOCK | 3 |
| CLKDIV | 1 |
| DHCEN | 2 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 893(867 LUTs, 26 ALUs) / 20736 | 4% |
| Register | 505 / 15990 | 3% |
| --Register as Latch | 0 / 15990 | 0% |
| --Register as FF | 505 / 15990 | 3% |
| BSRAM | 2 / 46 | 4% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| memory_clk_p | Base | 10.000 | 100.0 | 0.000 | 5.000 | memory_clk_p_ibuf/I | ||
| memory_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | memory_clk_ibuf/I | ||
| clk_d | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_d_ibuf/I | ||
| u_psram_top/clkdiv/CLKOUT.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | memory_clk_ibuf/I | memory_clk | u_psram_top/clkdiv/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk_d | 100.0(MHz) | 278.1(MHz) | 5 | TOP |
| 2 | u_psram_top/clkdiv/CLKOUT.default_gen_clk | 50.0(MHz) | 278.4(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 4.372 |
| Data Arrival Time | 1.332 |
| Data Required Time | 5.704 |
| From | u_psram_top/u_psram_sync/cs_memsync_4_s0 |
| To | u_psram_top/u_dqce_clk_x2 |
| Launch Clk | clk_d[F] |
| Latch Clk | memory_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_d | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_d_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 31 | clk_d_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_psram_top/u_psram_sync/cs_memsync_4_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 7 | u_psram_top/u_psram_sync/cs_memsync_4_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | u_psram_top/u_dqce_clk_x2/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | memory_clk | |||
| 5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
| 5.688 | 0.688 | tINS | FF | 1 | memory_clk_ibuf/O |
| 5.924 | 0.237 | tNET | FF | 3 | u_psram_top/u_dqce_clk_x2/CLKIN |
| 5.890 | -0.035 | tUnc | u_psram_top/u_dqce_clk_x2 | ||
| 5.704 | -0.186 | tSu | 1 | u_psram_top/u_dqce_clk_x2 |
| Clock Skew: | 0.062 |
| Setup Relationship: | 5.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:| Slack | 4.372 |
| Data Arrival Time | 1.332 |
| Data Required Time | 5.704 |
| From | u_psram_top/u_psram_sync/cs_memsync_4_s0 |
| To | u_psram_top/u_dqce_clk_x2p |
| Launch Clk | clk_d[F] |
| Latch Clk | memory_clk_p[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_d | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_d_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 31 | clk_d_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_psram_top/u_psram_sync/cs_memsync_4_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 7 | u_psram_top/u_psram_sync/cs_memsync_4_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | u_psram_top/u_dqce_clk_x2p/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | memory_clk_p | |||
| 5.000 | 0.000 | tCL | FF | 1 | memory_clk_p_ibuf/I |
| 5.688 | 0.688 | tINS | FF | 1 | memory_clk_p_ibuf/O |
| 5.924 | 0.237 | tNET | FF | 3 | u_psram_top/u_dqce_clk_x2p/CLKIN |
| 5.890 | -0.035 | tUnc | u_psram_top/u_dqce_clk_x2p | ||
| 5.704 | -0.186 | tSu | 1 | u_psram_top/u_dqce_clk_x2p |
| Clock Skew: | 0.062 |
| Setup Relationship: | 5.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:| Slack | 6.404 |
| Data Arrival Time | 4.424 |
| Data Required Time | 10.828 |
| From | u_psram_top/u_psram_sync/cs_memsync_5_s0 |
| To | u_psram_top/u_psram_sync/flag_1_s0 |
| Launch Clk | clk_d[R] |
| Latch Clk | clk_d[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_d | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_d_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 31 | clk_d_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_psram_top/u_psram_sync/cs_memsync_5_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 6 | u_psram_top/u_psram_sync/cs_memsync_5_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n359_s9/I1 |
| 1.887 | 0.555 | tINS | FF | 6 | u_psram_top/u_psram_sync/n359_s9/F |
| 2.124 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n326_s14/I0 |
| 2.641 | 0.517 | tINS | FF | 3 | u_psram_top/u_psram_sync/n326_s14/F |
| 2.878 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n348_s6/I1 |
| 3.433 | 0.555 | tINS | FF | 2 | u_psram_top/u_psram_sync/n348_s6/F |
| 3.670 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n348_s5/I0 |
| 4.187 | 0.517 | tINS | FF | 1 | u_psram_top/u_psram_sync/n348_s5/F |
| 4.424 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/flag_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_d | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_d_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 31 | clk_d_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_psram_top/u_psram_sync/flag_1_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | u_psram_top/u_psram_sync/flag_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.144, 60.208%; route: 1.185, 33.277%; tC2Q: 0.232, 6.515% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:| Slack | 6.512 |
| Data Arrival Time | 4.316 |
| Data Required Time | 10.828 |
| From | u_psram_top/u_psram_sync/count_2_s0 |
| To | u_psram_top/u_psram_sync/count_0_s0 |
| Launch Clk | clk_d[R] |
| Latch Clk | clk_d[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_d | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_d_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 31 | clk_d_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_psram_top/u_psram_sync/count_2_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 5 | u_psram_top/u_psram_sync/count_2_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n282_s17/I1 |
| 1.887 | 0.555 | tINS | FF | 2 | u_psram_top/u_psram_sync/n282_s17/F |
| 2.124 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n315_s13/I3 |
| 2.495 | 0.371 | tINS | FF | 2 | u_psram_top/u_psram_sync/n315_s13/F |
| 2.732 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n389_s2/I1 |
| 3.287 | 0.555 | tINS | FF | 3 | u_psram_top/u_psram_sync/n389_s2/F |
| 3.524 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n389_s1/I1 |
| 4.079 | 0.555 | tINS | FF | 1 | u_psram_top/u_psram_sync/n389_s1/F |
| 4.316 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/count_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_d | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_d_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 31 | clk_d_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_psram_top/u_psram_sync/count_0_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | u_psram_top/u_psram_sync/count_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.036, 58.963%; route: 1.185, 34.318%; tC2Q: 0.232, 6.719% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:| Slack | 6.550 |
| Data Arrival Time | 4.278 |
| Data Required Time | 10.828 |
| From | u_psram_top/u_psram_sync/cs_memsync_5_s0 |
| To | u_psram_top/u_psram_sync/flag_0_s0 |
| Launch Clk | clk_d[R] |
| Latch Clk | clk_d[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_d | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_d_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 31 | clk_d_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_psram_top/u_psram_sync/cs_memsync_5_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 6 | u_psram_top/u_psram_sync/cs_memsync_5_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n359_s9/I1 |
| 1.887 | 0.555 | tINS | FF | 6 | u_psram_top/u_psram_sync/n359_s9/F |
| 2.124 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n326_s14/I0 |
| 2.641 | 0.517 | tINS | FF | 3 | u_psram_top/u_psram_sync/n326_s14/F |
| 2.878 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n348_s6/I1 |
| 3.433 | 0.555 | tINS | FF | 2 | u_psram_top/u_psram_sync/n348_s6/F |
| 3.670 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n359_s6/I3 |
| 4.041 | 0.371 | tINS | FF | 1 | u_psram_top/u_psram_sync/n359_s6/F |
| 4.278 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/flag_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_d | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_d_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 31 | clk_d_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_psram_top/u_psram_sync/flag_0_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | u_psram_top/u_psram_sync/flag_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 1.998, 58.506%; route: 1.185, 34.700%; tC2Q: 0.232, 6.794% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |