vcs:
	vcs -sverilog -R -full64 -fsdb -timescale=1ns/100ps -debug_region+cell+encrypt \
	-v ../../tb/prim_sim.v       \
	../../simulation/vcs_sim/dqs_25k_vcs.vp	\
	../../tb/tb.v     \
	../../project/src/top.v       \
	../../project/src/key_debounce.v    \
	../../project/src/test_2k.v    \
	../../project/src/gowin_pll/gowin_pll.v \
	../../tb/sim_model/AP26408A_vcs.vp \
	../../project/src/uhs2_psram_memory_interface/uhs2_psram_memory_interface.vo \
	+incdir+../../project/src/ \
	+incdir+../../project/src/uhs2_psram_memory_interface/temp/UHS2PSRAM/   \
	+incdir+../../tb/sim_model/  \
	+incdir+../../tb/  | tee log


vd:
	verdi -sverilog -timescale=1ns/100ps -debug_region+cell+encrypt -v	\
	../../tb/prim_sim.v  \
	../../simulation/vcs_sim/dqs_25k_vcs.vp	\
	../../tb/tb.v     \
	../../project/src/top.v       \
	../../project/src/key_debounce.v    \
	../../project/src/test.v    \
	../../project/src/gowin_pll/gowin_pll.v \
	../../tb/sim_model/AP26408A_vcs.vp \
	../../project/src/uhs2_psram_memory_interface/uhs2_psram_memory_interface.vo \
	+incdir+../../project/src/ \
	+incdir+../../project/src/uhs2_psram_memory_interface/temp/UHS2PSRAM/   \
	+incdir+../../tb/sim_model/  \
	+incdir+../../tb/        \
	-ssf tb.fsdb                &
