________________________________________________________________________
	UHS2 PSRAM Memory Interface IP Reference Design Read Me
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	Object device:GW5AR-LV25UG256PC2/I1
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File List:
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.
|-- docs
|   `-- Readme.txt                      	-->  Read Me file (this file)
|-- project
    `-- fpga_project   
|     |-- fpga_project.gprj	-->  Gowin Project File for Example Design
|     `-- src                               	-->  File for Gowin Project in it
|      `-- uhs2_psram_memory_interface_v2    -->  IP CORE
       |-- fpga_project.cst		   -->  Physical Constraints file
       |-- fpga_project.sdc                	   -->  Timing Constraints file
       | --Key_debounce.v       		   -->  button file
       |-- test.v			   -->  Test file
       |-- top.v			   -->  Top model file 
|-- simulation			   -->  simulation file
|-- tb				   -->  testbench file
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HOW TO OPEN A PROJECT IN Gowin:
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1. Unzip the respective design files.
2. Launch GOWIN FPGA Designer and select "File -> Open -> Project"
3. In the Open Project dialog, enter the Project location -- "project/fpga_project",select the project"fpga_project.gprj".
4. Click Finish. Now the project is successfully loaded. 

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HOW TO RUN SYNTHESIZE, PLACE AND ROUTE, IP CORE GENERATION, AND TIMING ANALYSIS IN Gowin:
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1. Click the Process tab in the process panel of the Gowin dashboard. 
   Double click on Synthsize. This will bring the design through synthesis.
2. Click the Process tab in the process panel of the Gowin dashboard. 
   Double click on Place & Route. This will bring the design through mapping, place and route.
3. Once Place & Route is done, user can double click on Timing Analysis Report to get 
   the timing analysis result.
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