Timing Messages

Report Title	Timing Analysis Report
Design File	E:\IP_Release\SSCPLL\1.5\ref_design\Gowin_SSCPLL_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\IP_Release\SSCPLL\1.5\ref_design\Gowin_SSCPLL_RefDesign\project\src\fpga.cst
Timing Constraint File	---
Tool Version	V1.9.12.02 (64-bit)
Part Number	GW5AST-LV138FPG676AC1/I0
Device	GW5AST-138
Device Version	B
Created Time	Mon Mar 9 10:55:45 2026
Legal Announcement	Copyright (C)2014-2026 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.873V 0C C1/I0
Hold Delay Model	Fast 0.927V 85C C1/I0
Numbers of Paths Analyzed	658
Numbers of Endpoints Analyzed	484
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	sys_clk	Base	20.000	50.000	0.000	10.000			sys_clk_ibuf/I
2	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKOUT0.default_gen_clk	Generated	10.000	100.000	0.000	5.000	sys_clk_ibuf/I	sys_clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKOUT0
3	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk	Generated	20.000	50.000	0.000	10.000	sys_clk_ibuf/I	sys_clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	sys_clk	50.000(MHz)	274.263(MHz)	3	TOP
2	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk	50.000(MHz)	148.074(MHz)	8	TOP

No timing paths to get frequency of sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKOUT0.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
sys_clk	Setup	0.000	0
sys_clk	Hold	0.000	0
sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKOUT0.default_gen_clk	Setup	0.000	0
sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKOUT0.default_gen_clk	Hold	0.000	0
sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk	Setup	0.000	0
sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	13.247	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_22_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.044	6.652
2	14.099	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_6_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.000	5.843
3	14.189	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_4_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.000	5.753
4	14.192	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_5_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.000	5.751
5	14.354	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_20_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.035	5.553
6	14.356	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_21_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.035	5.551
7	14.386	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_3_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.000	5.556
8	14.436	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_18_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.044	5.463
9	14.446	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_19_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.035	5.461
10	14.517	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_2_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.000	5.426
11	14.526	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_16_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.044	5.373
12	14.528	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_17_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.044	5.371
13	14.616	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_14_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.044	5.283
14	14.618	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_15_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.044	5.281
15	14.620	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_1_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.000	5.322
16	14.697	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_12_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.052	5.193
17	14.708	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_13_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.044	5.191
18	14.790	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_11_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.052	5.101
19	14.800	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_mdiv_code_conv/frac_o_2_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	-0.008	5.151
20	14.835	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_0_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.044	5.064
21	14.839	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_10_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.052	5.051
22	14.869	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_15_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.046	5.028
23	14.954	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_mdiv_code_conv/frac_o_0_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	-0.008	4.997
24	14.980	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_20_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.035	4.933
25	14.985	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_19_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.035	4.922

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.250	sscpll0/u_gwfpll/u_triangle_codegen/div_o_0_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/div_o_0_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	0.000	0.000	0.273
2	0.250	rstn_cnt_0_s1/Q	rstn_cnt_0_s1/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.273
3	0.295	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_1_s0/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_1_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.318
4	0.295	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_0_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_0_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	0.000	0.000	0.318
5	0.301	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_0_s0/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.324
6	0.304	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_0_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	0.000	0.000	0.327
7	0.310	rstn_cnt_1_s1/Q	rstn_cnt_2_s1/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.332
8	0.310	rstn_cnt_1_s1/Q	rstn_cnt_1_s1/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.332
9	0.310	rstn_cnt_1_s1/Q	rstn_cnt_3_s1/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.332
10	0.333	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_1_s1/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_9_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	-0.004	0.359
11	0.333	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_1_s1/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_10_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	-0.004	0.359
12	0.333	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	0.000	0.000	0.355
13	0.333	sscpll0/u_gwfpll/u_triangle_codegen/div_o_4_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/div_o_4_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	0.000	0.000	0.355
14	0.333	sscpll0/u_gwfpll/u_triangle_codegen/div_o_8_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/div_o_8_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	0.000	0.000	0.355
15	0.333	sscpll0/u_gwfpll/u_triangle_codegen/div_o_10_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/div_o_10_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	0.000	0.000	0.355
16	0.335	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_6_s0/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/Waitlock_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.004	0.354
17	0.339	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_0_s0/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_0_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.362
18	0.339	sscpll0/u_gwfpll/u_triangle_codegen/div_o_12_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/div_o_12_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	0.000	0.000	0.362
19	0.339	sscpll0/u_gwfpll/u_triangle_codegen/div_o_18_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/div_o_18_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	0.000	0.000	0.362
20	0.339	sscpll0/u_gwfpll/u_triangle_codegen/div_o_24_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/div_o_24_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	0.000	0.000	0.362
21	0.339	sscpll0/u_gwfpll/u_triangle_codegen/div_o_30_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/div_o_30_s0/D	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	0.000	0.000	0.362
22	0.355	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_3_s0/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_3_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.366
23	0.355	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_7_s0/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_7_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.366
24	0.355	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_9_s0/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_9_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.366
25	0.355	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_13_s0/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_13_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.366

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	16.413	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/div_o_28_s0/PRESET	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	-0.008	3.248
2	16.413	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/o_dir_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	-0.008	3.248
3	16.413	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/div_o_25_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	-0.008	3.248
4	16.413	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/div_o_26_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	-0.008	3.248
5	16.413	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/div_o_27_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	-0.008	3.248
6	16.413	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/div_o_29_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	-0.008	3.248
7	16.413	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/div_o_30_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	-0.008	3.248
8	16.421	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/div_o_19_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	-0.017	3.248
9	16.421	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/div_o_20_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	-0.017	3.248
10	16.421	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/div_o_21_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	-0.017	3.248
11	16.421	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/div_o_22_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	-0.017	3.248
12	16.421	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/div_o_23_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	-0.017	3.248
13	16.421	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/div_o_24_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	-0.017	3.248
14	16.456	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_13_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.037	3.159
15	16.456	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_14_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.037	3.159
16	16.456	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_15_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.037	3.159
17	16.464	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_7_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.046	3.143
18	16.464	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_8_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.046	3.143
19	16.467	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_18_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.027	3.158
20	16.467	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_19_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.027	3.158
21	16.467	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_20_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.027	3.158
22	16.467	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_19_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.027	3.158
23	16.467	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_20_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.027	3.158
24	16.467	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_21_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	0.027	3.158
25	16.640	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/div_o_13_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	20.000	-0.008	3.021

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.320	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_1_s0/CLEAR	sys_clk:[R]	sys_clk:[R]	0.000	-0.006	0.278
2	0.323	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_0_s0/CLEAR	sys_clk:[R]	sys_clk:[R]	0.000	-0.003	0.278
3	0.325	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/laststep_s0/CLEAR	sys_clk:[R]	sys_clk:[R]	0.000	-0.003	0.280
4	0.404	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_2_s0/CLEAR	sys_clk:[R]	sys_clk:[R]	0.000	0.001	0.355
5	0.507	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/ssc_en_o_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	0.000	-0.005	0.499
6	0.524	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/CLEAR	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.476
7	0.524	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_0_s0/CLEAR	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.476
8	0.535	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_triangle_codegen/div_o_0_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	0.000	-0.004	0.526
9	0.560	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_0_s1/CLEAR	sys_clk:[R]	sys_clk:[R]	0.000	0.001	0.511
10	0.560	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_2_s1/CLEAR	sys_clk:[R]	sys_clk:[R]	0.000	0.001	0.511
11	0.609	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_0_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	0.000	0.001	0.595
12	0.609	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	0.000	0.001	0.595
13	0.639	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_12_s0/CLEAR	sys_clk:[R]	sys_clk:[R]	0.000	-0.006	0.598
14	0.707	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_1_s1/CLEAR	sys_clk:[R]	sys_clk:[R]	0.000	-0.003	0.662
15	0.707	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_3_s1/CLEAR	sys_clk:[R]	sys_clk:[R]	0.000	-0.003	0.662
16	0.737	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_9_s0/CLEAR	sys_clk:[R]	sys_clk:[R]	0.000	-0.006	0.696
17	0.737	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_10_s0/CLEAR	sys_clk:[R]	sys_clk:[R]	0.000	-0.006	0.696
18	0.741	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_0_s0/CLEAR	sys_clk:[R]	sys_clk:[R]	0.000	-0.003	0.696
19	0.741	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_8_s0/CLEAR	sys_clk:[R]	sys_clk:[R]	0.000	-0.003	0.696
20	0.755	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_1_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	0.000	-0.003	0.745
21	0.755	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_2_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	0.000	-0.003	0.745
22	0.755	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_3_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	0.000	-0.003	0.745
23	0.755	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_22_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	0.000	-0.003	0.745
24	1.302	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_4_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	0.000	-0.006	1.296
25	1.302	rstn_d1_s0/Q	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_5_s0/CLEAR	sys_clk:[R]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]	0.000	-0.006	1.296

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	7.948	8.173	0.225	High Pulse Width	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk	sscpll0/u_gwfpll/u_triangle_codegen/div_o_24_s0
2	7.948	8.173	0.225	High Pulse Width	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk	sscpll0/u_gwfpll/u_triangle_codegen/div_o_23_s0
3	7.948	8.173	0.225	High Pulse Width	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk	sscpll0/u_gwfpll/u_triangle_codegen/div_o_19_s0
4	7.948	8.173	0.225	High Pulse Width	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk	sscpll0/u_gwfpll/u_triangle_codegen/div_o_22_s0
5	7.948	8.173	0.225	High Pulse Width	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk	sscpll0/u_gwfpll/u_triangle_codegen/div_o_21_s0
6	7.948	8.173	0.225	High Pulse Width	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk	sscpll0/u_gwfpll/u_triangle_codegen/div_o_20_s0
7	7.948	8.173	0.225	High Pulse Width	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_18_s0
8	7.948	8.173	0.225	High Pulse Width	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_17_s0
9	7.948	8.173	0.225	High Pulse Width	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_16_s0
10	7.948	8.173	0.225	High Pulse Width	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_15_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	13.247
Data Arrival Time	10.599
Data Required Time	23.845
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_22_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
7.028	0.267	tINS	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/SUM
8.292	1.264	tNET	RR	2	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/I0
8.828	0.535	tINS	RF	1	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/COUT
8.828	0.000	tNET	FF	2	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/CIN
8.873	0.045	tINS	FR	1	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/COUT
8.873	0.000	tNET	RR	2	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/CIN
8.918	0.045	tINS	RR	1	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/COUT
8.918	0.000	tNET	RR	2	R54C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n87_s/CIN
8.963	0.045	tINS	RR	1	R54C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n87_s/COUT
8.963	0.000	tNET	RR	2	R54C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n86_s/CIN
9.008	0.045	tINS	RR	1	R54C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n86_s/COUT
9.008	0.000	tNET	RR	2	R54C114[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n85_s/CIN
9.053	0.045	tINS	RR	1	R54C114[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n85_s/COUT
9.053	0.000	tNET	RR	2	R54C114[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n84_s/CIN
9.098	0.045	tINS	RR	1	R54C114[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n84_s/COUT
9.098	0.000	tNET	RR	2	R54C114[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n83_s/CIN
9.143	0.045	tINS	RR	1	R54C114[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n83_s/COUT
9.143	0.000	tNET	RR	2	R54C114[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n82_s/CIN
9.188	0.045	tINS	RR	1	R54C114[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n82_s/COUT
9.188	0.000	tNET	RR	2	R54C115[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n81_s/CIN
9.233	0.045	tINS	RR	1	R54C115[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n81_s/COUT
9.233	0.000	tNET	RR	2	R54C115[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n80_s/CIN
9.278	0.045	tINS	RR	1	R54C115[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n80_s/COUT
9.278	0.000	tNET	RR	2	R54C115[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n79_s/CIN
9.323	0.045	tINS	RR	1	R54C115[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n79_s/COUT
10.142	0.819	tNET	RR	1	R54C110[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n78_9_3_s0/I0
10.599	0.457	tINS	RR	1	R54C110[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n78_9_3_s0/F
10.599	0.000	tNET	RR	1	R54C110[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.903	3.286	tNET	RR	1	R54C110[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_22_s0/CLK
23.845	-0.057	tSu		1	R54C110[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_22_s0

Path Statistics:

Clock Skew	-0.044
Setup Relationship	20.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 2.564, 38.542%; route: 3.744, 56.283%; tC2Q: 0.344, 5.175%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.286, 100.000%

Path2

Path Summary:

Slack	14.099
Data Arrival Time	9.790
Data Required Time	23.889
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_6_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
6.806	0.045	tINS	RR	1	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/COUT
6.806	0.000	tNET	RR	2	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/CIN
6.851	0.045	tINS	RR	1	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/COUT
6.851	0.000	tNET	RR	2	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/CIN
6.896	0.045	tINS	RR	1	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/COUT
6.896	0.000	tNET	RR	2	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/CIN
6.941	0.045	tINS	RR	1	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/COUT
6.941	0.000	tNET	RR	2	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/CIN
6.986	0.045	tINS	RR	1	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/COUT
6.986	0.000	tNET	RR	2	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/CIN
7.031	0.045	tINS	RR	1	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/COUT
7.031	0.000	tNET	RR	2	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/CIN
7.076	0.045	tINS	RR	1	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/COUT
7.076	0.000	tNET	RR	2	R54C96[2][A]	sscpll0/u_gwfpll/u_sdm2/error_16_s/CIN
7.121	0.045	tINS	RR	1	R54C96[2][A]	sscpll0/u_gwfpll/u_sdm2/error_16_s/COUT
7.121	0.000	tNET	RR	2	R54C96[2][B]	sscpll0/u_gwfpll/u_sdm2/error_17_s/CIN
7.166	0.045	tINS	RR	1	R54C96[2][B]	sscpll0/u_gwfpll/u_sdm2/error_17_s/COUT
7.166	0.000	tNET	RR	2	R54C97[0][A]	sscpll0/u_gwfpll/u_sdm2/error_18_s/CIN
7.211	0.045	tINS	RR	1	R54C97[0][A]	sscpll0/u_gwfpll/u_sdm2/error_18_s/COUT
7.211	0.000	tNET	RR	2	R54C97[0][B]	sscpll0/u_gwfpll/u_sdm2/error_19_s/CIN
7.256	0.045	tINS	RR	1	R54C97[0][B]	sscpll0/u_gwfpll/u_sdm2/error_19_s/COUT
7.256	0.000	tNET	RR	2	R54C97[1][A]	sscpll0/u_gwfpll/u_sdm2/error_20_s/CIN
7.301	0.045	tINS	RR	1	R54C97[1][A]	sscpll0/u_gwfpll/u_sdm2/error_20_s/COUT
7.301	0.000	tNET	RR	2	R54C97[1][B]	sscpll0/u_gwfpll/u_sdm2/out_0_s/CIN
7.346	0.045	tINS	RR	1	R54C97[1][B]	sscpll0/u_gwfpll/u_sdm2/out_0_s/COUT
7.346	0.000	tNET	RR	2	R54C97[2][A]	sscpll0/u_gwfpll/u_sdm2/out_1_s/CIN
7.391	0.045	tINS	RR	1	R54C97[2][A]	sscpll0/u_gwfpll/u_sdm2/out_1_s/COUT
7.391	0.000	tNET	RR	2	R54C97[2][B]	sscpll0/u_gwfpll/u_sdm2/out_2_s/CIN
7.436	0.045	tINS	RR	1	R54C97[2][B]	sscpll0/u_gwfpll/u_sdm2/out_2_s/COUT
7.436	0.000	tNET	RR	2	R54C98[0][A]	sscpll0/u_gwfpll/u_sdm2/out_3_s/CIN
7.481	0.045	tINS	RR	1	R54C98[0][A]	sscpll0/u_gwfpll/u_sdm2/out_3_s/COUT
7.481	0.000	tNET	RR	2	R54C98[0][B]	sscpll0/u_gwfpll/u_sdm2/out_4_s/CIN
7.526	0.045	tINS	RR	1	R54C98[0][B]	sscpll0/u_gwfpll/u_sdm2/out_4_s/COUT
7.526	0.000	tNET	RR	2	R54C98[1][A]	sscpll0/u_gwfpll/u_sdm2/out_5_s/CIN
7.571	0.045	tINS	RR	1	R54C98[1][A]	sscpll0/u_gwfpll/u_sdm2/out_5_s/COUT
7.571	0.000	tNET	RR	2	R54C98[1][B]	sscpll0/u_gwfpll/u_sdm2/out_6_s/CIN
7.838	0.267	tINS	RR	1	R54C98[1][B]	sscpll0/u_gwfpll/u_sdm2/out_6_s/SUM
8.943	1.105	tNET	RR	2	R54C80[1][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/n16_s/I1
9.433	0.490	tINS	RR	1	R54C80[1][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/n16_s/COUT
9.433	0.000	tNET	RR	2	R54C80[1][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/n15_s/CIN
9.478	0.045	tINS	RR	1	R54C80[1][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/n15_s/COUT
9.478	0.000	tNET	RR	2	R54C80[2][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/n14_s/CIN
9.523	0.045	tINS	RR	1	R54C80[2][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/n14_s/COUT
9.523	0.000	tNET	RR	2	R54C80[2][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/n13_s/CIN
9.790	0.267	tINS	RR	1	R54C80[2][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/n13_s/SUM
9.790	0.000	tNET	RR	1	R54C80[2][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.946	3.330	tNET	RR	1	R54C80[2][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_6_s0/CLK
23.889	-0.057	tSu		1	R54C80[2][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 2.734, 46.785%; route: 2.765, 47.324%; tC2Q: 0.344, 5.891%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%

Path3

Path Summary:

Slack	14.189
Data Arrival Time	9.700
Data Required Time	23.889
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_4_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
6.806	0.045	tINS	RR	1	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/COUT
6.806	0.000	tNET	RR	2	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/CIN
6.851	0.045	tINS	RR	1	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/COUT
6.851	0.000	tNET	RR	2	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/CIN
6.896	0.045	tINS	RR	1	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/COUT
6.896	0.000	tNET	RR	2	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/CIN
6.941	0.045	tINS	RR	1	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/COUT
6.941	0.000	tNET	RR	2	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/CIN
6.986	0.045	tINS	RR	1	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/COUT
6.986	0.000	tNET	RR	2	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/CIN
7.031	0.045	tINS	RR	1	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/COUT
7.031	0.000	tNET	RR	2	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/CIN
7.076	0.045	tINS	RR	1	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/COUT
7.076	0.000	tNET	RR	2	R54C96[2][A]	sscpll0/u_gwfpll/u_sdm2/error_16_s/CIN
7.121	0.045	tINS	RR	1	R54C96[2][A]	sscpll0/u_gwfpll/u_sdm2/error_16_s/COUT
7.121	0.000	tNET	RR	2	R54C96[2][B]	sscpll0/u_gwfpll/u_sdm2/error_17_s/CIN
7.166	0.045	tINS	RR	1	R54C96[2][B]	sscpll0/u_gwfpll/u_sdm2/error_17_s/COUT
7.166	0.000	tNET	RR	2	R54C97[0][A]	sscpll0/u_gwfpll/u_sdm2/error_18_s/CIN
7.211	0.045	tINS	RR	1	R54C97[0][A]	sscpll0/u_gwfpll/u_sdm2/error_18_s/COUT
7.211	0.000	tNET	RR	2	R54C97[0][B]	sscpll0/u_gwfpll/u_sdm2/error_19_s/CIN
7.256	0.045	tINS	RR	1	R54C97[0][B]	sscpll0/u_gwfpll/u_sdm2/error_19_s/COUT
7.256	0.000	tNET	RR	2	R54C97[1][A]	sscpll0/u_gwfpll/u_sdm2/error_20_s/CIN
7.301	0.045	tINS	RR	1	R54C97[1][A]	sscpll0/u_gwfpll/u_sdm2/error_20_s/COUT
7.301	0.000	tNET	RR	2	R54C97[1][B]	sscpll0/u_gwfpll/u_sdm2/out_0_s/CIN
7.346	0.045	tINS	RR	1	R54C97[1][B]	sscpll0/u_gwfpll/u_sdm2/out_0_s/COUT
7.346	0.000	tNET	RR	2	R54C97[2][A]	sscpll0/u_gwfpll/u_sdm2/out_1_s/CIN
7.391	0.045	tINS	RR	1	R54C97[2][A]	sscpll0/u_gwfpll/u_sdm2/out_1_s/COUT
7.391	0.000	tNET	RR	2	R54C97[2][B]	sscpll0/u_gwfpll/u_sdm2/out_2_s/CIN
7.436	0.045	tINS	RR	1	R54C97[2][B]	sscpll0/u_gwfpll/u_sdm2/out_2_s/COUT
7.436	0.000	tNET	RR	2	R54C98[0][A]	sscpll0/u_gwfpll/u_sdm2/out_3_s/CIN
7.481	0.045	tINS	RR	1	R54C98[0][A]	sscpll0/u_gwfpll/u_sdm2/out_3_s/COUT
7.481	0.000	tNET	RR	2	R54C98[0][B]	sscpll0/u_gwfpll/u_sdm2/out_4_s/CIN
7.526	0.045	tINS	RR	1	R54C98[0][B]	sscpll0/u_gwfpll/u_sdm2/out_4_s/COUT
7.526	0.000	tNET	RR	2	R54C98[1][A]	sscpll0/u_gwfpll/u_sdm2/out_5_s/CIN
7.571	0.045	tINS	RR	1	R54C98[1][A]	sscpll0/u_gwfpll/u_sdm2/out_5_s/COUT
7.571	0.000	tNET	RR	2	R54C98[1][B]	sscpll0/u_gwfpll/u_sdm2/out_6_s/CIN
7.838	0.267	tINS	RR	1	R54C98[1][B]	sscpll0/u_gwfpll/u_sdm2/out_6_s/SUM
8.943	1.105	tNET	RR	2	R54C80[1][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/n16_s/I1
9.433	0.490	tINS	RR	1	R54C80[1][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/n16_s/COUT
9.433	0.000	tNET	RR	2	R54C80[1][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/n15_s/CIN
9.700	0.267	tINS	RR	1	R54C80[1][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/n15_s/SUM
9.700	0.000	tNET	RR	1	R54C80[1][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.946	3.330	tNET	RR	1	R54C80[1][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_4_s0/CLK
23.889	-0.057	tSu		1	R54C80[1][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 2.644, 45.952%; route: 2.765, 48.064%; tC2Q: 0.344, 5.984%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%

Path4

Path Summary:

Slack	14.192
Data Arrival Time	9.698
Data Required Time	23.889
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_5_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
6.806	0.045	tINS	RR	1	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/COUT
6.806	0.000	tNET	RR	2	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/CIN
6.851	0.045	tINS	RR	1	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/COUT
6.851	0.000	tNET	RR	2	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/CIN
6.896	0.045	tINS	RR	1	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/COUT
6.896	0.000	tNET	RR	2	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/CIN
6.941	0.045	tINS	RR	1	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/COUT
6.941	0.000	tNET	RR	2	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/CIN
6.986	0.045	tINS	RR	1	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/COUT
6.986	0.000	tNET	RR	2	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/CIN
7.031	0.045	tINS	RR	1	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/COUT
7.031	0.000	tNET	RR	2	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/CIN
7.076	0.045	tINS	RR	1	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/COUT
7.076	0.000	tNET	RR	2	R54C96[2][A]	sscpll0/u_gwfpll/u_sdm2/error_16_s/CIN
7.121	0.045	tINS	RR	1	R54C96[2][A]	sscpll0/u_gwfpll/u_sdm2/error_16_s/COUT
7.121	0.000	tNET	RR	2	R54C96[2][B]	sscpll0/u_gwfpll/u_sdm2/error_17_s/CIN
7.166	0.045	tINS	RR	1	R54C96[2][B]	sscpll0/u_gwfpll/u_sdm2/error_17_s/COUT
7.166	0.000	tNET	RR	2	R54C97[0][A]	sscpll0/u_gwfpll/u_sdm2/error_18_s/CIN
7.211	0.045	tINS	RR	1	R54C97[0][A]	sscpll0/u_gwfpll/u_sdm2/error_18_s/COUT
7.211	0.000	tNET	RR	2	R54C97[0][B]	sscpll0/u_gwfpll/u_sdm2/error_19_s/CIN
7.256	0.045	tINS	RR	1	R54C97[0][B]	sscpll0/u_gwfpll/u_sdm2/error_19_s/COUT
7.256	0.000	tNET	RR	2	R54C97[1][A]	sscpll0/u_gwfpll/u_sdm2/error_20_s/CIN
7.301	0.045	tINS	RR	1	R54C97[1][A]	sscpll0/u_gwfpll/u_sdm2/error_20_s/COUT
7.301	0.000	tNET	RR	2	R54C97[1][B]	sscpll0/u_gwfpll/u_sdm2/out_0_s/CIN
7.346	0.045	tINS	RR	1	R54C97[1][B]	sscpll0/u_gwfpll/u_sdm2/out_0_s/COUT
7.346	0.000	tNET	RR	2	R54C97[2][A]	sscpll0/u_gwfpll/u_sdm2/out_1_s/CIN
7.391	0.045	tINS	RR	1	R54C97[2][A]	sscpll0/u_gwfpll/u_sdm2/out_1_s/COUT
7.391	0.000	tNET	RR	2	R54C97[2][B]	sscpll0/u_gwfpll/u_sdm2/out_2_s/CIN
7.436	0.045	tINS	RR	1	R54C97[2][B]	sscpll0/u_gwfpll/u_sdm2/out_2_s/COUT
7.436	0.000	tNET	RR	2	R54C98[0][A]	sscpll0/u_gwfpll/u_sdm2/out_3_s/CIN
7.481	0.045	tINS	RR	1	R54C98[0][A]	sscpll0/u_gwfpll/u_sdm2/out_3_s/COUT
7.481	0.000	tNET	RR	2	R54C98[0][B]	sscpll0/u_gwfpll/u_sdm2/out_4_s/CIN
7.526	0.045	tINS	RR	1	R54C98[0][B]	sscpll0/u_gwfpll/u_sdm2/out_4_s/COUT
7.526	0.000	tNET	RR	2	R54C98[1][A]	sscpll0/u_gwfpll/u_sdm2/out_5_s/CIN
7.571	0.045	tINS	RR	1	R54C98[1][A]	sscpll0/u_gwfpll/u_sdm2/out_5_s/COUT
7.571	0.000	tNET	RR	2	R54C98[1][B]	sscpll0/u_gwfpll/u_sdm2/out_6_s/CIN
7.838	0.267	tINS	RR	1	R54C98[1][B]	sscpll0/u_gwfpll/u_sdm2/out_6_s/SUM
8.943	1.105	tNET	RR	2	R54C80[1][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/n16_s/I1
9.433	0.490	tINS	RR	1	R54C80[1][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/n16_s/COUT
9.433	0.000	tNET	RR	2	R54C80[1][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/n15_s/CIN
9.478	0.045	tINS	RR	1	R54C80[1][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/n15_s/COUT
9.478	0.000	tNET	RR	2	R54C80[2][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/n14_s/CIN
9.698	0.219	tINS	RR	1	R54C80[2][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/n14_s/SUM
9.698	0.000	tNET	RR	1	R54C80[2][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.946	3.330	tNET	RR	1	R54C80[2][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_5_s0/CLK
23.889	-0.057	tSu		1	R54C80[2][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 2.641, 45.931%; route: 2.765, 48.083%; tC2Q: 0.344, 5.986%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%

Path5

Path Summary:

Slack	14.354
Data Arrival Time	9.499
Data Required Time	23.854
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_20_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
7.028	0.267	tINS	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/SUM
8.292	1.264	tNET	RR	2	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/I0
8.828	0.535	tINS	RF	1	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/COUT
8.828	0.000	tNET	FF	2	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/CIN
8.873	0.045	tINS	FR	1	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/COUT
8.873	0.000	tNET	RR	2	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/CIN
8.918	0.045	tINS	RR	1	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/COUT
8.918	0.000	tNET	RR	2	R54C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n87_s/CIN
8.963	0.045	tINS	RR	1	R54C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n87_s/COUT
8.963	0.000	tNET	RR	2	R54C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n86_s/CIN
9.008	0.045	tINS	RR	1	R54C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n86_s/COUT
9.008	0.000	tNET	RR	2	R54C114[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n85_s/CIN
9.053	0.045	tINS	RR	1	R54C114[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n85_s/COUT
9.053	0.000	tNET	RR	2	R54C114[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n84_s/CIN
9.098	0.045	tINS	RR	1	R54C114[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n84_s/COUT
9.098	0.000	tNET	RR	2	R54C114[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n83_s/CIN
9.143	0.045	tINS	RR	1	R54C114[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n83_s/COUT
9.143	0.000	tNET	RR	2	R54C114[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n82_s/CIN
9.188	0.045	tINS	RR	1	R54C114[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n82_s/COUT
9.188	0.000	tNET	RR	2	R54C115[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n81_s/CIN
9.233	0.045	tINS	RR	1	R54C115[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n81_s/COUT
9.233	0.000	tNET	RR	2	R54C115[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n80_s/CIN
9.500	0.267	tINS	RR	1	R54C115[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n80_s/SUM
9.500	0.000	tNET	RR	1	R54C115[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.911	3.295	tNET	RR	1	R54C115[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_20_s0/CLK
23.854	-0.057	tSu		1	R54C115[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_20_s0

Path Statistics:

Clock Skew	-0.035
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 2.284, 41.126%; route: 2.925, 52.674%; tC2Q: 0.344, 6.199%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.295, 100.000%

Path6

Path Summary:

Slack	14.356
Data Arrival Time	9.497
Data Required Time	23.854
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_21_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
7.028	0.267	tINS	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/SUM
8.292	1.264	tNET	RR	2	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/I0
8.828	0.535	tINS	RF	1	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/COUT
8.828	0.000	tNET	FF	2	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/CIN
8.873	0.045	tINS	FR	1	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/COUT
8.873	0.000	tNET	RR	2	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/CIN
8.918	0.045	tINS	RR	1	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/COUT
8.918	0.000	tNET	RR	2	R54C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n87_s/CIN
8.963	0.045	tINS	RR	1	R54C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n87_s/COUT
8.963	0.000	tNET	RR	2	R54C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n86_s/CIN
9.008	0.045	tINS	RR	1	R54C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n86_s/COUT
9.008	0.000	tNET	RR	2	R54C114[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n85_s/CIN
9.053	0.045	tINS	RR	1	R54C114[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n85_s/COUT
9.053	0.000	tNET	RR	2	R54C114[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n84_s/CIN
9.098	0.045	tINS	RR	1	R54C114[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n84_s/COUT
9.098	0.000	tNET	RR	2	R54C114[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n83_s/CIN
9.143	0.045	tINS	RR	1	R54C114[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n83_s/COUT
9.143	0.000	tNET	RR	2	R54C114[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n82_s/CIN
9.188	0.045	tINS	RR	1	R54C114[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n82_s/COUT
9.188	0.000	tNET	RR	2	R54C115[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n81_s/CIN
9.233	0.045	tINS	RR	1	R54C115[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n81_s/COUT
9.233	0.000	tNET	RR	2	R54C115[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n80_s/CIN
9.278	0.045	tINS	RR	1	R54C115[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n80_s/COUT
9.278	0.000	tNET	RR	2	R54C115[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n79_s/CIN
9.497	0.219	tINS	RR	1	R54C115[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n79_s/SUM
9.497	0.000	tNET	RR	1	R54C115[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.911	3.295	tNET	RR	1	R54C115[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_21_s0/CLK
23.854	-0.057	tSu		1	R54C115[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_21_s0

Path Statistics:

Clock Skew	-0.035
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 2.281, 41.103%; route: 2.925, 52.696%; tC2Q: 0.344, 6.202%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.295, 100.000%

Path7

Path Summary:

Slack	14.386
Data Arrival Time	9.503
Data Required Time	23.889
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_3_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
6.806	0.045	tINS	RR	1	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/COUT
6.806	0.000	tNET	RR	2	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/CIN
6.851	0.045	tINS	RR	1	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/COUT
6.851	0.000	tNET	RR	2	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/CIN
6.896	0.045	tINS	RR	1	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/COUT
6.896	0.000	tNET	RR	2	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/CIN
6.941	0.045	tINS	RR	1	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/COUT
6.941	0.000	tNET	RR	2	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/CIN
6.986	0.045	tINS	RR	1	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/COUT
6.986	0.000	tNET	RR	2	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/CIN
7.031	0.045	tINS	RR	1	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/COUT
7.031	0.000	tNET	RR	2	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/CIN
7.076	0.045	tINS	RR	1	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/COUT
7.076	0.000	tNET	RR	2	R54C96[2][A]	sscpll0/u_gwfpll/u_sdm2/error_16_s/CIN
7.121	0.045	tINS	RR	1	R54C96[2][A]	sscpll0/u_gwfpll/u_sdm2/error_16_s/COUT
7.121	0.000	tNET	RR	2	R54C96[2][B]	sscpll0/u_gwfpll/u_sdm2/error_17_s/CIN
7.166	0.045	tINS	RR	1	R54C96[2][B]	sscpll0/u_gwfpll/u_sdm2/error_17_s/COUT
7.166	0.000	tNET	RR	2	R54C97[0][A]	sscpll0/u_gwfpll/u_sdm2/error_18_s/CIN
7.211	0.045	tINS	RR	1	R54C97[0][A]	sscpll0/u_gwfpll/u_sdm2/error_18_s/COUT
7.211	0.000	tNET	RR	2	R54C97[0][B]	sscpll0/u_gwfpll/u_sdm2/error_19_s/CIN
7.256	0.045	tINS	RR	1	R54C97[0][B]	sscpll0/u_gwfpll/u_sdm2/error_19_s/COUT
7.256	0.000	tNET	RR	2	R54C97[1][A]	sscpll0/u_gwfpll/u_sdm2/error_20_s/CIN
7.301	0.045	tINS	RR	1	R54C97[1][A]	sscpll0/u_gwfpll/u_sdm2/error_20_s/COUT
7.301	0.000	tNET	RR	2	R54C97[1][B]	sscpll0/u_gwfpll/u_sdm2/out_0_s/CIN
7.346	0.045	tINS	RR	1	R54C97[1][B]	sscpll0/u_gwfpll/u_sdm2/out_0_s/COUT
7.346	0.000	tNET	RR	2	R54C97[2][A]	sscpll0/u_gwfpll/u_sdm2/out_1_s/CIN
7.391	0.045	tINS	RR	1	R54C97[2][A]	sscpll0/u_gwfpll/u_sdm2/out_1_s/COUT
7.391	0.000	tNET	RR	2	R54C97[2][B]	sscpll0/u_gwfpll/u_sdm2/out_2_s/CIN
7.436	0.045	tINS	RR	1	R54C97[2][B]	sscpll0/u_gwfpll/u_sdm2/out_2_s/COUT
7.436	0.000	tNET	RR	2	R54C98[0][A]	sscpll0/u_gwfpll/u_sdm2/out_3_s/CIN
7.481	0.045	tINS	RR	1	R54C98[0][A]	sscpll0/u_gwfpll/u_sdm2/out_3_s/COUT
7.481	0.000	tNET	RR	2	R54C98[0][B]	sscpll0/u_gwfpll/u_sdm2/out_4_s/CIN
7.526	0.045	tINS	RR	1	R54C98[0][B]	sscpll0/u_gwfpll/u_sdm2/out_4_s/COUT
7.526	0.000	tNET	RR	2	R54C98[1][A]	sscpll0/u_gwfpll/u_sdm2/out_5_s/CIN
7.571	0.045	tINS	RR	1	R54C98[1][A]	sscpll0/u_gwfpll/u_sdm2/out_5_s/COUT
7.571	0.000	tNET	RR	2	R54C98[1][B]	sscpll0/u_gwfpll/u_sdm2/out_6_s/CIN
7.838	0.267	tINS	RR	1	R54C98[1][B]	sscpll0/u_gwfpll/u_sdm2/out_6_s/SUM
8.943	1.105	tNET	RR	2	R54C80[1][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/n16_s/I1
9.503	0.560	tINS	RR	1	R54C80[1][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/n16_s/SUM
9.503	0.000	tNET	RR	1	R54C80[1][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.946	3.330	tNET	RR	1	R54C80[1][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_3_s0/CLK
23.889	-0.057	tSu		1	R54C80[1][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 2.447, 44.037%; route: 2.765, 49.767%; tC2Q: 0.344, 6.196%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%

Path8

Path Summary:

Slack	14.436
Data Arrival Time	9.409
Data Required Time	23.845
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_18_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
7.028	0.267	tINS	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/SUM
8.292	1.264	tNET	RR	2	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/I0
8.828	0.535	tINS	RF	1	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/COUT
8.828	0.000	tNET	FF	2	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/CIN
8.873	0.045	tINS	FR	1	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/COUT
8.873	0.000	tNET	RR	2	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/CIN
8.918	0.045	tINS	RR	1	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/COUT
8.918	0.000	tNET	RR	2	R54C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n87_s/CIN
8.963	0.045	tINS	RR	1	R54C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n87_s/COUT
8.963	0.000	tNET	RR	2	R54C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n86_s/CIN
9.008	0.045	tINS	RR	1	R54C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n86_s/COUT
9.008	0.000	tNET	RR	2	R54C114[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n85_s/CIN
9.053	0.045	tINS	RR	1	R54C114[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n85_s/COUT
9.053	0.000	tNET	RR	2	R54C114[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n84_s/CIN
9.098	0.045	tINS	RR	1	R54C114[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n84_s/COUT
9.098	0.000	tNET	RR	2	R54C114[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n83_s/CIN
9.143	0.045	tINS	RR	1	R54C114[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n83_s/COUT
9.143	0.000	tNET	RR	2	R54C114[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n82_s/CIN
9.410	0.267	tINS	RR	1	R54C114[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n82_s/SUM
9.410	0.000	tNET	RR	1	R54C114[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.903	3.286	tNET	RR	1	R54C114[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_18_s0/CLK
23.845	-0.057	tSu		1	R54C114[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_18_s0

Path Statistics:

Clock Skew	-0.044
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 2.194, 40.157%; route: 2.925, 53.542%; tC2Q: 0.344, 6.301%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.286, 100.000%

Path9

Path Summary:

Slack	14.446
Data Arrival Time	9.407
Data Required Time	23.854
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_19_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
7.028	0.267	tINS	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/SUM
8.292	1.264	tNET	RR	2	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/I0
8.828	0.535	tINS	RF	1	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/COUT
8.828	0.000	tNET	FF	2	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/CIN
8.873	0.045	tINS	FR	1	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/COUT
8.873	0.000	tNET	RR	2	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/CIN
8.918	0.045	tINS	RR	1	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/COUT
8.918	0.000	tNET	RR	2	R54C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n87_s/CIN
8.963	0.045	tINS	RR	1	R54C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n87_s/COUT
8.963	0.000	tNET	RR	2	R54C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n86_s/CIN
9.008	0.045	tINS	RR	1	R54C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n86_s/COUT
9.008	0.000	tNET	RR	2	R54C114[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n85_s/CIN
9.053	0.045	tINS	RR	1	R54C114[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n85_s/COUT
9.053	0.000	tNET	RR	2	R54C114[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n84_s/CIN
9.098	0.045	tINS	RR	1	R54C114[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n84_s/COUT
9.098	0.000	tNET	RR	2	R54C114[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n83_s/CIN
9.143	0.045	tINS	RR	1	R54C114[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n83_s/COUT
9.143	0.000	tNET	RR	2	R54C114[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n82_s/CIN
9.188	0.045	tINS	RR	1	R54C114[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n82_s/COUT
9.188	0.000	tNET	RR	2	R54C115[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n81_s/CIN
9.407	0.219	tINS	RR	1	R54C115[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n81_s/SUM
9.407	0.000	tNET	RR	1	R54C115[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.911	3.295	tNET	RR	1	R54C115[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_19_s0/CLK
23.854	-0.057	tSu		1	R54C115[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_19_s0

Path Statistics:

Clock Skew	-0.035
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 2.191, 40.132%; route: 2.925, 53.564%; tC2Q: 0.344, 6.304%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.295, 100.000%

Path10

Path Summary:

Slack	14.517
Data Arrival Time	9.372
Data Required Time	23.889
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_2_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
6.806	0.045	tINS	RR	1	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/COUT
6.806	0.000	tNET	RR	2	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/CIN
6.851	0.045	tINS	RR	1	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/COUT
6.851	0.000	tNET	RR	2	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/CIN
6.896	0.045	tINS	RR	1	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/COUT
6.896	0.000	tNET	RR	2	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/CIN
6.941	0.045	tINS	RR	1	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/COUT
6.941	0.000	tNET	RR	2	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/CIN
6.986	0.045	tINS	RR	1	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/COUT
6.986	0.000	tNET	RR	2	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/CIN
7.031	0.045	tINS	RR	1	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/COUT
7.031	0.000	tNET	RR	2	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/CIN
7.076	0.045	tINS	RR	1	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/COUT
7.076	0.000	tNET	RR	2	R54C96[2][A]	sscpll0/u_gwfpll/u_sdm2/error_16_s/CIN
7.121	0.045	tINS	RR	1	R54C96[2][A]	sscpll0/u_gwfpll/u_sdm2/error_16_s/COUT
7.121	0.000	tNET	RR	2	R54C96[2][B]	sscpll0/u_gwfpll/u_sdm2/error_17_s/CIN
7.166	0.045	tINS	RR	1	R54C96[2][B]	sscpll0/u_gwfpll/u_sdm2/error_17_s/COUT
7.166	0.000	tNET	RR	2	R54C97[0][A]	sscpll0/u_gwfpll/u_sdm2/error_18_s/CIN
7.211	0.045	tINS	RR	1	R54C97[0][A]	sscpll0/u_gwfpll/u_sdm2/error_18_s/COUT
7.211	0.000	tNET	RR	2	R54C97[0][B]	sscpll0/u_gwfpll/u_sdm2/error_19_s/CIN
7.256	0.045	tINS	RR	1	R54C97[0][B]	sscpll0/u_gwfpll/u_sdm2/error_19_s/COUT
7.256	0.000	tNET	RR	2	R54C97[1][A]	sscpll0/u_gwfpll/u_sdm2/error_20_s/CIN
7.301	0.045	tINS	RR	1	R54C97[1][A]	sscpll0/u_gwfpll/u_sdm2/error_20_s/COUT
7.301	0.000	tNET	RR	2	R54C97[1][B]	sscpll0/u_gwfpll/u_sdm2/out_0_s/CIN
7.346	0.045	tINS	RR	1	R54C97[1][B]	sscpll0/u_gwfpll/u_sdm2/out_0_s/COUT
7.346	0.000	tNET	RR	2	R54C97[2][A]	sscpll0/u_gwfpll/u_sdm2/out_1_s/CIN
7.391	0.045	tINS	RR	1	R54C97[2][A]	sscpll0/u_gwfpll/u_sdm2/out_1_s/COUT
7.391	0.000	tNET	RR	2	R54C97[2][B]	sscpll0/u_gwfpll/u_sdm2/out_2_s/CIN
7.436	0.045	tINS	RR	1	R54C97[2][B]	sscpll0/u_gwfpll/u_sdm2/out_2_s/COUT
7.436	0.000	tNET	RR	2	R54C98[0][A]	sscpll0/u_gwfpll/u_sdm2/out_3_s/CIN
7.481	0.045	tINS	RR	1	R54C98[0][A]	sscpll0/u_gwfpll/u_sdm2/out_3_s/COUT
7.481	0.000	tNET	RR	2	R54C98[0][B]	sscpll0/u_gwfpll/u_sdm2/out_4_s/CIN
7.748	0.267	tINS	RR	1	R54C98[0][B]	sscpll0/u_gwfpll/u_sdm2/out_4_s/SUM
8.566	0.818	tNET	RR	2	R54C80[0][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/n18_s/I0
9.106	0.540	tINS	RF	1	R54C80[0][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/n18_s/COUT
9.106	0.000	tNET	FF	2	R54C80[0][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/n17_s/CIN
9.372	0.267	tINS	FR	1	R54C80[0][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/n17_s/SUM
9.372	0.000	tNET	RR	1	R54C80[0][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.946	3.330	tNET	RR	1	R54C80[0][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_2_s0/CLK
23.889	-0.057	tSu		1	R54C80[0][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 2.603, 47.978%; route: 2.478, 45.677%; tC2Q: 0.344, 6.345%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%

Path11

Path Summary:

Slack	14.526
Data Arrival Time	9.319
Data Required Time	23.845
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_16_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
7.028	0.267	tINS	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/SUM
8.292	1.264	tNET	RR	2	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/I0
8.828	0.535	tINS	RF	1	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/COUT
8.828	0.000	tNET	FF	2	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/CIN
8.873	0.045	tINS	FR	1	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/COUT
8.873	0.000	tNET	RR	2	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/CIN
8.918	0.045	tINS	RR	1	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/COUT
8.918	0.000	tNET	RR	2	R54C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n87_s/CIN
8.963	0.045	tINS	RR	1	R54C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n87_s/COUT
8.963	0.000	tNET	RR	2	R54C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n86_s/CIN
9.008	0.045	tINS	RR	1	R54C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n86_s/COUT
9.008	0.000	tNET	RR	2	R54C114[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n85_s/CIN
9.053	0.045	tINS	RR	1	R54C114[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n85_s/COUT
9.053	0.000	tNET	RR	2	R54C114[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n84_s/CIN
9.320	0.267	tINS	RR	1	R54C114[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n84_s/SUM
9.320	0.000	tNET	RR	1	R54C114[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.903	3.286	tNET	RR	1	R54C114[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_16_s0/CLK
23.845	-0.057	tSu		1	R54C114[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_16_s0

Path Statistics:

Clock Skew	-0.044
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 2.104, 39.154%; route: 2.925, 54.439%; tC2Q: 0.344, 6.407%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.286, 100.000%

Path12

Path Summary:

Slack	14.528
Data Arrival Time	9.317
Data Required Time	23.845
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_17_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
7.028	0.267	tINS	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/SUM
8.292	1.264	tNET	RR	2	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/I0
8.828	0.535	tINS	RF	1	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/COUT
8.828	0.000	tNET	FF	2	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/CIN
8.873	0.045	tINS	FR	1	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/COUT
8.873	0.000	tNET	RR	2	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/CIN
8.918	0.045	tINS	RR	1	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/COUT
8.918	0.000	tNET	RR	2	R54C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n87_s/CIN
8.963	0.045	tINS	RR	1	R54C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n87_s/COUT
8.963	0.000	tNET	RR	2	R54C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n86_s/CIN
9.008	0.045	tINS	RR	1	R54C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n86_s/COUT
9.008	0.000	tNET	RR	2	R54C114[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n85_s/CIN
9.053	0.045	tINS	RR	1	R54C114[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n85_s/COUT
9.053	0.000	tNET	RR	2	R54C114[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n84_s/CIN
9.098	0.045	tINS	RR	1	R54C114[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n84_s/COUT
9.098	0.000	tNET	RR	2	R54C114[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n83_s/CIN
9.317	0.219	tINS	RR	1	R54C114[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n83_s/SUM
9.317	0.000	tNET	RR	1	R54C114[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.903	3.286	tNET	RR	1	R54C114[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_17_s0/CLK
23.845	-0.057	tSu		1	R54C114[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_17_s0

Path Statistics:

Clock Skew	-0.044
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 2.101, 39.129%; route: 2.925, 54.462%; tC2Q: 0.344, 6.410%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.286, 100.000%

Path13

Path Summary:

Slack	14.616
Data Arrival Time	9.229
Data Required Time	23.845
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_14_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
7.028	0.267	tINS	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/SUM
8.292	1.264	tNET	RR	2	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/I0
8.828	0.535	tINS	RF	1	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/COUT
8.828	0.000	tNET	FF	2	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/CIN
8.873	0.045	tINS	FR	1	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/COUT
8.873	0.000	tNET	RR	2	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/CIN
8.918	0.045	tINS	RR	1	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/COUT
8.918	0.000	tNET	RR	2	R54C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n87_s/CIN
8.963	0.045	tINS	RR	1	R54C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n87_s/COUT
8.963	0.000	tNET	RR	2	R54C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n86_s/CIN
9.230	0.267	tINS	RR	1	R54C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n86_s/SUM
9.230	0.000	tNET	RR	1	R54C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.903	3.286	tNET	RR	1	R54C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_14_s0/CLK
23.845	-0.057	tSu		1	R54C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_14_s0

Path Statistics:

Clock Skew	-0.044
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 2.014, 38.118%; route: 2.925, 55.366%; tC2Q: 0.344, 6.516%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.286, 100.000%

Path14

Path Summary:

Slack	14.618
Data Arrival Time	9.227
Data Required Time	23.845
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_15_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
7.028	0.267	tINS	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/SUM
8.292	1.264	tNET	RR	2	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/I0
8.828	0.535	tINS	RF	1	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/COUT
8.828	0.000	tNET	FF	2	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/CIN
8.873	0.045	tINS	FR	1	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/COUT
8.873	0.000	tNET	RR	2	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/CIN
8.918	0.045	tINS	RR	1	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/COUT
8.918	0.000	tNET	RR	2	R54C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n87_s/CIN
8.963	0.045	tINS	RR	1	R54C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n87_s/COUT
8.963	0.000	tNET	RR	2	R54C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n86_s/CIN
9.008	0.045	tINS	RR	1	R54C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n86_s/COUT
9.008	0.000	tNET	RR	2	R54C114[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n85_s/CIN
9.227	0.219	tINS	RR	1	R54C114[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n85_s/SUM
9.227	0.000	tNET	RR	1	R54C114[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.903	3.286	tNET	RR	1	R54C114[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_15_s0/CLK
23.845	-0.057	tSu		1	R54C114[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_15_s0

Path Statistics:

Clock Skew	-0.044
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 2.011, 38.091%; route: 2.925, 55.390%; tC2Q: 0.344, 6.519%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.286, 100.000%

Path15

Path Summary:

Slack	14.620
Data Arrival Time	9.269
Data Required Time	23.889
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_1_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
6.806	0.045	tINS	RR	1	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/COUT
6.806	0.000	tNET	RR	2	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/CIN
6.851	0.045	tINS	RR	1	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/COUT
6.851	0.000	tNET	RR	2	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/CIN
6.896	0.045	tINS	RR	1	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/COUT
6.896	0.000	tNET	RR	2	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/CIN
6.941	0.045	tINS	RR	1	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/COUT
6.941	0.000	tNET	RR	2	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/CIN
6.986	0.045	tINS	RR	1	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/COUT
6.986	0.000	tNET	RR	2	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/CIN
7.031	0.045	tINS	RR	1	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/COUT
7.031	0.000	tNET	RR	2	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/CIN
7.076	0.045	tINS	RR	1	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/COUT
7.076	0.000	tNET	RR	2	R54C96[2][A]	sscpll0/u_gwfpll/u_sdm2/error_16_s/CIN
7.121	0.045	tINS	RR	1	R54C96[2][A]	sscpll0/u_gwfpll/u_sdm2/error_16_s/COUT
7.121	0.000	tNET	RR	2	R54C96[2][B]	sscpll0/u_gwfpll/u_sdm2/error_17_s/CIN
7.166	0.045	tINS	RR	1	R54C96[2][B]	sscpll0/u_gwfpll/u_sdm2/error_17_s/COUT
7.166	0.000	tNET	RR	2	R54C97[0][A]	sscpll0/u_gwfpll/u_sdm2/error_18_s/CIN
7.211	0.045	tINS	RR	1	R54C97[0][A]	sscpll0/u_gwfpll/u_sdm2/error_18_s/COUT
7.211	0.000	tNET	RR	2	R54C97[0][B]	sscpll0/u_gwfpll/u_sdm2/error_19_s/CIN
7.256	0.045	tINS	RR	1	R54C97[0][B]	sscpll0/u_gwfpll/u_sdm2/error_19_s/COUT
7.256	0.000	tNET	RR	2	R54C97[1][A]	sscpll0/u_gwfpll/u_sdm2/error_20_s/CIN
7.301	0.045	tINS	RR	1	R54C97[1][A]	sscpll0/u_gwfpll/u_sdm2/error_20_s/COUT
7.301	0.000	tNET	RR	2	R54C97[1][B]	sscpll0/u_gwfpll/u_sdm2/out_0_s/CIN
7.346	0.045	tINS	RR	1	R54C97[1][B]	sscpll0/u_gwfpll/u_sdm2/out_0_s/COUT
7.346	0.000	tNET	RR	2	R54C97[2][A]	sscpll0/u_gwfpll/u_sdm2/out_1_s/CIN
7.391	0.045	tINS	RR	1	R54C97[2][A]	sscpll0/u_gwfpll/u_sdm2/out_1_s/COUT
7.391	0.000	tNET	RR	2	R54C97[2][B]	sscpll0/u_gwfpll/u_sdm2/out_2_s/CIN
7.436	0.045	tINS	RR	1	R54C97[2][B]	sscpll0/u_gwfpll/u_sdm2/out_2_s/COUT
7.436	0.000	tNET	RR	2	R54C98[0][A]	sscpll0/u_gwfpll/u_sdm2/out_3_s/CIN
7.481	0.045	tINS	RR	1	R54C98[0][A]	sscpll0/u_gwfpll/u_sdm2/out_3_s/COUT
7.481	0.000	tNET	RR	2	R54C98[0][B]	sscpll0/u_gwfpll/u_sdm2/out_4_s/CIN
7.748	0.267	tINS	RR	1	R54C98[0][B]	sscpll0/u_gwfpll/u_sdm2/out_4_s/SUM
8.566	0.818	tNET	RR	2	R54C80[0][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/n18_s/I0
9.269	0.703	tINS	RR	1	R54C80[0][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/n18_s/SUM
9.269	0.000	tNET	RR	1	R54C80[0][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.946	3.330	tNET	RR	1	R54C80[0][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_1_s0/CLK
23.889	-0.057	tSu		1	R54C80[0][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 2.500, 46.967%; route: 2.478, 46.565%; tC2Q: 0.344, 6.468%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%

Path16

Path Summary:

Slack	14.697
Data Arrival Time	9.139
Data Required Time	23.837
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_12_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
7.028	0.267	tINS	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/SUM
8.292	1.264	tNET	RR	2	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/I0
8.828	0.535	tINS	RF	1	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/COUT
8.828	0.000	tNET	FF	2	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/CIN
8.873	0.045	tINS	FR	1	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/COUT
8.873	0.000	tNET	RR	2	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/CIN
9.140	0.267	tINS	RR	1	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/SUM
9.140	0.000	tNET	RR	1	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.894	3.278	tNET	RR	1	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_12_s0/CLK
23.837	-0.057	tSu		1	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_12_s0

Path Statistics:

Clock Skew	-0.052
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 1.924, 37.045%; route: 2.925, 56.326%; tC2Q: 0.344, 6.629%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.278, 100.000%

Path17

Path Summary:

Slack	14.708
Data Arrival Time	9.137
Data Required Time	23.845
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_13_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
7.028	0.267	tINS	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/SUM
8.292	1.264	tNET	RR	2	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/I0
8.828	0.535	tINS	RF	1	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/COUT
8.828	0.000	tNET	FF	2	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/CIN
8.873	0.045	tINS	FR	1	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/COUT
8.873	0.000	tNET	RR	2	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/CIN
8.918	0.045	tINS	RR	1	R54C113[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/COUT
8.918	0.000	tNET	RR	2	R54C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n87_s/CIN
9.137	0.219	tINS	RR	1	R54C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n87_s/SUM
9.137	0.000	tNET	RR	1	R54C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.903	3.286	tNET	RR	1	R54C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_13_s0/CLK
23.845	-0.057	tSu		1	R54C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_13_s0

Path Statistics:

Clock Skew	-0.044
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 1.922, 37.018%; route: 2.925, 56.350%; tC2Q: 0.344, 6.632%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.286, 100.000%

Path18

Path Summary:

Slack	14.790
Data Arrival Time	9.047
Data Required Time	23.837
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_11_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
7.028	0.267	tINS	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/SUM
8.292	1.264	tNET	RR	2	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/I0
8.828	0.535	tINS	RF	1	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/COUT
8.828	0.000	tNET	FF	2	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/CIN
9.047	0.219	tINS	FR	1	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/SUM
9.047	0.000	tNET	RR	1	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.894	3.278	tNET	RR	1	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_11_s0/CLK
23.837	-0.057	tSu		1	R54C113[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_11_s0

Path Statistics:

Clock Skew	-0.052
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 1.832, 35.906%; route: 2.925, 57.345%; tC2Q: 0.344, 6.749%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.278, 100.000%

Path19

Path Summary:

Slack	14.800
Data Arrival Time	9.098
Data Required Time	23.898
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_mdiv_code_conv/frac_o_2_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
6.806	0.045	tINS	RR	1	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/COUT
6.806	0.000	tNET	RR	2	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/CIN
6.851	0.045	tINS	RR	1	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/COUT
6.851	0.000	tNET	RR	2	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/CIN
6.896	0.045	tINS	RR	1	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/COUT
6.896	0.000	tNET	RR	2	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/CIN
6.941	0.045	tINS	RR	1	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/COUT
6.941	0.000	tNET	RR	2	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/CIN
6.986	0.045	tINS	RR	1	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/COUT
6.986	0.000	tNET	RR	2	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/CIN
7.031	0.045	tINS	RR	1	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/COUT
7.031	0.000	tNET	RR	2	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/CIN
7.076	0.045	tINS	RR	1	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/COUT
7.076	0.000	tNET	RR	2	R54C96[2][A]	sscpll0/u_gwfpll/u_sdm2/error_16_s/CIN
7.121	0.045	tINS	RR	1	R54C96[2][A]	sscpll0/u_gwfpll/u_sdm2/error_16_s/COUT
7.121	0.000	tNET	RR	2	R54C96[2][B]	sscpll0/u_gwfpll/u_sdm2/error_17_s/CIN
7.166	0.045	tINS	RR	1	R54C96[2][B]	sscpll0/u_gwfpll/u_sdm2/error_17_s/COUT
7.166	0.000	tNET	RR	2	R54C97[0][A]	sscpll0/u_gwfpll/u_sdm2/error_18_s/CIN
7.211	0.045	tINS	RR	1	R54C97[0][A]	sscpll0/u_gwfpll/u_sdm2/error_18_s/COUT
7.211	0.000	tNET	RR	2	R54C97[0][B]	sscpll0/u_gwfpll/u_sdm2/error_19_s/CIN
7.256	0.045	tINS	RR	1	R54C97[0][B]	sscpll0/u_gwfpll/u_sdm2/error_19_s/COUT
7.256	0.000	tNET	RR	2	R54C97[1][A]	sscpll0/u_gwfpll/u_sdm2/error_20_s/CIN
7.301	0.045	tINS	RR	1	R54C97[1][A]	sscpll0/u_gwfpll/u_sdm2/error_20_s/COUT
7.301	0.000	tNET	RR	2	R54C97[1][B]	sscpll0/u_gwfpll/u_sdm2/out_0_s/CIN
7.346	0.045	tINS	RR	1	R54C97[1][B]	sscpll0/u_gwfpll/u_sdm2/out_0_s/COUT
7.346	0.000	tNET	RR	2	R54C97[2][A]	sscpll0/u_gwfpll/u_sdm2/out_1_s/CIN
7.391	0.045	tINS	RR	1	R54C97[2][A]	sscpll0/u_gwfpll/u_sdm2/out_1_s/COUT
7.391	0.000	tNET	RR	2	R54C97[2][B]	sscpll0/u_gwfpll/u_sdm2/out_2_s/CIN
7.658	0.267	tINS	RR	1	R54C97[2][B]	sscpll0/u_gwfpll/u_sdm2/out_2_s/SUM
8.577	0.919	tNET	RR	1	R54C79[0][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/n20_6_s0/I0
9.098	0.521	tINS	RR	1	R54C79[0][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/n20_6_s0/F
9.098	0.000	tNET	RR	1	R54C79[0][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/frac_o_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.955	3.338	tNET	RR	1	R54C79[0][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/frac_o_2_s0/CLK
23.898	-0.057	tSu		1	R54C79[0][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/frac_o_2_s0

Path Statistics:

Clock Skew	0.008
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 2.227, 43.241%; route: 2.580, 50.076%; tC2Q: 0.344, 6.683%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.338, 100.000%

Path20

Path Summary:

Slack	14.835
Data Arrival Time	9.010
Data Required Time	23.845
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_0_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
6.806	0.045	tINS	RR	1	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/COUT
6.806	0.000	tNET	RR	2	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/CIN
6.851	0.045	tINS	RR	1	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/COUT
6.851	0.000	tNET	RR	2	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/CIN
6.896	0.045	tINS	RR	1	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/COUT
6.896	0.000	tNET	RR	2	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/CIN
6.941	0.045	tINS	RR	1	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/COUT
6.941	0.000	tNET	RR	2	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/CIN
6.986	0.045	tINS	RR	1	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/COUT
6.986	0.000	tNET	RR	2	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/CIN
7.031	0.045	tINS	RR	1	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/COUT
7.031	0.000	tNET	RR	2	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/CIN
7.076	0.045	tINS	RR	1	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/COUT
7.076	0.000	tNET	RR	2	R54C96[2][A]	sscpll0/u_gwfpll/u_sdm2/error_16_s/CIN
7.121	0.045	tINS	RR	1	R54C96[2][A]	sscpll0/u_gwfpll/u_sdm2/error_16_s/COUT
7.121	0.000	tNET	RR	2	R54C96[2][B]	sscpll0/u_gwfpll/u_sdm2/error_17_s/CIN
7.166	0.045	tINS	RR	1	R54C96[2][B]	sscpll0/u_gwfpll/u_sdm2/error_17_s/COUT
7.166	0.000	tNET	RR	2	R54C97[0][A]	sscpll0/u_gwfpll/u_sdm2/error_18_s/CIN
7.211	0.045	tINS	RR	1	R54C97[0][A]	sscpll0/u_gwfpll/u_sdm2/error_18_s/COUT
7.211	0.000	tNET	RR	2	R54C97[0][B]	sscpll0/u_gwfpll/u_sdm2/error_19_s/CIN
7.256	0.045	tINS	RR	1	R54C97[0][B]	sscpll0/u_gwfpll/u_sdm2/error_19_s/COUT
7.256	0.000	tNET	RR	2	R54C97[1][A]	sscpll0/u_gwfpll/u_sdm2/error_20_s/CIN
7.301	0.045	tINS	RR	1	R54C97[1][A]	sscpll0/u_gwfpll/u_sdm2/error_20_s/COUT
7.301	0.000	tNET	RR	2	R54C97[1][B]	sscpll0/u_gwfpll/u_sdm2/out_0_s/CIN
7.346	0.045	tINS	RR	1	R54C97[1][B]	sscpll0/u_gwfpll/u_sdm2/out_0_s/COUT
7.346	0.000	tNET	RR	2	R54C97[2][A]	sscpll0/u_gwfpll/u_sdm2/out_1_s/CIN
7.391	0.045	tINS	RR	1	R54C97[2][A]	sscpll0/u_gwfpll/u_sdm2/out_1_s/COUT
7.391	0.000	tNET	RR	2	R54C97[2][B]	sscpll0/u_gwfpll/u_sdm2/out_2_s/CIN
7.436	0.045	tINS	RR	1	R54C97[2][B]	sscpll0/u_gwfpll/u_sdm2/out_2_s/COUT
7.436	0.000	tNET	RR	2	R54C98[0][A]	sscpll0/u_gwfpll/u_sdm2/out_3_s/CIN
7.656	0.219	tINS	RR	2	R54C98[0][A]	sscpll0/u_gwfpll/u_sdm2/out_3_s/SUM
9.010	1.355	tNET	RR	1	R54C118[1][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.903	3.286	tNET	RR	1	R54C118[1][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_0_s0/CLK
23.845	-0.057	tSu		1	R54C118[1][B]	sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_0_s0

Path Statistics:

Clock Skew	-0.044
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 1.704, 33.659%; route: 3.015, 59.542%; tC2Q: 0.344, 6.798%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.286, 100.000%

Path21

Path Summary:

Slack	14.839
Data Arrival Time	8.998
Data Required Time	23.837
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_10_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
7.028	0.267	tINS	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/SUM
8.292	1.264	tNET	RR	2	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/I0
8.998	0.705	tINS	RR	1	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/SUM
8.998	0.000	tNET	RR	1	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.894	3.278	tNET	RR	1	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_10_s0/CLK
23.837	-0.057	tSu		1	R54C113[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_10_s0

Path Statistics:

Clock Skew	-0.052
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 1.782, 35.278%; route: 2.925, 57.906%; tC2Q: 0.344, 6.815%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.278, 100.000%

Path22

Path Summary:

Slack	14.869
Data Arrival Time	8.974
Data Required Time	23.844
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_15_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
6.806	0.045	tINS	RR	1	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/COUT
6.806	0.000	tNET	RR	2	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/CIN
6.851	0.045	tINS	RR	1	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/COUT
6.851	0.000	tNET	RR	2	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/CIN
6.896	0.045	tINS	RR	1	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/COUT
6.896	0.000	tNET	RR	2	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/CIN
6.941	0.045	tINS	RR	1	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/COUT
6.941	0.000	tNET	RR	2	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/CIN
6.986	0.045	tINS	RR	1	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/COUT
6.986	0.000	tNET	RR	2	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/CIN
7.031	0.045	tINS	RR	1	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/COUT
7.031	0.000	tNET	RR	2	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/CIN
7.298	0.267	tINS	RR	2	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/SUM
8.974	1.676	tNET	RR	1	R53C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.901	3.284	tNET	RR	1	R53C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_15_s0/CLK
23.844	-0.057	tSu		1	R53C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_15_s0

Path Statistics:

Clock Skew	-0.046
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 1.347, 26.785%; route: 3.337, 66.368%; tC2Q: 0.344, 6.847%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.284, 100.000%

Path23

Path Summary:

Slack	14.954
Data Arrival Time	8.944
Data Required Time	23.898
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_mdiv_code_conv/frac_o_0_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
6.806	0.045	tINS	RR	1	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/COUT
6.806	0.000	tNET	RR	2	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/CIN
6.851	0.045	tINS	RR	1	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/COUT
6.851	0.000	tNET	RR	2	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/CIN
6.896	0.045	tINS	RR	1	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/COUT
6.896	0.000	tNET	RR	2	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/CIN
6.941	0.045	tINS	RR	1	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/COUT
6.941	0.000	tNET	RR	2	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/CIN
6.986	0.045	tINS	RR	1	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/COUT
6.986	0.000	tNET	RR	2	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/CIN
7.031	0.045	tINS	RR	1	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/COUT
7.031	0.000	tNET	RR	2	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/CIN
7.076	0.045	tINS	RR	1	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/COUT
7.076	0.000	tNET	RR	2	R54C96[2][A]	sscpll0/u_gwfpll/u_sdm2/error_16_s/CIN
7.121	0.045	tINS	RR	1	R54C96[2][A]	sscpll0/u_gwfpll/u_sdm2/error_16_s/COUT
7.121	0.000	tNET	RR	2	R54C96[2][B]	sscpll0/u_gwfpll/u_sdm2/error_17_s/CIN
7.166	0.045	tINS	RR	1	R54C96[2][B]	sscpll0/u_gwfpll/u_sdm2/error_17_s/COUT
7.166	0.000	tNET	RR	2	R54C97[0][A]	sscpll0/u_gwfpll/u_sdm2/error_18_s/CIN
7.211	0.045	tINS	RR	1	R54C97[0][A]	sscpll0/u_gwfpll/u_sdm2/error_18_s/COUT
7.211	0.000	tNET	RR	2	R54C97[0][B]	sscpll0/u_gwfpll/u_sdm2/error_19_s/CIN
7.256	0.045	tINS	RR	1	R54C97[0][B]	sscpll0/u_gwfpll/u_sdm2/error_19_s/COUT
7.256	0.000	tNET	RR	2	R54C97[1][A]	sscpll0/u_gwfpll/u_sdm2/error_20_s/CIN
7.301	0.045	tINS	RR	1	R54C97[1][A]	sscpll0/u_gwfpll/u_sdm2/error_20_s/COUT
7.301	0.000	tNET	RR	2	R54C97[1][B]	sscpll0/u_gwfpll/u_sdm2/out_0_s/CIN
7.568	0.267	tINS	RR	1	R54C97[1][B]	sscpll0/u_gwfpll/u_sdm2/out_0_s/SUM
8.487	0.919	tNET	RR	1	R54C79[0][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/n22_6_s0/I0
8.944	0.457	tINS	RR	1	R54C79[0][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/n22_6_s0/F
8.944	0.000	tNET	RR	1	R54C79[0][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/frac_o_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.955	3.338	tNET	RR	1	R54C79[0][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/frac_o_0_s0/CLK
23.898	-0.057	tSu		1	R54C79[0][A]	sscpll0/u_gwfpll/u_mdiv_code_conv/frac_o_0_s0

Path Statistics:

Clock Skew	0.008
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 2.073, 41.490%; route: 2.580, 51.621%; tC2Q: 0.344, 6.889%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.338, 100.000%

Path24

Path Summary:

Slack	14.980
Data Arrival Time	8.880
Data Required Time	23.859
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_20_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
6.806	0.045	tINS	RR	1	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/COUT
6.806	0.000	tNET	RR	2	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/CIN
6.851	0.045	tINS	RR	1	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/COUT
6.851	0.000	tNET	RR	2	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/CIN
6.896	0.045	tINS	RR	1	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/COUT
6.896	0.000	tNET	RR	2	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/CIN
6.941	0.045	tINS	RR	1	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/COUT
6.941	0.000	tNET	RR	2	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/CIN
6.986	0.045	tINS	RR	1	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/COUT
6.986	0.000	tNET	RR	2	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/CIN
7.031	0.045	tINS	RR	1	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/COUT
7.031	0.000	tNET	RR	2	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/CIN
7.076	0.045	tINS	RR	1	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/COUT
7.076	0.000	tNET	RR	2	R54C96[2][A]	sscpll0/u_gwfpll/u_sdm2/error_16_s/CIN
7.121	0.045	tINS	RR	1	R54C96[2][A]	sscpll0/u_gwfpll/u_sdm2/error_16_s/COUT
7.121	0.000	tNET	RR	2	R54C96[2][B]	sscpll0/u_gwfpll/u_sdm2/error_17_s/CIN
7.166	0.045	tINS	RR	1	R54C96[2][B]	sscpll0/u_gwfpll/u_sdm2/error_17_s/COUT
7.166	0.000	tNET	RR	2	R54C97[0][A]	sscpll0/u_gwfpll/u_sdm2/error_18_s/CIN
7.211	0.045	tINS	RR	1	R54C97[0][A]	sscpll0/u_gwfpll/u_sdm2/error_18_s/COUT
7.211	0.000	tNET	RR	2	R54C97[0][B]	sscpll0/u_gwfpll/u_sdm2/error_19_s/CIN
7.256	0.045	tINS	RR	1	R54C97[0][B]	sscpll0/u_gwfpll/u_sdm2/error_19_s/COUT
7.256	0.000	tNET	RR	2	R54C97[1][A]	sscpll0/u_gwfpll/u_sdm2/error_20_s/CIN
7.476	0.219	tINS	RF	2	R54C97[1][A]	sscpll0/u_gwfpll/u_sdm2/error_20_s/SUM
8.880	1.404	tNET	FF	1	R54C115[3][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.911	3.295	tNET	RR	1	R54C115[3][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_20_s0/CLK
23.859	-0.052	tSu		1	R54C115[3][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_20_s0

Path Statistics:

Clock Skew	-0.035
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 1.524, 30.901%; route: 3.065, 62.121%; tC2Q: 0.344, 6.978%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.295, 100.000%

Path25

Path Summary:

Slack	14.985
Data Arrival Time	8.868
Data Required Time	23.854
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_19_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.946	3.330	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
4.291	0.344	tC2Q	RR	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
5.951	1.661	tNET	RR	2	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/I0
6.491	0.540	tINS	RF	1	R54C94[1][A]	sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
6.491	0.000	tNET	FF	2	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
6.536	0.045	tINS	FR	1	R54C94[1][B]	sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
6.536	0.000	tNET	RR	2	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
6.581	0.045	tINS	RR	1	R54C94[2][A]	sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
6.581	0.000	tNET	RR	2	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
6.626	0.045	tINS	RR	1	R54C94[2][B]	sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
6.626	0.000	tNET	RR	2	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
6.671	0.045	tINS	RR	1	R54C95[0][A]	sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
6.671	0.000	tNET	RR	2	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
6.716	0.045	tINS	RR	1	R54C95[0][B]	sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
6.716	0.000	tNET	RR	2	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
6.761	0.045	tINS	RR	1	R54C95[1][A]	sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
6.761	0.000	tNET	RR	2	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
6.806	0.045	tINS	RR	1	R54C95[1][B]	sscpll0/u_gwfpll/u_sdm2/error_9_s/COUT
6.806	0.000	tNET	RR	2	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/CIN
6.851	0.045	tINS	RR	1	R54C95[2][A]	sscpll0/u_gwfpll/u_sdm2/error_10_s/COUT
6.851	0.000	tNET	RR	2	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/CIN
6.896	0.045	tINS	RR	1	R54C95[2][B]	sscpll0/u_gwfpll/u_sdm2/error_11_s/COUT
6.896	0.000	tNET	RR	2	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/CIN
6.941	0.045	tINS	RR	1	R54C96[0][A]	sscpll0/u_gwfpll/u_sdm2/error_12_s/COUT
6.941	0.000	tNET	RR	2	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/CIN
6.986	0.045	tINS	RR	1	R54C96[0][B]	sscpll0/u_gwfpll/u_sdm2/error_13_s/COUT
6.986	0.000	tNET	RR	2	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/CIN
7.031	0.045	tINS	RR	1	R54C96[1][A]	sscpll0/u_gwfpll/u_sdm2/error_14_s/COUT
7.031	0.000	tNET	RR	2	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/CIN
7.076	0.045	tINS	RR	1	R54C96[1][B]	sscpll0/u_gwfpll/u_sdm2/error_15_s/COUT
7.076	0.000	tNET	RR	2	R54C96[2][A]	sscpll0/u_gwfpll/u_sdm2/error_16_s/CIN
7.121	0.045	tINS	RR	1	R54C96[2][A]	sscpll0/u_gwfpll/u_sdm2/error_16_s/COUT
7.121	0.000	tNET	RR	2	R54C96[2][B]	sscpll0/u_gwfpll/u_sdm2/error_17_s/CIN
7.166	0.045	tINS	RR	1	R54C96[2][B]	sscpll0/u_gwfpll/u_sdm2/error_17_s/COUT
7.166	0.000	tNET	RR	2	R54C97[0][A]	sscpll0/u_gwfpll/u_sdm2/error_18_s/CIN
7.211	0.045	tINS	RR	1	R54C97[0][A]	sscpll0/u_gwfpll/u_sdm2/error_18_s/COUT
7.211	0.000	tNET	RR	2	R54C97[0][B]	sscpll0/u_gwfpll/u_sdm2/error_19_s/CIN
7.478	0.267	tINS	RR	2	R54C97[0][B]	sscpll0/u_gwfpll/u_sdm2/error_19_s/SUM
8.868	1.391	tNET	RR	1	R54C115[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.911	3.295	tNET	RR	1	R54C115[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_19_s0/CLK
23.854	-0.057	tSu		1	R54C115[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_19_s0

Path Statistics:

Clock Skew	-0.035
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%
Arrival Data Path Delay	cell: 1.527, 31.017%; route: 3.051, 61.989%; tC2Q: 0.344, 6.994%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.295, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.250
Data Arrival Time	2.154
Data Required Time	1.904
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_0_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/div_o_0_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.881	1.271	tNET	RR	1	R54C78[0][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_0_s0/CLK
2.008	0.127	tC2Q	RF	3	R54C78[0][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_0_s0/Q
2.016	0.008	tNET	FF	1	R54C78[0][A]	sscpll0/u_gwfpll/u_triangle_codegen/n74_6_s0/I0
2.154	0.138	tINS	FF	1	R54C78[0][A]	sscpll0/u_gwfpll/u_triangle_codegen/n74_6_s0/F
2.154	0.000	tNET	FF	1	R54C78[0][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.881	1.271	tNET	RR	1	R54C78[0][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_0_s0/CLK
1.904	0.022	tHld		1	R54C78[0][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.271, 100.000%
Arrival Data Path Delay	cell: 0.138, 50.495%; route: 0.008, 2.970%; tC2Q: 0.127, 46.535%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.271, 100.000%

Path2

Path Summary:

Slack	0.250
Data Arrival Time	2.150
Data Required Time	1.900
From	rstn_cnt_0_s1
To	rstn_cnt_0_s1
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[0][A]	rstn_cnt_0_s1/CLK
2.005	0.127	tC2Q	RF	5	R54C87[0][A]	rstn_cnt_0_s1/Q
2.013	0.008	tNET	FF	1	R54C87[0][A]	rstn_cnt_0_s4/I3
2.150	0.138	tINS	FF	1	R54C87[0][A]	rstn_cnt_0_s4/F
2.150	0.000	tNET	FF	1	R54C87[0][A]	rstn_cnt_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[0][A]	rstn_cnt_0_s1/CLK
1.900	0.022	tHld		1	R54C87[0][A]	rstn_cnt_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.138, 50.495%; route: 0.008, 2.970%; tC2Q: 0.127, 46.535%
Required Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%

Path3

Path Summary:

Slack	0.295
Data Arrival Time	2.202
Data Required Time	1.906
From	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_1_s0
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_1_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.884	1.276	tNET	RR	1	R54C93[2][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_1_s0/CLK
2.011	0.127	tC2Q	RF	12	R54C93[2][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_1_s0/Q
2.016	0.005	tNET	FF	1	R54C93[2][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/n516_s7/I2
2.202	0.185	tINS	FF	1	R54C93[2][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/n516_s7/F
2.202	0.000	tNET	FF	1	R54C93[2][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.884	1.276	tNET	RR	1	R54C93[2][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_1_s0/CLK
1.906	0.022	tHld		1	R54C93[2][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.608, 32.270%; route: 1.276, 67.730%
Arrival Data Path Delay	cell: 0.185, 58.357%; route: 0.005, 1.700%; tC2Q: 0.127, 39.943%
Required Clock Path Delay	cell: 0.608, 32.270%; route: 1.276, 67.730%

Path4

Path Summary:

Slack	0.295
Data Arrival Time	2.199
Data Required Time	1.904
From	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_0_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_0_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.881	1.271	tNET	RR	1	R54C78[2][A]	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_0_s0/CLK
2.008	0.127	tC2Q	RF	3	R54C78[2][A]	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_0_s0/Q
2.014	0.005	tNET	FF	1	R54C78[2][A]	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/n33_6_s0/I0
2.199	0.185	tINS	FF	1	R54C78[2][A]	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/n33_6_s0/F
2.199	0.000	tNET	FF	1	R54C78[2][A]	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.881	1.271	tNET	RR	1	R54C78[2][A]	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_0_s0/CLK
1.904	0.022	tHld		1	R54C78[2][A]	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.271, 100.000%
Arrival Data Path Delay	cell: 0.185, 58.357%; route: 0.005, 1.700%; tC2Q: 0.127, 39.943%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.271, 100.000%

Path5

Path Summary:

Slack	0.301
Data Arrival Time	2.202
Data Required Time	1.900
From	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_0_s0
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[1][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_0_s0/CLK
2.005	0.127	tC2Q	RF	1	R54C87[1][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_0_s0/Q
2.202	0.197	tNET	FF	1	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/CLK
1.900	0.022	tHld		1	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.197, 60.833%; tC2Q: 0.127, 39.167%
Required Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%

Path6

Path Summary:

Slack	0.304
Data Arrival Time	2.203
Data Required Time	1.899
From	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_0_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.877	1.266	tNET	RR	1	R54C101[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_0_s0/CLK
2.004	0.127	tC2Q	RF	2	R54C101[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_0_s0/Q
2.203	0.200	tNET	FF	1	R54C101[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.877	1.266	tNET	RR	1	R54C101[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0/CLK
1.899	0.022	tHld		1	R54C101[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.266, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.200, 61.157%; tC2Q: 0.127, 38.843%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.266, 100.000%

Path7

Path Summary:

Slack	0.310
Data Arrival Time	2.216
Data Required Time	1.906
From	rstn_cnt_1_s1
To	rstn_cnt_2_s1
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.884	1.276	tNET	RR	1	R54C93[0][B]	rstn_cnt_1_s1/CLK
2.011	0.127	tC2Q	RF	5	R54C93[0][B]	rstn_cnt_1_s1/Q
2.078	0.067	tNET	FF	1	R54C93[0][A]	rstn_cnt_2_s3/I2
2.216	0.138	tINS	FF	1	R54C93[0][A]	rstn_cnt_2_s3/F
2.216	0.000	tNET	FF	1	R54C93[0][A]	rstn_cnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.884	1.276	tNET	RR	1	R54C93[0][A]	rstn_cnt_2_s1/CLK
1.906	0.022	tHld		1	R54C93[0][A]	rstn_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.608, 32.270%; route: 1.276, 67.730%
Arrival Data Path Delay	cell: 0.138, 41.463%; route: 0.067, 20.325%; tC2Q: 0.127, 38.211%
Required Clock Path Delay	cell: 0.608, 32.270%; route: 1.276, 67.730%

Path8

Path Summary:

Slack	0.310
Data Arrival Time	2.216
Data Required Time	1.906
From	rstn_cnt_1_s1
To	rstn_cnt_1_s1
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.884	1.276	tNET	RR	1	R54C93[0][B]	rstn_cnt_1_s1/CLK
2.011	0.127	tC2Q	RF	5	R54C93[0][B]	rstn_cnt_1_s1/Q
2.078	0.067	tNET	FF	1	R54C93[0][B]	rstn_cnt_1_s3/I3
2.216	0.138	tINS	FF	1	R54C93[0][B]	rstn_cnt_1_s3/F
2.216	0.000	tNET	FF	1	R54C93[0][B]	rstn_cnt_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.884	1.276	tNET	RR	1	R54C93[0][B]	rstn_cnt_1_s1/CLK
1.906	0.022	tHld		1	R54C93[0][B]	rstn_cnt_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.608, 32.270%; route: 1.276, 67.730%
Arrival Data Path Delay	cell: 0.138, 41.463%; route: 0.067, 20.325%; tC2Q: 0.127, 38.211%
Required Clock Path Delay	cell: 0.608, 32.270%; route: 1.276, 67.730%

Path9

Path Summary:

Slack	0.310
Data Arrival Time	2.216
Data Required Time	1.906
From	rstn_cnt_1_s1
To	rstn_cnt_3_s1
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.884	1.276	tNET	RR	1	R54C93[0][B]	rstn_cnt_1_s1/CLK
2.011	0.127	tC2Q	RF	5	R54C93[0][B]	rstn_cnt_1_s1/Q
2.078	0.067	tNET	FF	1	R54C93[1][A]	rstn_cnt_3_s3/I0
2.216	0.138	tINS	FF	1	R54C93[1][A]	rstn_cnt_3_s3/F
2.216	0.000	tNET	FF	1	R54C93[1][A]	rstn_cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.884	1.276	tNET	RR	1	R54C93[1][A]	rstn_cnt_3_s1/CLK
1.906	0.022	tHld		1	R54C93[1][A]	rstn_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.608, 32.270%; route: 1.276, 67.730%
Arrival Data Path Delay	cell: 0.138, 41.463%; route: 0.067, 20.325%; tC2Q: 0.127, 38.211%
Required Clock Path Delay	cell: 0.608, 32.270%; route: 1.276, 67.730%

Path10

Path Summary:

Slack	0.333
Data Arrival Time	2.239
Data Required Time	1.906
From	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_1_s1
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_9_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.880	1.272	tNET	RR	1	R54C108[1][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_1_s1/CLK
2.010	0.130	tC2Q	RR	14	R54C108[1][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_1_s1/Q
2.102	0.092	tNET	RR	1	R54C109[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/n27_s21/I1
2.239	0.138	tINS	RF	1	R54C109[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/n27_s21/F
2.239	0.000	tNET	FF	1	R54C109[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.884	1.276	tNET	RR	1	R54C109[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_9_s0/CLK
1.906	0.022	tHld		1	R54C109[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_9_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.608, 32.332%; route: 1.272, 67.668%
Arrival Data Path Delay	cell: 0.138, 38.346%; route: 0.092, 25.564%; tC2Q: 0.130, 36.090%
Required Clock Path Delay	cell: 0.608, 32.270%; route: 1.276, 67.730%

Path11

Path Summary:

Slack	0.333
Data Arrival Time	2.239
Data Required Time	1.906
From	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_1_s1
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_10_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.880	1.272	tNET	RR	1	R54C108[1][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_1_s1/CLK
2.010	0.130	tC2Q	RR	14	R54C108[1][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_1_s1/Q
2.102	0.092	tNET	RR	1	R54C109[0][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/n26_s22/I1
2.239	0.138	tINS	RF	1	R54C109[0][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/n26_s22/F
2.239	0.000	tNET	FF	1	R54C109[0][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.884	1.276	tNET	RR	1	R54C109[0][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_10_s0/CLK
1.906	0.022	tHld		1	R54C109[0][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_10_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.608, 32.332%; route: 1.272, 67.668%
Arrival Data Path Delay	cell: 0.138, 38.346%; route: 0.092, 25.564%; tC2Q: 0.130, 36.090%
Required Clock Path Delay	cell: 0.608, 32.270%; route: 1.276, 67.730%

Path12

Path Summary:

Slack	0.333
Data Arrival Time	2.237
Data Required Time	1.904
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.881	1.271	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
2.008	0.127	tC2Q	RF	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/Q
2.014	0.005	tNET	FF	2	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/n72_s/I0
2.237	0.223	tINS	FF	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/n72_s/SUM
2.237	0.000	tNET	FF	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.881	1.271	tNET	RR	1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0/CLK
1.904	0.022	tHld		1	R54C64[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.271, 100.000%
Arrival Data Path Delay	cell: 0.223, 62.785%; route: 0.005, 1.519%; tC2Q: 0.127, 35.696%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.271, 100.000%

Path13

Path Summary:

Slack	0.333
Data Arrival Time	2.237
Data Required Time	1.904
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_4_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/div_o_4_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.881	1.271	tNET	RR	1	R54C64[1][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_4_s0/CLK
2.008	0.127	tC2Q	RF	2	R54C64[1][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_4_s0/Q
2.014	0.005	tNET	FF	2	R54C64[1][B]	sscpll0/u_gwfpll/u_triangle_codegen/n70_s/I0
2.237	0.223	tINS	FF	1	R54C64[1][B]	sscpll0/u_gwfpll/u_triangle_codegen/n70_s/SUM
2.237	0.000	tNET	FF	1	R54C64[1][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.881	1.271	tNET	RR	1	R54C64[1][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_4_s0/CLK
1.904	0.022	tHld		1	R54C64[1][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.271, 100.000%
Arrival Data Path Delay	cell: 0.223, 62.785%; route: 0.005, 1.519%; tC2Q: 0.127, 35.696%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.271, 100.000%

Path14

Path Summary:

Slack	0.333
Data Arrival Time	2.233
Data Required Time	1.900
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_8_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/div_o_8_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.878	1.267	tNET	RR	1	R54C65[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_8_s0/CLK
2.005	0.127	tC2Q	RF	2	R54C65[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_8_s0/Q
2.010	0.005	tNET	FF	2	R54C65[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/n66_s/I0
2.233	0.223	tINS	FF	1	R54C65[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/n66_s/SUM
2.233	0.000	tNET	FF	1	R54C65[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.878	1.267	tNET	RR	1	R54C65[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_8_s0/CLK
1.900	0.022	tHld		1	R54C65[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.267, 100.000%
Arrival Data Path Delay	cell: 0.223, 62.785%; route: 0.005, 1.519%; tC2Q: 0.127, 35.696%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.267, 100.000%

Path15

Path Summary:

Slack	0.333
Data Arrival Time	2.233
Data Required Time	1.900
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_10_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/div_o_10_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.878	1.267	tNET	RR	1	R54C65[1][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_10_s0/CLK
2.005	0.127	tC2Q	RF	2	R54C65[1][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_10_s0/Q
2.010	0.005	tNET	FF	2	R54C65[1][B]	sscpll0/u_gwfpll/u_triangle_codegen/n64_s/I0
2.233	0.223	tINS	FF	1	R54C65[1][B]	sscpll0/u_gwfpll/u_triangle_codegen/n64_s/SUM
2.233	0.000	tNET	FF	1	R54C65[1][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.878	1.267	tNET	RR	1	R54C65[1][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_10_s0/CLK
1.900	0.022	tHld		1	R54C65[1][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.267, 100.000%
Arrival Data Path Delay	cell: 0.223, 62.785%; route: 0.005, 1.519%; tC2Q: 0.127, 35.696%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.267, 100.000%

Path16

Path Summary:

Slack	0.335
Data Arrival Time	2.234
Data Required Time	1.899
From	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_6_s0
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/Waitlock_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.880	1.272	tNET	RR	1	R54C104[2][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_6_s0/CLK
2.010	0.130	tC2Q	RR	2	R54C104[2][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_6_s0/Q
2.096	0.086	tNET	RR	1	R54C103[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/n541_s0/I1
2.234	0.138	tINS	RF	1	R54C103[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/n541_s0/F
2.234	0.000	tNET	FF	1	R54C103[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/Waitlock_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.877	1.269	tNET	RR	1	R54C103[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/Waitlock_s0/CLK
1.899	0.022	tHld		1	R54C103[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/Waitlock_s0

Path Statistics:

Clock Skew	-0.004
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.608, 32.332%; route: 1.272, 67.668%
Arrival Data Path Delay	cell: 0.138, 38.931%; route: 0.086, 24.427%; tC2Q: 0.130, 36.641%
Required Clock Path Delay	cell: 0.608, 32.394%; route: 1.269, 67.606%

Path17

Path Summary:

Slack	0.339
Data Arrival Time	2.242
Data Required Time	1.903
From	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_0_s0
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_0_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.880	1.272	tNET	RR	1	R54C118[2][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_0_s0/CLK
2.007	0.127	tC2Q	RF	3	R54C118[2][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_0_s0/Q
2.013	0.005	tNET	FF	1	R54C118[2][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/n562_6_s0/I0
2.242	0.229	tINS	FF	1	R54C118[2][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/n562_6_s0/F
2.242	0.000	tNET	FF	1	R54C118[2][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.880	1.272	tNET	RR	1	R54C118[2][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_0_s0/CLK
1.903	0.022	tHld		1	R54C118[2][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.608, 32.332%; route: 1.272, 67.668%
Arrival Data Path Delay	cell: 0.229, 63.433%; route: 0.005, 1.493%; tC2Q: 0.127, 35.075%
Required Clock Path Delay	cell: 0.608, 32.332%; route: 1.272, 67.668%

Path18

Path Summary:

Slack	0.339
Data Arrival Time	2.239
Data Required Time	1.900
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_12_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/div_o_12_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.878	1.267	tNET	RR	1	R54C65[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_12_s0/CLK
2.005	0.127	tC2Q	RF	2	R54C65[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_12_s0/Q
2.010	0.005	tNET	FF	2	R54C65[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/n62_s0/I0
2.239	0.229	tINS	FF	1	R54C65[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/n62_s0/SUM
2.239	0.000	tNET	FF	1	R54C65[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.878	1.267	tNET	RR	1	R54C65[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_12_s0/CLK
1.900	0.022	tHld		1	R54C65[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.267, 100.000%
Arrival Data Path Delay	cell: 0.229, 63.433%; route: 0.005, 1.493%; tC2Q: 0.127, 35.075%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.267, 100.000%

Path19

Path Summary:

Slack	0.339
Data Arrival Time	2.243
Data Required Time	1.904
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_18_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/div_o_18_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.881	1.271	tNET	RR	1	R54C66[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_18_s0/CLK
2.008	0.127	tC2Q	RF	2	R54C66[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_18_s0/Q
2.014	0.005	tNET	FF	2	R54C66[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/n56_s0/I0
2.243	0.229	tINS	FF	1	R54C66[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/n56_s0/SUM
2.243	0.000	tNET	FF	1	R54C66[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.881	1.271	tNET	RR	1	R54C66[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_18_s0/CLK
1.904	0.022	tHld		1	R54C66[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_18_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.271, 100.000%
Arrival Data Path Delay	cell: 0.229, 63.433%; route: 0.005, 1.493%; tC2Q: 0.127, 35.075%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.271, 100.000%

Path20

Path Summary:

Slack	0.339
Data Arrival Time	2.247
Data Required Time	1.907
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_24_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/div_o_24_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.885	1.274	tNET	RR	1	R54C67[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_24_s0/CLK
2.012	0.127	tC2Q	RF	2	R54C67[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_24_s0/Q
2.017	0.005	tNET	FF	2	R54C67[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/n50_s0/I0
2.247	0.229	tINS	FF	1	R54C67[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/n50_s0/SUM
2.247	0.000	tNET	FF	1	R54C67[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_24_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.885	1.274	tNET	RR	1	R54C67[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_24_s0/CLK
1.907	0.022	tHld		1	R54C67[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_24_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.274, 100.000%
Arrival Data Path Delay	cell: 0.229, 63.433%; route: 0.005, 1.493%; tC2Q: 0.127, 35.075%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.274, 100.000%

Path21

Path Summary:

Slack	0.339
Data Arrival Time	2.243
Data Required Time	1.904
From	sscpll0/u_gwfpll/u_triangle_codegen/div_o_30_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/div_o_30_s0
Launch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.881	1.271	tNET	RR	1	R54C68[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_30_s0/CLK
2.008	0.127	tC2Q	RF	2	R54C68[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_30_s0/Q
2.014	0.005	tNET	FF	2	R54C68[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/n44_s0/I0
2.243	0.229	tINS	FF	1	R54C68[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/n44_s0/SUM
2.243	0.000	tNET	FF	1	R54C68[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_30_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.881	1.271	tNET	RR	1	R54C68[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_30_s0/CLK
1.904	0.022	tHld		1	R54C68[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_30_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.271, 100.000%
Arrival Data Path Delay	cell: 0.229, 63.433%; route: 0.005, 1.493%; tC2Q: 0.127, 35.075%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.271, 100.000%

Path22

Path Summary:

Slack	0.355
Data Arrival Time	2.247
Data Required Time	1.892
From	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_3_s0
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_3_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.880	1.272	tNET	RR	1	R54C104[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_3_s0/CLK
2.007	0.127	tC2Q	RF	2	R54C104[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_3_s0/Q
2.013	0.005	tNET	FF	2	R54C104[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/n559_s/I1
2.247	0.234	tINS	FR	1	R54C104[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/n559_s/SUM
2.247	0.000	tNET	RR	1	R54C104[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.880	1.272	tNET	RR	1	R54C104[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_3_s0/CLK
1.892	0.012	tHld		1	R54C104[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.608, 32.332%; route: 1.272, 67.668%
Arrival Data Path Delay	cell: 0.234, 63.882%; route: 0.005, 1.474%; tC2Q: 0.127, 34.644%
Required Clock Path Delay	cell: 0.608, 32.332%; route: 1.272, 67.668%

Path23

Path Summary:

Slack	0.355
Data Arrival Time	2.250
Data Required Time	1.896
From	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_7_s0
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_7_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.884	1.276	tNET	RR	1	R54C105[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_7_s0/CLK
2.011	0.127	tC2Q	RF	2	R54C105[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_7_s0/Q
2.016	0.005	tNET	FF	2	R54C105[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/n555_s/I1
2.250	0.234	tINS	FR	1	R54C105[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/n555_s/SUM
2.250	0.000	tNET	RR	1	R54C105[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.884	1.276	tNET	RR	1	R54C105[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_7_s0/CLK
1.896	0.012	tHld		1	R54C105[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.608, 32.270%; route: 1.276, 67.730%
Arrival Data Path Delay	cell: 0.234, 63.882%; route: 0.005, 1.474%; tC2Q: 0.127, 34.644%
Required Clock Path Delay	cell: 0.608, 32.270%; route: 1.276, 67.730%

Path24

Path Summary:

Slack	0.355
Data Arrival Time	2.250
Data Required Time	1.896
From	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_9_s0
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_9_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.884	1.276	tNET	RR	1	R54C105[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_9_s0/CLK
2.011	0.127	tC2Q	RF	2	R54C105[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_9_s0/Q
2.016	0.005	tNET	FF	2	R54C105[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/n553_s/I1
2.250	0.234	tINS	FR	1	R54C105[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/n553_s/SUM
2.250	0.000	tNET	RR	1	R54C105[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.884	1.276	tNET	RR	1	R54C105[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_9_s0/CLK
1.896	0.012	tHld		1	R54C105[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_9_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.608, 32.270%; route: 1.276, 67.730%
Arrival Data Path Delay	cell: 0.234, 63.882%; route: 0.005, 1.474%; tC2Q: 0.127, 34.644%
Required Clock Path Delay	cell: 0.608, 32.270%; route: 1.276, 67.730%

Path25

Path Summary:

Slack	0.355
Data Arrival Time	2.247
Data Required Time	1.892
From	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_13_s0
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_13_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.880	1.272	tNET	RR	1	R54C106[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_13_s0/CLK
2.007	0.127	tC2Q	RF	2	R54C106[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_13_s0/Q
2.013	0.005	tNET	FF	2	R54C106[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/n549_s/I1
2.247	0.234	tINS	FR	1	R54C106[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/n549_s/SUM
2.247	0.000	tNET	RR	1	R54C106[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.880	1.272	tNET	RR	1	R54C106[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_13_s0/CLK
1.892	0.012	tHld		1	R54C106[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/waitcnt_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.608, 32.332%; route: 1.272, 67.668%
Arrival Data Path Delay	cell: 0.234, 63.882%; route: 0.005, 1.474%; tC2Q: 0.127, 34.644%
Required Clock Path Delay	cell: 0.608, 32.332%; route: 1.272, 67.668%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	16.413
Data Arrival Time	7.186
Data Required Time	23.599
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/div_o_28_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.186	2.917	tNET	FF	1	R54C68[1][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_28_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.946	3.330	tNET	RR	1	R54C68[1][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_28_s0/CLK
23.911	-0.035	tUnc
23.599	-0.313	tSu		1	R54C68[1][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_28_s0

Path Statistics:

Clock Skew	0.008
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.917, 89.816%; tC2Q: 0.331, 10.184%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%

Path2

Path Summary:

Slack	16.413
Data Arrival Time	7.186
Data Required Time	23.599
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/o_dir_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.186	2.917	tNET	FF	1	R54C68[3][A]	sscpll0/u_gwfpll/u_triangle_codegen/o_dir_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.946	3.330	tNET	RR	1	R54C68[3][A]	sscpll0/u_gwfpll/u_triangle_codegen/o_dir_s0/CLK
23.911	-0.035	tUnc
23.599	-0.313	tSu		1	R54C68[3][A]	sscpll0/u_gwfpll/u_triangle_codegen/o_dir_s0

Path Statistics:

Clock Skew	0.008
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.917, 89.816%; tC2Q: 0.331, 10.184%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%

Path3

Path Summary:

Slack	16.413
Data Arrival Time	7.186
Data Required Time	23.599
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/div_o_25_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.186	2.917	tNET	FF	1	R54C68[0][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_25_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.946	3.330	tNET	RR	1	R54C68[0][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_25_s0/CLK
23.911	-0.035	tUnc
23.599	-0.313	tSu		1	R54C68[0][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_25_s0

Path Statistics:

Clock Skew	0.008
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.917, 89.816%; tC2Q: 0.331, 10.184%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%

Path4

Path Summary:

Slack	16.413
Data Arrival Time	7.186
Data Required Time	23.599
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/div_o_26_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.186	2.917	tNET	FF	1	R54C68[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_26_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.946	3.330	tNET	RR	1	R54C68[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_26_s0/CLK
23.911	-0.035	tUnc
23.599	-0.313	tSu		1	R54C68[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_26_s0

Path Statistics:

Clock Skew	0.008
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.917, 89.816%; tC2Q: 0.331, 10.184%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%

Path5

Path Summary:

Slack	16.413
Data Arrival Time	7.186
Data Required Time	23.599
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/div_o_27_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.186	2.917	tNET	FF	1	R54C68[1][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_27_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.946	3.330	tNET	RR	1	R54C68[1][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_27_s0/CLK
23.911	-0.035	tUnc
23.599	-0.313	tSu		1	R54C68[1][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_27_s0

Path Statistics:

Clock Skew	0.008
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.917, 89.816%; tC2Q: 0.331, 10.184%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%

Path6

Path Summary:

Slack	16.413
Data Arrival Time	7.186
Data Required Time	23.599
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/div_o_29_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.186	2.917	tNET	FF	1	R54C68[2][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_29_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.946	3.330	tNET	RR	1	R54C68[2][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_29_s0/CLK
23.911	-0.035	tUnc
23.599	-0.313	tSu		1	R54C68[2][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_29_s0

Path Statistics:

Clock Skew	0.008
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.917, 89.816%; tC2Q: 0.331, 10.184%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%

Path7

Path Summary:

Slack	16.413
Data Arrival Time	7.186
Data Required Time	23.599
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/div_o_30_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.186	2.917	tNET	FF	1	R54C68[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_30_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.946	3.330	tNET	RR	1	R54C68[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_30_s0/CLK
23.911	-0.035	tUnc
23.599	-0.313	tSu		1	R54C68[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_30_s0

Path Statistics:

Clock Skew	0.008
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.917, 89.816%; tC2Q: 0.331, 10.184%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%

Path8

Path Summary:

Slack	16.421
Data Arrival Time	7.186
Data Required Time	23.607
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/div_o_19_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.186	2.917	tNET	FF	1	R54C67[0][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_19_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.955	3.338	tNET	RR	1	R54C67[0][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_19_s0/CLK
23.920	-0.035	tUnc
23.607	-0.313	tSu		1	R54C67[0][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_19_s0

Path Statistics:

Clock Skew	0.017
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.917, 89.816%; tC2Q: 0.331, 10.184%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.338, 100.000%

Path9

Path Summary:

Slack	16.421
Data Arrival Time	7.186
Data Required Time	23.607
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/div_o_20_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.186	2.917	tNET	FF	1	R54C67[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_20_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.955	3.338	tNET	RR	1	R54C67[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_20_s0/CLK
23.920	-0.035	tUnc
23.607	-0.313	tSu		1	R54C67[0][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_20_s0

Path Statistics:

Clock Skew	0.017
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.917, 89.816%; tC2Q: 0.331, 10.184%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.338, 100.000%

Path10

Path Summary:

Slack	16.421
Data Arrival Time	7.186
Data Required Time	23.607
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/div_o_21_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.186	2.917	tNET	FF	1	R54C67[1][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_21_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.955	3.338	tNET	RR	1	R54C67[1][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_21_s0/CLK
23.920	-0.035	tUnc
23.607	-0.313	tSu		1	R54C67[1][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_21_s0

Path Statistics:

Clock Skew	0.017
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.917, 89.816%; tC2Q: 0.331, 10.184%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.338, 100.000%

Path11

Path Summary:

Slack	16.421
Data Arrival Time	7.186
Data Required Time	23.607
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/div_o_22_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.186	2.917	tNET	FF	1	R54C67[1][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_22_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.955	3.338	tNET	RR	1	R54C67[1][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_22_s0/CLK
23.920	-0.035	tUnc
23.607	-0.313	tSu		1	R54C67[1][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_22_s0

Path Statistics:

Clock Skew	0.017
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.917, 89.816%; tC2Q: 0.331, 10.184%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.338, 100.000%

Path12

Path Summary:

Slack	16.421
Data Arrival Time	7.186
Data Required Time	23.607
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/div_o_23_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.186	2.917	tNET	FF	1	R54C67[2][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_23_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.955	3.338	tNET	RR	1	R54C67[2][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_23_s0/CLK
23.920	-0.035	tUnc
23.607	-0.313	tSu		1	R54C67[2][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_23_s0

Path Statistics:

Clock Skew	0.017
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.917, 89.816%; tC2Q: 0.331, 10.184%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.338, 100.000%

Path13

Path Summary:

Slack	16.421
Data Arrival Time	7.186
Data Required Time	23.607
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/div_o_24_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.186	2.917	tNET	FF	1	R54C67[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_24_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.955	3.338	tNET	RR	1	R54C67[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_24_s0/CLK
23.920	-0.035	tUnc
23.607	-0.313	tSu		1	R54C67[2][B]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_24_s0

Path Statistics:

Clock Skew	0.017
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.917, 89.816%; tC2Q: 0.331, 10.184%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.338, 100.000%

Path14

Path Summary:

Slack	16.456
Data Arrival Time	7.097
Data Required Time	23.553
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_13_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.097	2.828	tNET	FF	1	R53C114[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_13_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.901	3.284	tNET	RR	1	R53C114[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_13_s0/CLK
23.866	-0.035	tUnc
23.553	-0.313	tSu		1	R53C114[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_13_s0

Path Statistics:

Clock Skew	-0.037
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.828, 89.530%; tC2Q: 0.331, 10.470%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.284, 100.000%

Path15

Path Summary:

Slack	16.456
Data Arrival Time	7.097
Data Required Time	23.553
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_14_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.097	2.828	tNET	FF	1	R53C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_14_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.901	3.284	tNET	RR	1	R53C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_14_s0/CLK
23.866	-0.035	tUnc
23.553	-0.313	tSu		1	R53C114[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_14_s0

Path Statistics:

Clock Skew	-0.037
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.828, 89.530%; tC2Q: 0.331, 10.470%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.284, 100.000%

Path16

Path Summary:

Slack	16.456
Data Arrival Time	7.097
Data Required Time	23.553
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_15_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.097	2.828	tNET	FF	1	R53C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_15_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.901	3.284	tNET	RR	1	R53C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_15_s0/CLK
23.866	-0.035	tUnc
23.553	-0.313	tSu		1	R53C114[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_15_s0

Path Statistics:

Clock Skew	-0.037
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.828, 89.530%; tC2Q: 0.331, 10.470%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.284, 100.000%

Path17

Path Summary:

Slack	16.464
Data Arrival Time	7.081
Data Required Time	23.545
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_7_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.081	2.812	tNET	FF	1	R53C113[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.892	3.276	tNET	RR	1	R53C113[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_7_s0/CLK
23.858	-0.035	tUnc
23.545	-0.313	tSu		1	R53C113[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_7_s0

Path Statistics:

Clock Skew	-0.046
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.812, 89.476%; tC2Q: 0.331, 10.524%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.276, 100.000%

Path18

Path Summary:

Slack	16.464
Data Arrival Time	7.081
Data Required Time	23.545
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_8_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.081	2.812	tNET	FF	1	R53C113[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.892	3.276	tNET	RR	1	R53C113[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_8_s0/CLK
23.858	-0.035	tUnc
23.545	-0.313	tSu		1	R53C113[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_8_s0

Path Statistics:

Clock Skew	-0.046
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.812, 89.476%; tC2Q: 0.331, 10.524%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.276, 100.000%

Path19

Path Summary:

Slack	16.467
Data Arrival Time	7.096
Data Required Time	23.563
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_18_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.096	2.828	tNET	FF	1	R54C115[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_18_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.911	3.295	tNET	RR	1	R54C115[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_18_s0/CLK
23.876	-0.035	tUnc
23.563	-0.313	tSu		1	R54C115[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_18_s0

Path Statistics:

Clock Skew	-0.027
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.828, 89.528%; tC2Q: 0.331, 10.472%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.295, 100.000%

Path20

Path Summary:

Slack	16.467
Data Arrival Time	7.096
Data Required Time	23.563
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_19_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.096	2.828	tNET	FF	1	R54C115[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_19_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.911	3.295	tNET	RR	1	R54C115[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_19_s0/CLK
23.876	-0.035	tUnc
23.563	-0.313	tSu		1	R54C115[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_19_s0

Path Statistics:

Clock Skew	-0.027
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.828, 89.528%; tC2Q: 0.331, 10.472%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.295, 100.000%

Path21

Path Summary:

Slack	16.467
Data Arrival Time	7.096
Data Required Time	23.563
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_20_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.096	2.828	tNET	FF	1	R54C115[3][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_20_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.911	3.295	tNET	RR	1	R54C115[3][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_20_s0/CLK
23.876	-0.035	tUnc
23.563	-0.313	tSu		1	R54C115[3][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_20_s0

Path Statistics:

Clock Skew	-0.027
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.828, 89.528%; tC2Q: 0.331, 10.472%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.295, 100.000%

Path22

Path Summary:

Slack	16.467
Data Arrival Time	7.096
Data Required Time	23.563
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_19_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.096	2.828	tNET	FF	1	R54C115[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_19_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.911	3.295	tNET	RR	1	R54C115[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_19_s0/CLK
23.876	-0.035	tUnc
23.563	-0.313	tSu		1	R54C115[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_19_s0

Path Statistics:

Clock Skew	-0.027
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.828, 89.528%; tC2Q: 0.331, 10.472%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.295, 100.000%

Path23

Path Summary:

Slack	16.467
Data Arrival Time	7.096
Data Required Time	23.563
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_20_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.096	2.828	tNET	FF	1	R54C115[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_20_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.911	3.295	tNET	RR	1	R54C115[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_20_s0/CLK
23.876	-0.035	tUnc
23.563	-0.313	tSu		1	R54C115[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_20_s0

Path Statistics:

Clock Skew	-0.027
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.828, 89.528%; tC2Q: 0.331, 10.472%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.295, 100.000%

Path24

Path Summary:

Slack	16.467
Data Arrival Time	7.096
Data Required Time	23.563
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_21_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
7.096	2.828	tNET	FF	1	R54C115[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_21_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.911	3.295	tNET	RR	1	R54C115[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_21_s0/CLK
23.876	-0.035	tUnc
23.563	-0.313	tSu		1	R54C115[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_21_s0

Path Statistics:

Clock Skew	-0.027
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.828, 89.528%; tC2Q: 0.331, 10.472%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.295, 100.000%

Path25

Path Summary:

Slack	16.640
Data Arrival Time	6.959
Data Required Time	23.599
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/div_o_13_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.614	0.614	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
3.938	3.324	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
4.269	0.331	tC2Q	RF	79	R54C87[0][B]	rstn_d1_s0/Q
6.959	2.690	tNET	FF	1	R54C66[0][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_13_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.617	0.617	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
23.946	3.330	tNET	RR	1	R54C66[0][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_13_s0/CLK
23.911	-0.035	tUnc
23.599	-0.313	tSu		1	R54C66[0][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_13_s0

Path Statistics:

Clock Skew	0.008
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.614, 15.598%; route: 3.324, 84.402%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.690, 89.050%; tC2Q: 0.331, 10.950%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.330, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.320
Data Arrival Time	2.156
Data Required Time	1.836
From	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_1_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/CLK
2.007	0.130	tC2Q	RR	20	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q
2.156	0.148	tNET	RR	1	R54C93[2][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.884	1.276	tNET	RR	1	R54C93[2][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_1_s0/CLK
1.836	-0.048	tHld		1	R54C93[2][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_1_s0

Path Statistics:

Clock Skew	0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.148, 53.398%; tC2Q: 0.130, 46.602%
Required Clock Path Delay	cell: 0.608, 32.270%; route: 1.276, 67.730%

Path2

Path Summary:

Slack	0.323
Data Arrival Time	2.156
Data Required Time	1.833
From	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_0_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/CLK
2.007	0.130	tC2Q	RR	20	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q
2.156	0.148	tNET	RR	1	R54C94[3][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.880	1.272	tNET	RR	1	R54C94[3][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_0_s0/CLK
1.833	-0.048	tHld		1	R54C94[3][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_0_s0

Path Statistics:

Clock Skew	0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.148, 53.398%; tC2Q: 0.130, 46.602%
Required Clock Path Delay	cell: 0.608, 32.332%; route: 1.272, 67.668%

Path3

Path Summary:

Slack	0.325
Data Arrival Time	2.158
Data Required Time	1.833
From	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/laststep_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/CLK
2.007	0.130	tC2Q	RR	20	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q
2.158	0.150	tNET	RR	1	R54C96[3][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/laststep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.880	1.272	tNET	RR	1	R54C96[3][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/laststep_s0/CLK
1.833	-0.048	tHld		1	R54C96[3][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/laststep_s0

Path Statistics:

Clock Skew	0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.150, 53.698%; tC2Q: 0.130, 46.302%
Required Clock Path Delay	cell: 0.608, 32.332%; route: 1.272, 67.668%

Path4

Path Summary:

Slack	0.404
Data Arrival Time	2.233
Data Required Time	1.829
From	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_2_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/CLK
2.007	0.130	tC2Q	RR	20	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q
2.233	0.226	tNET	RR	1	R54C95[3][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.877	1.269	tNET	RR	1	R54C95[3][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_2_s0/CLK
1.829	-0.048	tHld		1	R54C95[3][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/state_2_s0

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.226, 63.544%; tC2Q: 0.130, 36.456%
Required Clock Path Delay	cell: 0.608, 32.394%; route: 1.269, 67.606%

Path5

Path Summary:

Slack	0.507
Data Arrival Time	2.377
Data Required Time	1.870
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/ssc_en_o_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
2.007	0.130	tC2Q	RR	79	R54C87[0][B]	rstn_d1_s0/Q
2.377	0.370	tNET	RR	1	R53C99[0][A]	sscpll0/u_gwfpll/u_triangle_codegen/ssc_en_o_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.883	1.272	tNET	RR	1	R53C99[0][A]	sscpll0/u_gwfpll/u_triangle_codegen/ssc_en_o_s0/CLK
1.918	0.035	tUnc
1.870	-0.048	tHld		1	R53C99[0][A]	sscpll0/u_gwfpll/u_triangle_codegen/ssc_en_o_s0

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.370, 74.054%; tC2Q: 0.130, 25.946%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.272, 100.000%

Path6

Path Summary:

Slack	0.524
Data Arrival Time	2.354
Data Required Time	1.830
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
2.007	0.130	tC2Q	RR	79	R54C87[0][B]	rstn_d1_s0/Q
2.354	0.346	tNET	RR	1	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/CLK
1.830	-0.048	tHld		1	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.346, 72.779%; tC2Q: 0.130, 27.221%
Required Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%

Path7

Path Summary:

Slack	0.524
Data Arrival Time	2.354
Data Required Time	1.830
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_0_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
2.007	0.130	tC2Q	RR	79	R54C87[0][B]	rstn_d1_s0/Q
2.354	0.346	tNET	RR	1	R54C87[1][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[1][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_0_s0/CLK
1.830	-0.048	tHld		1	R54C87[1][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.346, 72.779%; tC2Q: 0.130, 27.221%
Required Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%

Path8

Path Summary:

Slack	0.535
Data Arrival Time	2.403
Data Required Time	1.869
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_triangle_codegen/div_o_0_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
2.007	0.130	tC2Q	RR	79	R54C87[0][B]	rstn_d1_s0/Q
2.403	0.396	tNET	RR	1	R54C78[0][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.881	1.271	tNET	RR	1	R54C78[0][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_0_s0/CLK
1.916	0.035	tUnc
1.869	-0.048	tHld		1	R54C78[0][A]	sscpll0/u_gwfpll/u_triangle_codegen/div_o_0_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.396, 75.342%; tC2Q: 0.130, 24.658%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.271, 100.000%

Path9

Path Summary:

Slack	0.560
Data Arrival Time	2.389
Data Required Time	1.829
From	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_0_s1
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/CLK
2.007	0.130	tC2Q	RR	20	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q
2.389	0.382	tNET	RR	1	R54C107[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.877	1.269	tNET	RR	1	R54C107[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_0_s1/CLK
1.829	-0.048	tHld		1	R54C107[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_0_s1

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 74.648%; tC2Q: 0.130, 25.352%
Required Clock Path Delay	cell: 0.608, 32.394%; route: 1.269, 67.606%

Path10

Path Summary:

Slack	0.560
Data Arrival Time	2.389
Data Required Time	1.829
From	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_2_s1
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/CLK
2.007	0.130	tC2Q	RR	20	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q
2.389	0.382	tNET	RR	1	R54C107[0][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.877	1.269	tNET	RR	1	R54C107[0][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_2_s1/CLK
1.829	-0.048	tHld		1	R54C107[0][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_2_s1

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 74.648%; tC2Q: 0.130, 25.352%
Required Clock Path Delay	cell: 0.608, 32.394%; route: 1.269, 67.606%

Path11

Path Summary:

Slack	0.609
Data Arrival Time	2.473
Data Required Time	1.864
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_0_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
2.007	0.130	tC2Q	RR	79	R54C87[0][B]	rstn_d1_s0/Q
2.473	0.465	tNET	RR	1	R54C101[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.877	1.266	tNET	RR	1	R54C101[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_0_s0/CLK
1.912	0.035	tUnc
1.864	-0.048	tHld		1	R54C101[0][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_0_s0

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.465, 78.215%; tC2Q: 0.130, 21.785%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.266, 100.000%

Path12

Path Summary:

Slack	0.609
Data Arrival Time	2.473
Data Required Time	1.864
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
2.007	0.130	tC2Q	RR	79	R54C87[0][B]	rstn_d1_s0/Q
2.473	0.465	tNET	RR	1	R54C101[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.877	1.266	tNET	RR	1	R54C101[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0/CLK
1.912	0.035	tUnc
1.864	-0.048	tHld		1	R54C101[0][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.465, 78.215%; tC2Q: 0.130, 21.785%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.266, 100.000%

Path13

Path Summary:

Slack	0.639
Data Arrival Time	2.475
Data Required Time	1.836
From	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_12_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/CLK
2.007	0.130	tC2Q	RR	20	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q
2.475	0.468	tNET	RR	1	R54C101[2][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_12_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.884	1.276	tNET	RR	1	R54C101[2][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_12_s0/CLK
1.836	-0.048	tHld		1	R54C101[2][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_12_s0

Path Statistics:

Clock Skew	0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.468, 78.313%; tC2Q: 0.130, 21.687%
Required Clock Path Delay	cell: 0.608, 32.270%; route: 1.276, 67.730%

Path14

Path Summary:

Slack	0.707
Data Arrival Time	2.540
Data Required Time	1.833
From	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_1_s1
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/CLK
2.007	0.130	tC2Q	RR	20	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q
2.540	0.533	tNET	RR	1	R54C108[1][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.880	1.272	tNET	RR	1	R54C108[1][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_1_s1/CLK
1.833	-0.048	tHld		1	R54C108[1][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_1_s1

Path Statistics:

Clock Skew	0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.533, 80.435%; tC2Q: 0.130, 19.565%
Required Clock Path Delay	cell: 0.608, 32.332%; route: 1.272, 67.668%

Path15

Path Summary:

Slack	0.707
Data Arrival Time	2.540
Data Required Time	1.833
From	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_3_s1
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/CLK
2.007	0.130	tC2Q	RR	20	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q
2.540	0.533	tNET	RR	1	R54C108[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.880	1.272	tNET	RR	1	R54C108[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_3_s1/CLK
1.833	-0.048	tHld		1	R54C108[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr_3_s1

Path Statistics:

Clock Skew	0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.533, 80.435%; tC2Q: 0.130, 19.565%
Required Clock Path Delay	cell: 0.608, 32.332%; route: 1.272, 67.668%

Path16

Path Summary:

Slack	0.737
Data Arrival Time	2.573
Data Required Time	1.836
From	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_9_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/CLK
2.007	0.130	tC2Q	RR	20	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q
2.573	0.566	tNET	RR	1	R54C109[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_9_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.884	1.276	tNET	RR	1	R54C109[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_9_s0/CLK
1.836	-0.048	tHld		1	R54C109[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_9_s0

Path Statistics:

Clock Skew	0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.566, 81.371%; tC2Q: 0.130, 18.629%
Required Clock Path Delay	cell: 0.608, 32.270%; route: 1.276, 67.730%

Path17

Path Summary:

Slack	0.737
Data Arrival Time	2.573
Data Required Time	1.836
From	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_10_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/CLK
2.007	0.130	tC2Q	RR	20	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q
2.573	0.566	tNET	RR	1	R54C109[0][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_10_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.884	1.276	tNET	RR	1	R54C109[0][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_10_s0/CLK
1.836	-0.048	tHld		1	R54C109[0][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_10_s0

Path Statistics:

Clock Skew	0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.566, 81.371%; tC2Q: 0.130, 18.629%
Required Clock Path Delay	cell: 0.608, 32.270%; route: 1.276, 67.730%

Path18

Path Summary:

Slack	0.741
Data Arrival Time	2.573
Data Required Time	1.833
From	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_0_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/CLK
2.007	0.130	tC2Q	RR	20	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q
2.573	0.566	tNET	RR	1	R54C110[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.880	1.272	tNET	RR	1	R54C110[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_0_s0/CLK
1.833	-0.048	tHld		1	R54C110[0][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_0_s0

Path Statistics:

Clock Skew	0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.566, 81.371%; tC2Q: 0.130, 18.629%
Required Clock Path Delay	cell: 0.608, 32.332%; route: 1.272, 67.668%

Path19

Path Summary:

Slack	0.741
Data Arrival Time	2.573
Data Required Time	1.833
From	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0
To	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_8_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/CLK
2.007	0.130	tC2Q	RR	20	R54C87[1][A]	sscpll0/u_gwfpll/u_pll0/u_pll_init/enable_r_1_s0/Q
2.573	0.566	tNET	RR	1	R54C110[0][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.880	1.272	tNET	RR	1	R54C110[0][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_8_s0/CLK
1.833	-0.048	tHld		1	R54C110[0][B]	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomDreg_8_s0

Path Statistics:

Clock Skew	0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.566, 81.371%; tC2Q: 0.130, 18.629%
Required Clock Path Delay	cell: 0.608, 32.332%; route: 1.272, 67.668%

Path20

Path Summary:

Slack	0.755
Data Arrival Time	2.623
Data Required Time	1.868
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_1_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
2.007	0.130	tC2Q	RR	79	R54C87[0][B]	rstn_d1_s0/Q
2.623	0.616	tNET	RR	1	R54C110[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.880	1.270	tNET	RR	1	R54C110[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_1_s0/CLK
1.915	0.035	tUnc
1.868	-0.048	tHld		1	R54C110[2][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_1_s0

Path Statistics:

Clock Skew	0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.616, 82.609%; tC2Q: 0.130, 17.391%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.270, 100.000%

Path21

Path Summary:

Slack	0.755
Data Arrival Time	2.623
Data Required Time	1.868
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_2_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
2.007	0.130	tC2Q	RR	79	R54C87[0][B]	rstn_d1_s0/Q
2.623	0.616	tNET	RR	1	R54C110[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.880	1.270	tNET	RR	1	R54C110[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_2_s0/CLK
1.915	0.035	tUnc
1.868	-0.048	tHld		1	R54C110[2][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_2_s0

Path Statistics:

Clock Skew	0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.616, 82.609%; tC2Q: 0.130, 17.391%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.270, 100.000%

Path22

Path Summary:

Slack	0.755
Data Arrival Time	2.623
Data Required Time	1.868
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_3_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
2.007	0.130	tC2Q	RR	79	R54C87[0][B]	rstn_d1_s0/Q
2.623	0.616	tNET	RR	1	R54C110[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.880	1.270	tNET	RR	1	R54C110[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_3_s0/CLK
1.915	0.035	tUnc
1.868	-0.048	tHld		1	R54C110[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_3_s0

Path Statistics:

Clock Skew	0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.616, 82.609%; tC2Q: 0.130, 17.391%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.270, 100.000%

Path23

Path Summary:

Slack	0.755
Data Arrival Time	2.623
Data Required Time	1.868
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_22_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
2.007	0.130	tC2Q	RR	79	R54C87[0][B]	rstn_d1_s0/Q
2.623	0.616	tNET	RR	1	R54C110[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_22_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.880	1.270	tNET	RR	1	R54C110[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_22_s0/CLK
1.915	0.035	tUnc
1.868	-0.048	tHld		1	R54C110[1][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_22_s0

Path Statistics:

Clock Skew	0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.616, 82.609%; tC2Q: 0.130, 17.391%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.270, 100.000%

Path24

Path Summary:

Slack	1.302
Data Arrival Time	3.174
Data Required Time	1.871
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_4_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
2.007	0.130	tC2Q	RR	79	R54C87[0][B]	rstn_d1_s0/Q
3.174	1.166	tNET	RR	1	R54C111[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.884	1.273	tNET	RR	1	R54C111[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_4_s0/CLK
1.919	0.035	tUnc
1.871	-0.048	tHld		1	R54C111[1][B]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_4_s0

Path Statistics:

Clock Skew	0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.166, 90.000%; tC2Q: 0.130, 10.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.273, 100.000%

Path25

Path Summary:

Slack	1.302
Data Arrival Time	3.174
Data Required Time	1.871
From	rstn_d1_s0
To	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_5_s0
Launch Clk	sys_clk:[R]
Latch Clk	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOR29[A]	sys_clk_ibuf/I
0.608	0.608	tINS	RR	45	IOR29[A]	sys_clk_ibuf/O
1.878	1.270	tNET	RR	1	R54C87[0][B]	rstn_d1_s0/CLK
2.007	0.130	tC2Q	RR	79	R54C87[0][B]	rstn_d1_s0/Q
3.174	1.166	tNET	RR	1	R54C111[3][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.611	0.611	tCL	RR	117	PLL_R[1]	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
1.884	1.273	tNET	RR	1	R54C111[3][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_5_s0/CLK
1.919	0.035	tUnc
1.871	-0.048	tHld		1	R54C111[3][A]	sscpll0/u_gwfpll/u_sdm2/mod_h_inst/in_reg_5_s0

Path Statistics:

Clock Skew	0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.608, 32.379%; route: 1.270, 67.621%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.166, 90.000%; tC2Q: 0.130, 10.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.273, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	7.948
Actual Width:	8.173
Required Width:	0.225
Type:	High Pulse Width
Clock:	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
Objects:	sscpll0/u_gwfpll/u_triangle_codegen/div_o_24_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.955	3.338	tNET	RR	sscpll0/u_gwfpll/u_triangle_codegen/div_o_24_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
10.611	0.611	tCL	FF	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
12.128	1.517	tNET	FF	sscpll0/u_gwfpll/u_triangle_codegen/div_o_24_s0/CLK

MPW2

MPW Summary:

Slack:	7.948
Actual Width:	8.173
Required Width:	0.225
Type:	High Pulse Width
Clock:	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
Objects:	sscpll0/u_gwfpll/u_triangle_codegen/div_o_23_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.955	3.338	tNET	RR	sscpll0/u_gwfpll/u_triangle_codegen/div_o_23_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
10.611	0.611	tCL	FF	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
12.128	1.517	tNET	FF	sscpll0/u_gwfpll/u_triangle_codegen/div_o_23_s0/CLK

MPW3

MPW Summary:

Slack:	7.948
Actual Width:	8.173
Required Width:	0.225
Type:	High Pulse Width
Clock:	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
Objects:	sscpll0/u_gwfpll/u_triangle_codegen/div_o_19_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.955	3.338	tNET	RR	sscpll0/u_gwfpll/u_triangle_codegen/div_o_19_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
10.611	0.611	tCL	FF	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
12.128	1.517	tNET	FF	sscpll0/u_gwfpll/u_triangle_codegen/div_o_19_s0/CLK

MPW4

MPW Summary:

Slack:	7.948
Actual Width:	8.173
Required Width:	0.225
Type:	High Pulse Width
Clock:	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
Objects:	sscpll0/u_gwfpll/u_triangle_codegen/div_o_22_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.955	3.338	tNET	RR	sscpll0/u_gwfpll/u_triangle_codegen/div_o_22_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
10.611	0.611	tCL	FF	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
12.128	1.517	tNET	FF	sscpll0/u_gwfpll/u_triangle_codegen/div_o_22_s0/CLK

MPW5

MPW Summary:

Slack:	7.948
Actual Width:	8.173
Required Width:	0.225
Type:	High Pulse Width
Clock:	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
Objects:	sscpll0/u_gwfpll/u_triangle_codegen/div_o_21_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.955	3.338	tNET	RR	sscpll0/u_gwfpll/u_triangle_codegen/div_o_21_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
10.611	0.611	tCL	FF	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
12.128	1.517	tNET	FF	sscpll0/u_gwfpll/u_triangle_codegen/div_o_21_s0/CLK

MPW6

MPW Summary:

Slack:	7.948
Actual Width:	8.173
Required Width:	0.225
Type:	High Pulse Width
Clock:	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
Objects:	sscpll0/u_gwfpll/u_triangle_codegen/div_o_20_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.955	3.338	tNET	RR	sscpll0/u_gwfpll/u_triangle_codegen/div_o_20_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
10.611	0.611	tCL	FF	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
12.128	1.517	tNET	FF	sscpll0/u_gwfpll/u_triangle_codegen/div_o_20_s0/CLK

MPW7

MPW Summary:

Slack:	7.948
Actual Width:	8.173
Required Width:	0.225
Type:	High Pulse Width
Clock:	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
Objects:	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_18_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.955	3.338	tNET	RR	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_18_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
10.611	0.611	tCL	FF	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
12.128	1.517	tNET	FF	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_18_s0/CLK

MPW8

MPW Summary:

Slack:	7.948
Actual Width:	8.173
Required Width:	0.225
Type:	High Pulse Width
Clock:	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
Objects:	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_17_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.955	3.338	tNET	RR	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_17_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
10.611	0.611	tCL	FF	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
12.128	1.517	tNET	FF	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_17_s0/CLK

MPW9

MPW Summary:

Slack:	7.948
Actual Width:	8.173
Required Width:	0.225
Type:	High Pulse Width
Clock:	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
Objects:	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_16_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.955	3.338	tNET	RR	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_16_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
10.611	0.611	tCL	FF	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
12.128	1.517	tNET	FF	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_16_s0/CLK

MPW10

MPW Summary:

Slack:	7.948
Actual Width:	8.173
Required Width:	0.225
Type:	High Pulse Width
Clock:	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
Objects:	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_15_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.617	0.617	tCL	RR	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
3.955	3.338	tNET	RR	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_15_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
10.611	0.611	tCL	FF	sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
12.128	1.517	tNET	FF	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/counter_15_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
117	sscpll0/u_gwfpll/clkfb	13.247	3.338
45	sys_clk_d	16.354	3.324
30	sscpll0/u_gwfpll/u_triangle_codegen/o_dir	16.649	0.993
28	sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/n34_116	16.178	1.179
17	sscpll0/u_gwfpll/u_pll0/u_pll_init/n564_4	17.253	0.688
15	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr[0]	17.553	0.561
14	sscpll0/u_gwfpll/u_pll0/u_pll_init/state[2]	16.870	0.911
14	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr[1]	17.297	0.826
13	sscpll0/u_gwfpll/u_pll0/u_pll_init/RomAddr[2]	17.429	0.873
12	sscpll0/u_gwfpll/u_pll0/u_pll_init/state[0]	16.820	1.047

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R54C97	38.89%
R54C99	37.50%
R54C95	36.11%
R54C107	34.72%
R54C94	33.33%
R54C96	33.33%
R54C109	31.94%
R54C98	31.94%
R54C106	30.56%
R54C112	29.17%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command