Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\IP_Release\SSCPLL\1.5\ref_design\Gowin_SSCPLL_RefDesign\project\src\sscpll\sscpll.v
E:\IP_Release\SSCPLL\1.5\ref_design\Gowin_SSCPLL_RefDesign\project\src\top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12.02 (64-bit)
Part Number GW5AST-LV138FPG676AC1/I0
Device GW5AST-138
Device Version B
Created Time Fri Mar 6 11:10:00 2026
Legal Announcement Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.226s, Peak memory usage = 236.438MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 236.438MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 236.438MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 236.438MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 236.438MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 236.438MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 236.438MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 236.438MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 236.438MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 236.438MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 236.438MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.138s, Peak memory usage = 259.680MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 259.680MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 259.680MB
Total Time and Memory Usage CPU time = 0h 0m 0.434s, Elapsed time = 0h 0m 0.445s, Peak memory usage = 259.680MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 2
I/O Buf 2
    IBUF 1
    OBUF 1
Register 161
    DFFRE 52
    DFFPE 1
    DFFCE 108
LUT 71
    LUT2 1
    LUT3 11
    LUT4 59
ALU 131
    ALU 131
INV 17
    INV 17
CLOCK 1
    PLL 1

Resource Utilization Summary

Resource Usage Utilization
Logic 219(88 LUT, 131 ALU) / 138240 <1%
Register 161 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 161 / 139140 <1%
BSRAM 0 / 340 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 sys_clk Base 20.000 50.000 0.000 10.000 sys_clk_ibuf/I
2 sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKOUT0.default_gen_clk Generated 10.000 100.000 0.000 5.000 sys_clk_ibuf/I sys_clk sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKOUT0
3 sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk Generated 20.000 50.000 0.000 10.000 sys_clk_ibuf/I sys_clk sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 sys_clk 50.000(MHz) 289.918(MHz) 4 TOP
2 sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk 50.000(MHz) 219.424(MHz) 8 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 15.443
Data Arrival Time 5.243
Data Required Time 20.685
From sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0
To sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_22_s0
Launch Clk sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk[R]
Latch Clk sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.371 0.371 tCL RR 117 sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
0.743 0.371 tNET RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0/CLK
1.087 0.344 tC2Q RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0/Q
1.458 0.371 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_0_s/I1
1.998 0.540 tINS RF 1 sscpll0/u_gwfpll/u_sdm2/error_0_s/COUT
1.998 0.000 tNET FF 2 sscpll0/u_gwfpll/u_sdm2/error_1_s/CIN
2.217 0.219 tINS FR 2 sscpll0/u_gwfpll/u_sdm2/error_1_s/SUM
2.589 0.371 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n98_s/I0
3.124 0.535 tINS RF 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n98_s/COUT
3.124 0.000 tNET FF 2 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n97_s/CIN
3.169 0.045 tINS FR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n97_s/COUT
3.169 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n96_s/CIN
3.214 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n96_s/COUT
3.214 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n95_s/CIN
3.259 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n95_s/COUT
3.259 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n94_s/CIN
3.304 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n94_s/COUT
3.304 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n93_s/CIN
3.349 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n93_s/COUT
3.349 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n92_s/CIN
3.394 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n92_s/COUT
3.394 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n91_s/CIN
3.439 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n91_s/COUT
3.439 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/CIN
3.484 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n90_s/COUT
3.484 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/CIN
3.529 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n89_s/COUT
3.529 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/CIN
3.574 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n88_s/COUT
3.574 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n87_s/CIN
3.619 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n87_s/COUT
3.619 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n86_s/CIN
3.664 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n86_s/COUT
3.664 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n85_s/CIN
3.709 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n85_s/COUT
3.709 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n84_s/CIN
3.754 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n84_s/COUT
3.754 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n83_s/CIN
3.799 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n83_s/COUT
3.799 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n82_s/CIN
3.844 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n82_s/COUT
3.844 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n81_s/CIN
3.889 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n81_s/COUT
3.889 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n80_s/CIN
3.934 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n80_s/COUT
3.934 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n79_s/CIN
3.979 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n79_s/COUT
4.350 0.371 tNET RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n78_9_3_s0/I0
4.871 0.521 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/n78_9_3_s0/F
5.243 0.371 tNET RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_22_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 20.000 active clock edge time
20.000 0.000 sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.371 0.371 tCL RR 117 sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
20.743 0.371 tNET RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_22_s0/CLK
20.685 -0.057 tSu 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_22_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.371, 100.000%
Arrival Data Path Delay: cell: 2.671, 59.350%; route: 1.485, 33.000%; tC2Q: 0.344, 7.650%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.371, 100.000%

Path 2

Path Summary:
Slack 15.710
Data Arrival Time 4.975
Data Required Time 20.685
From sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0
To sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_6_s0
Launch Clk sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk[R]
Latch Clk sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.371 0.371 tCL RR 117 sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
0.743 0.371 tNET RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0/CLK
1.087 0.344 tC2Q RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0/Q
1.458 0.371 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_0_s/I1
1.998 0.540 tINS RF 1 sscpll0/u_gwfpll/u_sdm2/error_0_s/COUT
1.998 0.000 tNET FF 2 sscpll0/u_gwfpll/u_sdm2/error_1_s/CIN
2.043 0.045 tINS FR 1 sscpll0/u_gwfpll/u_sdm2/error_1_s/COUT
2.043 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_2_s/CIN
2.088 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
2.088 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
2.133 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
2.133 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
2.178 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
2.178 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
2.223 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
2.223 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
2.268 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
2.268 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
2.313 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
2.313 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
2.358 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
2.358 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
2.403 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_9_s/COUT
2.403 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_10_s/CIN
2.448 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_10_s/COUT
2.448 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_11_s/CIN
2.493 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_11_s/COUT
2.493 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_12_s/CIN
2.538 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_12_s/COUT
2.538 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_13_s/CIN
2.583 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_13_s/COUT
2.583 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_14_s/CIN
2.628 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_14_s/COUT
2.628 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_15_s/CIN
2.673 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_15_s/COUT
2.673 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_16_s/CIN
2.718 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_16_s/COUT
2.718 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_17_s/CIN
2.763 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_17_s/COUT
2.763 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_18_s/CIN
2.808 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_18_s/COUT
2.808 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_19_s/CIN
2.853 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_19_s/COUT
2.853 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_20_s/CIN
2.898 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_20_s/COUT
2.898 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/out_0_s/CIN
2.943 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/out_0_s/COUT
2.943 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/out_1_s/CIN
2.988 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/out_1_s/COUT
2.988 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/out_2_s/CIN
3.033 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/out_2_s/COUT
3.033 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/out_3_s/CIN
3.078 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/out_3_s/COUT
3.078 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/out_4_s/CIN
3.297 0.219 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/out_4_s/SUM
3.669 0.371 tNET RR 2 sscpll0/u_gwfpll/u_mdiv_code_conv/n18_s/I0
4.204 0.535 tINS RF 1 sscpll0/u_gwfpll/u_mdiv_code_conv/n18_s/COUT
4.204 0.000 tNET FF 2 sscpll0/u_gwfpll/u_mdiv_code_conv/n17_s/CIN
4.249 0.045 tINS FR 1 sscpll0/u_gwfpll/u_mdiv_code_conv/n17_s/COUT
4.249 0.000 tNET RR 2 sscpll0/u_gwfpll/u_mdiv_code_conv/n16_s/CIN
4.294 0.045 tINS RR 1 sscpll0/u_gwfpll/u_mdiv_code_conv/n16_s/COUT
4.294 0.000 tNET RR 2 sscpll0/u_gwfpll/u_mdiv_code_conv/n15_s/CIN
4.339 0.045 tINS RR 1 sscpll0/u_gwfpll/u_mdiv_code_conv/n15_s/COUT
4.339 0.000 tNET RR 2 sscpll0/u_gwfpll/u_mdiv_code_conv/n14_s/CIN
4.384 0.045 tINS RR 1 sscpll0/u_gwfpll/u_mdiv_code_conv/n14_s/COUT
4.384 0.000 tNET RR 2 sscpll0/u_gwfpll/u_mdiv_code_conv/n13_s/CIN
4.604 0.219 tINS RR 1 sscpll0/u_gwfpll/u_mdiv_code_conv/n13_s/SUM
4.975 0.371 tNET RR 1 sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_6_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 20.000 active clock edge time
20.000 0.000 sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.371 0.371 tCL RR 117 sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
20.743 0.371 tNET RR 1 sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_6_s0/CLK
20.685 -0.057 tSu 1 sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_6_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.371, 100.000%
Arrival Data Path Delay: cell: 2.774, 65.550%; route: 1.114, 26.316%; tC2Q: 0.344, 8.134%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.371, 100.000%

Path 3

Path Summary:
Slack 15.755
Data Arrival Time 4.930
Data Required Time 20.685
From sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0
To sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_5_s0
Launch Clk sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk[R]
Latch Clk sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.371 0.371 tCL RR 117 sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
0.743 0.371 tNET RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0/CLK
1.087 0.344 tC2Q RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0/Q
1.458 0.371 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_0_s/I1
1.998 0.540 tINS RF 1 sscpll0/u_gwfpll/u_sdm2/error_0_s/COUT
1.998 0.000 tNET FF 2 sscpll0/u_gwfpll/u_sdm2/error_1_s/CIN
2.043 0.045 tINS FR 1 sscpll0/u_gwfpll/u_sdm2/error_1_s/COUT
2.043 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_2_s/CIN
2.088 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
2.088 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
2.133 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
2.133 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
2.178 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
2.178 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
2.223 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
2.223 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
2.268 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
2.268 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
2.313 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
2.313 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
2.358 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
2.358 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
2.403 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_9_s/COUT
2.403 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_10_s/CIN
2.448 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_10_s/COUT
2.448 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_11_s/CIN
2.493 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_11_s/COUT
2.493 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_12_s/CIN
2.538 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_12_s/COUT
2.538 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_13_s/CIN
2.583 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_13_s/COUT
2.583 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_14_s/CIN
2.628 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_14_s/COUT
2.628 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_15_s/CIN
2.673 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_15_s/COUT
2.673 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_16_s/CIN
2.718 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_16_s/COUT
2.718 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_17_s/CIN
2.763 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_17_s/COUT
2.763 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_18_s/CIN
2.808 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_18_s/COUT
2.808 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_19_s/CIN
2.853 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_19_s/COUT
2.853 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_20_s/CIN
2.898 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_20_s/COUT
2.898 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/out_0_s/CIN
2.943 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/out_0_s/COUT
2.943 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/out_1_s/CIN
2.988 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/out_1_s/COUT
2.988 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/out_2_s/CIN
3.033 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/out_2_s/COUT
3.033 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/out_3_s/CIN
3.078 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/out_3_s/COUT
3.078 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/out_4_s/CIN
3.297 0.219 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/out_4_s/SUM
3.669 0.371 tNET RR 2 sscpll0/u_gwfpll/u_mdiv_code_conv/n18_s/I0
4.204 0.535 tINS RF 1 sscpll0/u_gwfpll/u_mdiv_code_conv/n18_s/COUT
4.204 0.000 tNET FF 2 sscpll0/u_gwfpll/u_mdiv_code_conv/n17_s/CIN
4.249 0.045 tINS FR 1 sscpll0/u_gwfpll/u_mdiv_code_conv/n17_s/COUT
4.249 0.000 tNET RR 2 sscpll0/u_gwfpll/u_mdiv_code_conv/n16_s/CIN
4.294 0.045 tINS RR 1 sscpll0/u_gwfpll/u_mdiv_code_conv/n16_s/COUT
4.294 0.000 tNET RR 2 sscpll0/u_gwfpll/u_mdiv_code_conv/n15_s/CIN
4.339 0.045 tINS RR 1 sscpll0/u_gwfpll/u_mdiv_code_conv/n15_s/COUT
4.339 0.000 tNET RR 2 sscpll0/u_gwfpll/u_mdiv_code_conv/n14_s/CIN
4.559 0.219 tINS RR 1 sscpll0/u_gwfpll/u_mdiv_code_conv/n14_s/SUM
4.930 0.371 tNET RR 1 sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 20.000 active clock edge time
20.000 0.000 sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.371 0.371 tCL RR 117 sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
20.743 0.371 tNET RR 1 sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_5_s0/CLK
20.685 -0.057 tSu 1 sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_5_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.371, 100.000%
Arrival Data Path Delay: cell: 2.729, 65.180%; route: 1.114, 26.599%; tC2Q: 0.344, 8.221%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.371, 100.000%

Path 4

Path Summary:
Slack 15.800
Data Arrival Time 4.885
Data Required Time 20.685
From sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0
To sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_4_s0
Launch Clk sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk[R]
Latch Clk sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.371 0.371 tCL RR 117 sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
0.743 0.371 tNET RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0/CLK
1.087 0.344 tC2Q RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0/Q
1.458 0.371 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_0_s/I1
1.998 0.540 tINS RF 1 sscpll0/u_gwfpll/u_sdm2/error_0_s/COUT
1.998 0.000 tNET FF 2 sscpll0/u_gwfpll/u_sdm2/error_1_s/CIN
2.043 0.045 tINS FR 1 sscpll0/u_gwfpll/u_sdm2/error_1_s/COUT
2.043 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_2_s/CIN
2.088 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
2.088 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
2.133 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
2.133 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
2.178 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
2.178 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
2.223 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
2.223 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
2.268 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
2.268 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
2.313 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
2.313 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
2.358 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
2.358 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
2.403 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_9_s/COUT
2.403 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_10_s/CIN
2.448 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_10_s/COUT
2.448 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_11_s/CIN
2.493 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_11_s/COUT
2.493 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_12_s/CIN
2.538 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_12_s/COUT
2.538 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_13_s/CIN
2.583 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_13_s/COUT
2.583 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_14_s/CIN
2.628 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_14_s/COUT
2.628 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_15_s/CIN
2.673 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_15_s/COUT
2.673 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_16_s/CIN
2.718 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_16_s/COUT
2.718 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_17_s/CIN
2.763 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_17_s/COUT
2.763 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_18_s/CIN
2.808 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_18_s/COUT
2.808 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_19_s/CIN
2.853 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_19_s/COUT
2.853 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_20_s/CIN
2.898 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_20_s/COUT
2.898 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/out_0_s/CIN
2.943 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/out_0_s/COUT
2.943 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/out_1_s/CIN
2.988 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/out_1_s/COUT
2.988 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/out_2_s/CIN
3.033 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/out_2_s/COUT
3.033 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/out_3_s/CIN
3.078 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/out_3_s/COUT
3.078 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/out_4_s/CIN
3.297 0.219 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/out_4_s/SUM
3.669 0.371 tNET RR 2 sscpll0/u_gwfpll/u_mdiv_code_conv/n18_s/I0
4.204 0.535 tINS RF 1 sscpll0/u_gwfpll/u_mdiv_code_conv/n18_s/COUT
4.204 0.000 tNET FF 2 sscpll0/u_gwfpll/u_mdiv_code_conv/n17_s/CIN
4.249 0.045 tINS FR 1 sscpll0/u_gwfpll/u_mdiv_code_conv/n17_s/COUT
4.249 0.000 tNET RR 2 sscpll0/u_gwfpll/u_mdiv_code_conv/n16_s/CIN
4.294 0.045 tINS RR 1 sscpll0/u_gwfpll/u_mdiv_code_conv/n16_s/COUT
4.294 0.000 tNET RR 2 sscpll0/u_gwfpll/u_mdiv_code_conv/n15_s/CIN
4.514 0.219 tINS RR 1 sscpll0/u_gwfpll/u_mdiv_code_conv/n15_s/SUM
4.885 0.371 tNET RR 1 sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 20.000 active clock edge time
20.000 0.000 sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.371 0.371 tCL RR 117 sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
20.743 0.371 tNET RR 1 sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_4_s0/CLK
20.685 -0.057 tSu 1 sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.371, 100.000%
Arrival Data Path Delay: cell: 2.684, 64.801%; route: 1.114, 26.888%; tC2Q: 0.344, 8.311%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.371, 100.000%

Path 5

Path Summary:
Slack 15.845
Data Arrival Time 4.840
Data Required Time 20.685
From sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0
To sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_3_s0
Launch Clk sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk[R]
Latch Clk sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
0.371 0.371 tCL RR 117 sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
0.743 0.371 tNET RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0/CLK
1.087 0.344 tC2Q RR 1 sscpll0/u_gwfpll/u_sdm2/mod_h_inst/out_reg_0_s0/Q
1.458 0.371 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_0_s/I1
1.998 0.540 tINS RF 1 sscpll0/u_gwfpll/u_sdm2/error_0_s/COUT
1.998 0.000 tNET FF 2 sscpll0/u_gwfpll/u_sdm2/error_1_s/CIN
2.043 0.045 tINS FR 1 sscpll0/u_gwfpll/u_sdm2/error_1_s/COUT
2.043 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_2_s/CIN
2.088 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_2_s/COUT
2.088 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_3_s/CIN
2.133 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_3_s/COUT
2.133 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_4_s/CIN
2.178 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_4_s/COUT
2.178 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_5_s/CIN
2.223 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_5_s/COUT
2.223 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_6_s/CIN
2.268 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_6_s/COUT
2.268 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_7_s/CIN
2.313 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_7_s/COUT
2.313 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_8_s/CIN
2.358 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_8_s/COUT
2.358 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_9_s/CIN
2.403 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_9_s/COUT
2.403 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_10_s/CIN
2.448 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_10_s/COUT
2.448 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_11_s/CIN
2.493 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_11_s/COUT
2.493 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_12_s/CIN
2.538 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_12_s/COUT
2.538 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_13_s/CIN
2.583 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_13_s/COUT
2.583 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_14_s/CIN
2.628 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_14_s/COUT
2.628 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_15_s/CIN
2.673 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_15_s/COUT
2.673 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_16_s/CIN
2.718 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_16_s/COUT
2.718 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_17_s/CIN
2.763 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_17_s/COUT
2.763 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_18_s/CIN
2.808 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_18_s/COUT
2.808 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_19_s/CIN
2.853 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_19_s/COUT
2.853 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/error_20_s/CIN
2.898 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/error_20_s/COUT
2.898 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/out_0_s/CIN
2.943 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/out_0_s/COUT
2.943 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/out_1_s/CIN
2.988 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/out_1_s/COUT
2.988 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/out_2_s/CIN
3.033 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/out_2_s/COUT
3.033 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/out_3_s/CIN
3.078 0.045 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/out_3_s/COUT
3.078 0.000 tNET RR 2 sscpll0/u_gwfpll/u_sdm2/out_4_s/CIN
3.297 0.219 tINS RR 1 sscpll0/u_gwfpll/u_sdm2/out_4_s/SUM
3.669 0.371 tNET RR 2 sscpll0/u_gwfpll/u_mdiv_code_conv/n18_s/I0
4.204 0.535 tINS RF 1 sscpll0/u_gwfpll/u_mdiv_code_conv/n18_s/COUT
4.204 0.000 tNET FF 2 sscpll0/u_gwfpll/u_mdiv_code_conv/n17_s/CIN
4.249 0.045 tINS FR 1 sscpll0/u_gwfpll/u_mdiv_code_conv/n17_s/COUT
4.249 0.000 tNET RR 2 sscpll0/u_gwfpll/u_mdiv_code_conv/n16_s/CIN
4.469 0.219 tINS RR 1 sscpll0/u_gwfpll/u_mdiv_code_conv/n16_s/SUM
4.840 0.371 tNET RR 1 sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 20.000 active clock edge time
20.000 0.000 sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk
20.371 0.371 tCL RR 117 sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT
20.743 0.371 tNET RR 1 sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_3_s0/CLK
20.685 -0.057 tSu 1 sscpll0/u_gwfpll/u_mdiv_code_conv/int_o_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.371, 100.000%
Arrival Data Path Delay: cell: 2.639, 64.415%; route: 1.114, 27.183%; tC2Q: 0.344, 8.402%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.371, 100.000%