Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12.03_x64_internal\IDE\ipcore\SSCPLL\data\sscpll.v D:\Gowin\Gowin_V1.9.12.03_x64_internal\IDE\ipcore\SSCPLL\data\sscpll_wrap.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.03 (64-bit) |
| Part Number | GW5AST-LV138FPG676AC1/I0 |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Tue May 19 09:35:04 2026 |
| Legal Announcement | Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | SSCPLL_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.227s, Peak memory usage = 77.211MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 77.211MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 77.211MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 77.211MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 77.211MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 77.211MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 77.211MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 77.211MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 77.211MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 77.211MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 77.211MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 77.211MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.352s, Peak memory usage = 99.074MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 99.074MB Generate output files: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 99.074MB |
| Total Time and Memory Usage | CPU time = 0h 0m 0.636s, Elapsed time = 0h 0m 0.705s, Peak memory usage = 99.074MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 5 |
| I/O Buf | 5 |
| IBUF | 3 |
| OBUF | 2 |
| Register | 156 |
| DFFRE | 52 |
| DFFPE | 1 |
| DFFCE | 103 |
| LUT | 67 |
| LUT2 | 1 |
| LUT3 | 11 |
| LUT4 | 55 |
| ALU | 131 |
| ALU | 131 |
| INV | 17 |
| INV | 17 |
| CLOCK | 1 |
| PLL | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 215(84 LUT, 131 ALU) / 138240 | <1% |
| Register | 156 / 139140 | <1% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 156 / 139140 | <1% |
| BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clkin | Base | 20.000 | 50.000 | 0.000 | 10.000 | clkin_ibuf/I | ||
| 2 | init_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | init_clk_ibuf/I | ||
| 3 | u_gwfpll/u_pll0/PLL_inst/CLKOUT0.default_gen_clk | Generated | 10.000 | 100.000 | 0.000 | 5.000 | clkin_ibuf/I | clkin | u_gwfpll/u_pll0/PLL_inst/CLKOUT0 |
| 4 | u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk | Generated | 20.000 | 50.000 | 0.000 | 10.000 | clkin_ibuf/I | clkin | u_gwfpll/u_pll0/PLL_inst/CLKFBOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | init_clk | 100.000(MHz) | 289.918(MHz) | 4 | TOP |
| 2 | u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk | 50.000(MHz) | 219.424(MHz) | 8 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 6.551 |
| Data Arrival Time | 3.763 |
| Data Required Time | 10.314 |
| From | u_gwfpll/u_pll0/u_pll_init/locksig_0_s0 |
| To | u_gwfpll/u_pll0/u_pll_init/RomAddr_2_s1 |
| Launch Clk | init_clk[R] |
| Latch Clk | init_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | init_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | init_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 39 | init_clk_ibuf/O |
| 0.371 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/locksig_0_s0/CLK |
| 0.715 | 0.344 | tC2Q | RR | 5 | u_gwfpll/u_pll0/u_pll_init/locksig_0_s0/Q |
| 1.087 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n523_s17/I0 |
| 1.608 | 0.521 | tINS | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n523_s17/F |
| 1.979 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n523_s13/I0 |
| 2.500 | 0.521 | tINS | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n523_s13/F |
| 2.871 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n523_s12/I0 |
| 3.392 | 0.521 | tINS | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n523_s12/F |
| 3.763 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/RomAddr_2_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | init_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | init_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 39 | init_clk_ibuf/O |
| 10.371 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/RomAddr_2_s1/CLK |
| 10.314 | -0.057 | tSu | 1 | u_gwfpll/u_pll0/u_pll_init/RomAddr_2_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
| Arrival Data Path Delay: | cell: 1.563, 46.070%; route: 1.485, 43.781%; tC2Q: 0.344, 10.149% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
Path 2
Path Summary:| Slack | 6.615 |
| Data Arrival Time | 3.699 |
| Data Required Time | 10.314 |
| From | u_gwfpll/u_pll0/u_pll_init/state_0_s0 |
| To | u_gwfpll/u_pll0/u_pll_init/RomAddr_0_s1 |
| Launch Clk | init_clk[R] |
| Latch Clk | init_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | init_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | init_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 39 | init_clk_ibuf/O |
| 0.371 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/state_0_s0/CLK |
| 0.715 | 0.344 | tC2Q | RR | 13 | u_gwfpll/u_pll0/u_pll_init/state_0_s0/Q |
| 1.087 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n504_s2/I0 |
| 1.608 | 0.521 | tINS | RR | 3 | u_gwfpll/u_pll0/u_pll_init/n504_s2/F |
| 1.979 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n527_s15/I0 |
| 2.500 | 0.521 | tINS | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n527_s15/F |
| 2.871 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n527_s12/I2 |
| 3.328 | 0.457 | tINS | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n527_s12/F |
| 3.699 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/RomAddr_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | init_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | init_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 39 | init_clk_ibuf/O |
| 10.371 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/RomAddr_0_s1/CLK |
| 10.314 | -0.057 | tSu | 1 | u_gwfpll/u_pll0/u_pll_init/RomAddr_0_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
| Arrival Data Path Delay: | cell: 1.498, 45.030%; route: 1.485, 44.625%; tC2Q: 0.344, 10.345% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
Path 3
Path Summary:| Slack | 6.615 |
| Data Arrival Time | 3.699 |
| Data Required Time | 10.314 |
| From | u_gwfpll/u_pll0/u_pll_init/waitcnt_13_s0 |
| To | u_gwfpll/u_pll0/u_pll_init/Waitlock_s0 |
| Launch Clk | init_clk[R] |
| Latch Clk | init_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | init_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | init_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 39 | init_clk_ibuf/O |
| 0.371 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/waitcnt_13_s0/CLK |
| 0.715 | 0.344 | tC2Q | RR | 2 | u_gwfpll/u_pll0/u_pll_init/waitcnt_13_s0/Q |
| 1.087 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n541_s4/I0 |
| 1.608 | 0.521 | tINS | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n541_s4/F |
| 1.979 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n541_s2/I0 |
| 2.500 | 0.521 | tINS | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n541_s2/F |
| 2.871 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n541_s0/I2 |
| 3.328 | 0.457 | tINS | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n541_s0/F |
| 3.699 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/Waitlock_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | init_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | init_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 39 | init_clk_ibuf/O |
| 10.371 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/Waitlock_s0/CLK |
| 10.314 | -0.057 | tSu | 1 | u_gwfpll/u_pll0/u_pll_init/Waitlock_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
| Arrival Data Path Delay: | cell: 1.498, 45.030%; route: 1.485, 44.625%; tC2Q: 0.344, 10.345% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
Path 4
Path Summary:| Slack | 6.625 |
| Data Arrival Time | 3.689 |
| Data Required Time | 10.314 |
| From | u_gwfpll/u_pll0/u_pll_init/locksig_5_s0 |
| To | u_gwfpll/u_pll0/u_pll_init/RomAddr_1_s1 |
| Launch Clk | init_clk[R] |
| Latch Clk | init_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | init_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | init_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 39 | init_clk_ibuf/O |
| 0.371 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/locksig_5_s0/CLK |
| 0.715 | 0.344 | tC2Q | RR | 7 | u_gwfpll/u_pll0/u_pll_init/locksig_5_s0/Q |
| 1.087 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n525_s16/I0 |
| 1.608 | 0.521 | tINS | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n525_s16/F |
| 1.979 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n525_s14/I1 |
| 2.490 | 0.511 | tINS | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n525_s14/F |
| 2.861 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n525_s12/I2 |
| 3.318 | 0.457 | tINS | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n525_s12/F |
| 3.689 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/RomAddr_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | init_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | init_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 39 | init_clk_ibuf/O |
| 10.371 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/RomAddr_1_s1/CLK |
| 10.314 | -0.057 | tSu | 1 | u_gwfpll/u_pll0/u_pll_init/RomAddr_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
| Arrival Data Path Delay: | cell: 1.488, 44.863%; route: 1.485, 44.761%; tC2Q: 0.344, 10.376% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
Path 5
Path Summary:| Slack | 6.812 |
| Data Arrival Time | 3.502 |
| Data Required Time | 10.314 |
| From | u_gwfpll/u_pll0/u_pll_init/state_1_s0 |
| To | u_gwfpll/u_pll0/u_pll_init/RomAddr_3_s1 |
| Launch Clk | init_clk[R] |
| Latch Clk | init_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | init_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | init_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 39 | init_clk_ibuf/O |
| 0.371 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/state_1_s0/CLK |
| 0.715 | 0.344 | tC2Q | RR | 13 | u_gwfpll/u_pll0/u_pll_init/state_1_s0/Q |
| 1.087 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/RomAddr_3_s4/I0 |
| 1.608 | 0.521 | tINS | RR | 5 | u_gwfpll/u_pll0/u_pll_init/RomAddr_3_s4/F |
| 1.979 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n521_s15/I0 |
| 2.500 | 0.521 | tINS | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n521_s15/F |
| 2.871 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n521_s12/I3 |
| 3.131 | 0.260 | tINS | RR | 1 | u_gwfpll/u_pll0/u_pll_init/n521_s12/F |
| 3.502 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/RomAddr_3_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | init_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | init_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 39 | init_clk_ibuf/O |
| 10.371 | 0.371 | tNET | RR | 1 | u_gwfpll/u_pll0/u_pll_init/RomAddr_3_s1/CLK |
| 10.314 | -0.057 | tSu | 1 | u_gwfpll/u_pll0/u_pll_init/RomAddr_3_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
| Arrival Data Path Delay: | cell: 1.302, 41.574%; route: 1.485, 47.431%; tC2Q: 0.344, 10.995% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |