Power Messages
| Report Title | Power Analysis Report |
| Design File | E:\IP_Release\SSCPLL\1.5.1\ref_design\Gowin_SSCPLL_RefDesign\project\impl\gwsynthesis\fpga_project.vg |
| Physical Constraints File | E:\IP_Release\SSCPLL\1.5.1\ref_design\Gowin_SSCPLL_RefDesign\project\src\fpga.cst |
| Timing Constraints File | --- |
| Tool Version | V1.9.12.03 (64-bit) |
| Part Number | GW5AST-LV138FPG676AC1/I0 |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Tue May 19 09:36:18 2026 |
| Legal Announcement | Copyright (C)2014-2026 Gowin Semiconductor Corporation. All rights reserved. |
Configure Information:
| Grade | Commercial |
| Process | Typical |
| Ambient Temperature | 25.000 |
| Use Custom Theta JA | false |
| Heat Sink | None |
| Air Flow | LFM_0 |
| Use Custom Theta SA | false |
| Board Thermal Model | None |
| Use Custom Theta JB | false |
| Related Vcd File | |
| Related Saif File | |
| Filter Glitches | false |
| Default IO Toggle Rate | 0.125 |
| Default Remain Toggle Rate | 0.125 |
Power Summary
Power Information:
| Total Power (mW) | 111.645 |
| Quiescent Power (mW) | 100.679 |
| Dynamic Power (mW) | 10.966 |
Thermal Information:
| Junction Temperature | 26.365 |
| Theta JA | 12.222 |
| Max Allowed Ambient Temperature | 83.635 |
Supply Information:
| Voltage Source | Voltage | Dynamic Current(mA) | Quiescent Current(mA) | Power(mW) |
|---|---|---|---|---|
| VCC | 0.900 | 11.591 | 80.001 | 82.433 |
| VCCX | 1.800 | 0.104 | 7.200 | 13.147 |
| VCCIO33 | 3.300 | 0.106 | 3.017 | 10.305 |
| VCCLDO | 1.200 | 0.000 | 4.800 | 5.760 |
Power Details
Power By Block Type:
| Block Type | Total Power(mW) | Static Power(mW) | Average Toggle Rate(millions of transitions/sec) |
|---|---|---|---|
| Logic | 0.211 | NA | 6.250 |
| IO | 10.749 | 10.121 | 31.250 |
| PLL | 10.122 | NA | NA |
Power By Hierarchy:
| Hierarchy Entity | Total Power(mW) | Block Dynamic Power(mW) |
|---|---|---|
| top | 10.333 | 10.333(10.332) |
| top/sscpll0/ | 10.332 | 10.332(10.332) |
| top/sscpll0/u_gwfpll/ | 10.332 | 10.332(10.332) |
| top/sscpll0/u_gwfpll/u_mdiv_code_conv/ | 0.009 | 0.009(0.000) |
| top/sscpll0/u_gwfpll/u_pll0/ | 10.157 | 10.157(0.035) |
| top/sscpll0/u_gwfpll/u_pll0/u_pll_init/ | 0.035 | 0.035(0.000) |
| top/sscpll0/u_gwfpll/u_sdm2/ | 0.078 | 0.078(0.034) |
| top/sscpll0/u_gwfpll/u_sdm2/mod_h_inst/ | 0.034 | 0.034(0.000) |
| top/sscpll0/u_gwfpll/u_triangle_codegen/ | 0.088 | 0.088(0.043) |
| top/sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/ | 0.043 | 0.043(0.000) |
Power By Clock Domain:
| Clock Domain | Clock Frequency(Mhz) | Total Dynamic Power(mW) |
|---|---|---|
| sscpll0/u_gwfpll/u_pll0/PLL_inst/CLKFBOUT.default_gen_clk | 50.000 | 0.177 |
| sys_clk | 50.000 | 10.161 |